sc9836.dtsi 4.3 KB

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  1. /*
  2. * Spreadtrum SC9836 SoC DTS file
  3. *
  4. * Copyright (C) 2014, Spreadtrum Communications Inc.
  5. *
  6. * This file is licensed under a dual GPLv2 or X11 license.
  7. */
  8. #include "sharkl64.dtsi"
  9. #include <dt-bindings/interrupt-controller/arm-gic.h>
  10. / {
  11. compatible = "sprd,sc9836";
  12. cpus {
  13. #address-cells = <2>;
  14. #size-cells = <0>;
  15. cpu0: cpu@0 {
  16. device_type = "cpu";
  17. compatible = "arm,cortex-a53", "arm,armv8";
  18. reg = <0x0 0x0>;
  19. enable-method = "psci";
  20. };
  21. cpu1: cpu@1 {
  22. device_type = "cpu";
  23. compatible = "arm,cortex-a53", "arm,armv8";
  24. reg = <0x0 0x1>;
  25. enable-method = "psci";
  26. };
  27. cpu2: cpu@2 {
  28. device_type = "cpu";
  29. compatible = "arm,cortex-a53", "arm,armv8";
  30. reg = <0x0 0x2>;
  31. enable-method = "psci";
  32. };
  33. cpu3: cpu@3 {
  34. device_type = "cpu";
  35. compatible = "arm,cortex-a53", "arm,armv8";
  36. reg = <0x0 0x3>;
  37. enable-method = "psci";
  38. };
  39. };
  40. etf@10003000 {
  41. compatible = "arm,coresight-tmc", "arm,primecell";
  42. reg = <0 0x10003000 0 0x1000>;
  43. clocks = <&clk26mhz>;
  44. clock-names = "apb_pclk";
  45. port {
  46. etf_in: endpoint {
  47. slave-mode;
  48. remote-endpoint = <&funnel_out_port0>;
  49. };
  50. };
  51. };
  52. funnel@10001000 {
  53. compatible = "arm,coresight-funnel", "arm,primecell";
  54. reg = <0 0x10001000 0 0x1000>;
  55. clocks = <&clk26mhz>;
  56. clock-names = "apb_pclk";
  57. ports {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. /* funnel output port */
  61. port@0 {
  62. reg = <0>;
  63. funnel_out_port0: endpoint {
  64. remote-endpoint = <&etf_in>;
  65. };
  66. };
  67. /* funnel input port 0-4 */
  68. port@1 {
  69. reg = <0>;
  70. funnel_in_port0: endpoint {
  71. slave-mode;
  72. remote-endpoint = <&etm0_out>;
  73. };
  74. };
  75. port@2 {
  76. reg = <1>;
  77. funnel_in_port1: endpoint {
  78. slave-mode;
  79. remote-endpoint = <&etm1_out>;
  80. };
  81. };
  82. port@3 {
  83. reg = <2>;
  84. funnel_in_port2: endpoint {
  85. slave-mode;
  86. remote-endpoint = <&etm2_out>;
  87. };
  88. };
  89. port@4 {
  90. reg = <3>;
  91. funnel_in_port3: endpoint {
  92. slave-mode;
  93. remote-endpoint = <&etm3_out>;
  94. };
  95. };
  96. port@5 {
  97. reg = <4>;
  98. funnel_in_port4: endpoint {
  99. slave-mode;
  100. remote-endpoint = <&stm_out>;
  101. };
  102. };
  103. /* Other input ports aren't connected to anyone */
  104. };
  105. };
  106. etm@10440000 {
  107. compatible = "arm,coresight-etm4x", "arm,primecell";
  108. reg = <0 0x10440000 0 0x1000>;
  109. cpu = <&cpu0>;
  110. clocks = <&clk26mhz>;
  111. clock-names = "apb_pclk";
  112. port {
  113. etm0_out: endpoint {
  114. remote-endpoint = <&funnel_in_port0>;
  115. };
  116. };
  117. };
  118. etm@10540000 {
  119. compatible = "arm,coresight-etm4x", "arm,primecell";
  120. reg = <0 0x10540000 0 0x1000>;
  121. cpu = <&cpu1>;
  122. clocks = <&clk26mhz>;
  123. clock-names = "apb_pclk";
  124. port {
  125. etm1_out: endpoint {
  126. remote-endpoint = <&funnel_in_port1>;
  127. };
  128. };
  129. };
  130. etm@10640000 {
  131. compatible = "arm,coresight-etm4x", "arm,primecell";
  132. reg = <0 0x10640000 0 0x1000>;
  133. cpu = <&cpu2>;
  134. clocks = <&clk26mhz>;
  135. clock-names = "apb_pclk";
  136. port {
  137. etm2_out: endpoint {
  138. remote-endpoint = <&funnel_in_port2>;
  139. };
  140. };
  141. };
  142. etm@10740000 {
  143. compatible = "arm,coresight-etm4x", "arm,primecell";
  144. reg = <0 0x10740000 0 0x1000>;
  145. cpu = <&cpu3>;
  146. clocks = <&clk26mhz>;
  147. clock-names = "apb_pclk";
  148. port {
  149. etm3_out: endpoint {
  150. remote-endpoint = <&funnel_in_port3>;
  151. };
  152. };
  153. };
  154. stm@10006000 {
  155. compatible = "arm,coresight-stm", "arm,primecell";
  156. reg = <0 0x10006000 0 0x1000>,
  157. <0 0x01000000 0 0x180000>;
  158. reg-names = "stm-base", "stm-stimulus-base";
  159. clocks = <&clk26mhz>;
  160. clock-names = "apb_pclk";
  161. port {
  162. stm_out: endpoint {
  163. remote-endpoint = <&funnel_in_port4>;
  164. };
  165. };
  166. };
  167. gic: interrupt-controller@12001000 {
  168. compatible = "arm,gic-400";
  169. reg = <0 0x12001000 0 0x1000>,
  170. <0 0x12002000 0 0x2000>,
  171. <0 0x12004000 0 0x2000>,
  172. <0 0x12006000 0 0x2000>;
  173. #interrupt-cells = <3>;
  174. interrupt-controller;
  175. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  176. };
  177. psci {
  178. compatible = "arm,psci";
  179. method = "smc";
  180. cpu_on = <0xc4000003>;
  181. cpu_off = <0x84000002>;
  182. cpu_suspend = <0xc4000001>;
  183. };
  184. timer {
  185. compatible = "arm,armv8-timer";
  186. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  187. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  188. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  189. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  190. };
  191. };