intc.c 4.1 KB

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  1. /*
  2. * Copyright (C) 2006, 2008 Atmel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/syscore_ops.h>
  15. #include <linux/export.h>
  16. #include <asm/io.h>
  17. #include "intc.h"
  18. struct intc {
  19. void __iomem *regs;
  20. struct irq_chip chip;
  21. #ifdef CONFIG_PM
  22. unsigned long suspend_ipr;
  23. unsigned long saved_ipr[64];
  24. #endif
  25. };
  26. extern struct platform_device at32_intc0_device;
  27. /*
  28. * TODO: We may be able to implement mask/unmask by setting IxM flags
  29. * in the status register.
  30. */
  31. static void intc_mask_irq(struct irq_data *d)
  32. {
  33. }
  34. static void intc_unmask_irq(struct irq_data *d)
  35. {
  36. }
  37. static struct intc intc0 = {
  38. .chip = {
  39. .name = "intc",
  40. .irq_mask = intc_mask_irq,
  41. .irq_unmask = intc_unmask_irq,
  42. },
  43. };
  44. /*
  45. * All interrupts go via intc at some point.
  46. */
  47. asmlinkage void do_IRQ(int level, struct pt_regs *regs)
  48. {
  49. struct pt_regs *old_regs;
  50. unsigned int irq;
  51. unsigned long status_reg;
  52. local_irq_disable();
  53. old_regs = set_irq_regs(regs);
  54. irq_enter();
  55. irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
  56. generic_handle_irq(irq);
  57. /*
  58. * Clear all interrupt level masks so that we may handle
  59. * interrupts during softirq processing. If this is a nested
  60. * interrupt, interrupts must stay globally disabled until we
  61. * return.
  62. */
  63. status_reg = sysreg_read(SR);
  64. status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
  65. | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
  66. sysreg_write(SR, status_reg);
  67. irq_exit();
  68. set_irq_regs(old_regs);
  69. }
  70. void __init init_IRQ(void)
  71. {
  72. extern void _evba(void);
  73. extern void irq_level0(void);
  74. struct resource *regs;
  75. struct clk *pclk;
  76. unsigned int i;
  77. u32 offset, readback;
  78. regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
  79. if (!regs) {
  80. printk(KERN_EMERG "intc: no mmio resource defined\n");
  81. goto fail;
  82. }
  83. pclk = clk_get(&at32_intc0_device.dev, "pclk");
  84. if (IS_ERR(pclk)) {
  85. printk(KERN_EMERG "intc: no clock defined\n");
  86. goto fail;
  87. }
  88. clk_enable(pclk);
  89. intc0.regs = ioremap(regs->start, resource_size(regs));
  90. if (!intc0.regs) {
  91. printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
  92. (unsigned long)regs->start);
  93. goto fail;
  94. }
  95. /*
  96. * Initialize all interrupts to level 0 (lowest priority). The
  97. * priority level may be changed by calling
  98. * irq_set_priority().
  99. *
  100. */
  101. offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
  102. for (i = 0; i < NR_INTERNAL_IRQS; i++) {
  103. intc_writel(&intc0, INTPR0 + 4 * i, offset);
  104. readback = intc_readl(&intc0, INTPR0 + 4 * i);
  105. if (readback == offset)
  106. irq_set_chip_and_handler(i, &intc0.chip,
  107. handle_simple_irq);
  108. }
  109. /* Unmask all interrupt levels */
  110. sysreg_write(SR, (sysreg_read(SR)
  111. & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
  112. return;
  113. fail:
  114. panic("Interrupt controller initialization failed!\n");
  115. }
  116. #ifdef CONFIG_PM
  117. void intc_set_suspend_handler(unsigned long offset)
  118. {
  119. intc0.suspend_ipr = offset;
  120. }
  121. static int intc_suspend(void)
  122. {
  123. int i;
  124. if (unlikely(!irqs_disabled())) {
  125. pr_err("intc_suspend: called with interrupts enabled\n");
  126. return -EINVAL;
  127. }
  128. if (unlikely(!intc0.suspend_ipr)) {
  129. pr_err("intc_suspend: suspend_ipr not initialized\n");
  130. return -EINVAL;
  131. }
  132. for (i = 0; i < 64; i++) {
  133. intc0.saved_ipr[i] = intc_readl(&intc0, INTPR0 + 4 * i);
  134. intc_writel(&intc0, INTPR0 + 4 * i, intc0.suspend_ipr);
  135. }
  136. return 0;
  137. }
  138. static void intc_resume(void)
  139. {
  140. int i;
  141. for (i = 0; i < 64; i++)
  142. intc_writel(&intc0, INTPR0 + 4 * i, intc0.saved_ipr[i]);
  143. }
  144. #else
  145. #define intc_suspend NULL
  146. #define intc_resume NULL
  147. #endif
  148. static struct syscore_ops intc_syscore_ops = {
  149. .suspend = intc_suspend,
  150. .resume = intc_resume,
  151. };
  152. static int __init intc_init_syscore(void)
  153. {
  154. register_syscore_ops(&intc_syscore_ops);
  155. return 0;
  156. }
  157. device_initcall(intc_init_syscore);
  158. unsigned long intc_get_pending(unsigned int group)
  159. {
  160. return intc_readl(&intc0, INTREQ0 + 4 * group);
  161. }
  162. EXPORT_SYMBOL_GPL(intc_get_pending);