pio.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470
  1. /*
  2. * Atmel PIO2 Port Multiplexer support
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/export.h>
  13. #include <linux/fs.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/irq.h>
  16. #include <asm/gpio.h>
  17. #include <asm/io.h>
  18. #include <mach/portmux.h>
  19. #include "pio.h"
  20. #define MAX_NR_PIO_DEVICES 8
  21. struct pio_device {
  22. struct gpio_chip chip;
  23. void __iomem *regs;
  24. const struct platform_device *pdev;
  25. struct clk *clk;
  26. u32 pinmux_mask;
  27. char name[8];
  28. };
  29. static struct pio_device pio_dev[MAX_NR_PIO_DEVICES];
  30. static struct pio_device *gpio_to_pio(unsigned int gpio)
  31. {
  32. struct pio_device *pio;
  33. unsigned int index;
  34. index = gpio >> 5;
  35. if (index >= MAX_NR_PIO_DEVICES)
  36. return NULL;
  37. pio = &pio_dev[index];
  38. if (!pio->regs)
  39. return NULL;
  40. return pio;
  41. }
  42. /* Pin multiplexing API */
  43. static DEFINE_SPINLOCK(pio_lock);
  44. void __init at32_select_periph(unsigned int port, u32 pin_mask,
  45. unsigned int periph, unsigned long flags)
  46. {
  47. struct pio_device *pio;
  48. /* assign and verify pio */
  49. pio = gpio_to_pio(port);
  50. if (unlikely(!pio)) {
  51. printk(KERN_WARNING "pio: invalid port %u\n", port);
  52. goto fail;
  53. }
  54. /* Test if any of the requested pins is already muxed */
  55. spin_lock(&pio_lock);
  56. if (unlikely(pio->pinmux_mask & pin_mask)) {
  57. printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
  58. pio->name, pin_mask, pio->pinmux_mask & pin_mask);
  59. spin_unlock(&pio_lock);
  60. goto fail;
  61. }
  62. pio->pinmux_mask |= pin_mask;
  63. /* enable pull ups */
  64. pio_writel(pio, PUER, pin_mask);
  65. /* select either peripheral A or B */
  66. if (periph)
  67. pio_writel(pio, BSR, pin_mask);
  68. else
  69. pio_writel(pio, ASR, pin_mask);
  70. /* enable peripheral control */
  71. pio_writel(pio, PDR, pin_mask);
  72. /* Disable pull ups if not requested. */
  73. if (!(flags & AT32_GPIOF_PULLUP))
  74. pio_writel(pio, PUDR, pin_mask);
  75. spin_unlock(&pio_lock);
  76. return;
  77. fail:
  78. dump_stack();
  79. }
  80. void __init at32_select_gpio(unsigned int pin, unsigned long flags)
  81. {
  82. struct pio_device *pio;
  83. unsigned int pin_index = pin & 0x1f;
  84. u32 mask = 1 << pin_index;
  85. pio = gpio_to_pio(pin);
  86. if (unlikely(!pio)) {
  87. printk("pio: invalid pin %u\n", pin);
  88. goto fail;
  89. }
  90. if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
  91. printk("%s: pin %u is busy\n", pio->name, pin_index);
  92. goto fail;
  93. }
  94. if (flags & AT32_GPIOF_OUTPUT) {
  95. if (flags & AT32_GPIOF_HIGH)
  96. pio_writel(pio, SODR, mask);
  97. else
  98. pio_writel(pio, CODR, mask);
  99. if (flags & AT32_GPIOF_MULTIDRV)
  100. pio_writel(pio, MDER, mask);
  101. else
  102. pio_writel(pio, MDDR, mask);
  103. pio_writel(pio, PUDR, mask);
  104. pio_writel(pio, OER, mask);
  105. } else {
  106. if (flags & AT32_GPIOF_PULLUP)
  107. pio_writel(pio, PUER, mask);
  108. else
  109. pio_writel(pio, PUDR, mask);
  110. if (flags & AT32_GPIOF_DEGLITCH)
  111. pio_writel(pio, IFER, mask);
  112. else
  113. pio_writel(pio, IFDR, mask);
  114. pio_writel(pio, ODR, mask);
  115. }
  116. pio_writel(pio, PER, mask);
  117. return;
  118. fail:
  119. dump_stack();
  120. }
  121. /*
  122. * Undo a previous pin reservation. Will not affect the hardware
  123. * configuration.
  124. */
  125. void at32_deselect_pin(unsigned int pin)
  126. {
  127. struct pio_device *pio;
  128. unsigned int pin_index = pin & 0x1f;
  129. pio = gpio_to_pio(pin);
  130. if (unlikely(!pio)) {
  131. printk("pio: invalid pin %u\n", pin);
  132. dump_stack();
  133. return;
  134. }
  135. clear_bit(pin_index, &pio->pinmux_mask);
  136. }
  137. /* Reserve a pin, preventing anyone else from changing its configuration. */
  138. void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
  139. {
  140. struct pio_device *pio;
  141. /* assign and verify pio */
  142. pio = gpio_to_pio(port);
  143. if (unlikely(!pio)) {
  144. printk(KERN_WARNING "pio: invalid port %u\n", port);
  145. goto fail;
  146. }
  147. /* Test if any of the requested pins is already muxed */
  148. spin_lock(&pio_lock);
  149. if (unlikely(pio->pinmux_mask & pin_mask)) {
  150. printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
  151. pio->name, pin_mask, pio->pinmux_mask & pin_mask);
  152. spin_unlock(&pio_lock);
  153. goto fail;
  154. }
  155. /* Reserve pins */
  156. pio->pinmux_mask |= pin_mask;
  157. spin_unlock(&pio_lock);
  158. return;
  159. fail:
  160. dump_stack();
  161. }
  162. /*--------------------------------------------------------------------------*/
  163. /* GPIO API */
  164. static int direction_input(struct gpio_chip *chip, unsigned offset)
  165. {
  166. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  167. u32 mask = 1 << offset;
  168. if (!(pio_readl(pio, PSR) & mask))
  169. return -EINVAL;
  170. pio_writel(pio, ODR, mask);
  171. return 0;
  172. }
  173. static int gpio_get(struct gpio_chip *chip, unsigned offset)
  174. {
  175. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  176. return (pio_readl(pio, PDSR) >> offset) & 1;
  177. }
  178. static void gpio_set(struct gpio_chip *chip, unsigned offset, int value);
  179. static int direction_output(struct gpio_chip *chip, unsigned offset, int value)
  180. {
  181. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  182. u32 mask = 1 << offset;
  183. if (!(pio_readl(pio, PSR) & mask))
  184. return -EINVAL;
  185. gpio_set(chip, offset, value);
  186. pio_writel(pio, OER, mask);
  187. return 0;
  188. }
  189. static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  190. {
  191. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  192. u32 mask = 1 << offset;
  193. if (value)
  194. pio_writel(pio, SODR, mask);
  195. else
  196. pio_writel(pio, CODR, mask);
  197. }
  198. /*--------------------------------------------------------------------------*/
  199. /* GPIO IRQ support */
  200. static void gpio_irq_mask(struct irq_data *d)
  201. {
  202. unsigned gpio = irq_to_gpio(d->irq);
  203. struct pio_device *pio = &pio_dev[gpio >> 5];
  204. pio_writel(pio, IDR, 1 << (gpio & 0x1f));
  205. }
  206. static void gpio_irq_unmask(struct irq_data *d)
  207. {
  208. unsigned gpio = irq_to_gpio(d->irq);
  209. struct pio_device *pio = &pio_dev[gpio >> 5];
  210. pio_writel(pio, IER, 1 << (gpio & 0x1f));
  211. }
  212. static int gpio_irq_type(struct irq_data *d, unsigned type)
  213. {
  214. if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
  215. return -EINVAL;
  216. return 0;
  217. }
  218. static struct irq_chip gpio_irqchip = {
  219. .name = "gpio",
  220. .irq_mask = gpio_irq_mask,
  221. .irq_unmask = gpio_irq_unmask,
  222. .irq_set_type = gpio_irq_type,
  223. };
  224. static void gpio_irq_handler(struct irq_desc *desc)
  225. {
  226. struct pio_device *pio = irq_desc_get_chip_data(desc);
  227. unsigned gpio_irq;
  228. gpio_irq = (unsigned) irq_desc_get_handler_data(desc);
  229. for (;;) {
  230. u32 isr;
  231. /* ack pending GPIO interrupts */
  232. isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
  233. if (!isr)
  234. break;
  235. do {
  236. int i;
  237. i = ffs(isr) - 1;
  238. isr &= ~(1 << i);
  239. i += gpio_irq;
  240. generic_handle_irq(i);
  241. } while (isr);
  242. }
  243. }
  244. static void __init
  245. gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
  246. {
  247. unsigned i;
  248. irq_set_chip_data(irq, pio);
  249. for (i = 0; i < 32; i++, gpio_irq++) {
  250. irq_set_chip_data(gpio_irq, pio);
  251. irq_set_chip_and_handler(gpio_irq, &gpio_irqchip,
  252. handle_simple_irq);
  253. }
  254. irq_set_chained_handler_and_data(irq, gpio_irq_handler,
  255. (void *)gpio_irq);
  256. }
  257. /*--------------------------------------------------------------------------*/
  258. #ifdef CONFIG_DEBUG_FS
  259. #include <linux/seq_file.h>
  260. /*
  261. * This shows more info than the generic gpio dump code:
  262. * pullups, deglitching, open drain drive.
  263. */
  264. static void pio_bank_show(struct seq_file *s, struct gpio_chip *chip)
  265. {
  266. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  267. u32 psr, osr, imr, pdsr, pusr, ifsr, mdsr;
  268. unsigned i;
  269. u32 mask;
  270. char bank;
  271. psr = pio_readl(pio, PSR);
  272. osr = pio_readl(pio, OSR);
  273. imr = pio_readl(pio, IMR);
  274. pdsr = pio_readl(pio, PDSR);
  275. pusr = pio_readl(pio, PUSR);
  276. ifsr = pio_readl(pio, IFSR);
  277. mdsr = pio_readl(pio, MDSR);
  278. bank = 'A' + pio->pdev->id;
  279. for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
  280. const char *label;
  281. label = gpiochip_is_requested(chip, i);
  282. if (!label && (imr & mask))
  283. label = "[irq]";
  284. if (!label)
  285. continue;
  286. seq_printf(s, " gpio-%-3d P%c%-2d (%-12s) %s %s %s",
  287. chip->base + i, bank, i,
  288. label,
  289. (osr & mask) ? "out" : "in ",
  290. (mask & pdsr) ? "hi" : "lo",
  291. (mask & pusr) ? " " : "up");
  292. if (ifsr & mask)
  293. seq_printf(s, " deglitch");
  294. if ((osr & mdsr) & mask)
  295. seq_printf(s, " open-drain");
  296. if (imr & mask)
  297. seq_printf(s, " irq-%d edge-both",
  298. gpio_to_irq(chip->base + i));
  299. seq_printf(s, "\n");
  300. }
  301. }
  302. #else
  303. #define pio_bank_show NULL
  304. #endif
  305. /*--------------------------------------------------------------------------*/
  306. static int __init pio_probe(struct platform_device *pdev)
  307. {
  308. struct pio_device *pio = NULL;
  309. int irq = platform_get_irq(pdev, 0);
  310. int gpio_irq_base = GPIO_IRQ_BASE + pdev->id * 32;
  311. BUG_ON(pdev->id >= MAX_NR_PIO_DEVICES);
  312. pio = &pio_dev[pdev->id];
  313. BUG_ON(!pio->regs);
  314. pio->chip.label = pio->name;
  315. pio->chip.base = pdev->id * 32;
  316. pio->chip.ngpio = 32;
  317. pio->chip.dev = &pdev->dev;
  318. pio->chip.owner = THIS_MODULE;
  319. pio->chip.direction_input = direction_input;
  320. pio->chip.get = gpio_get;
  321. pio->chip.direction_output = direction_output;
  322. pio->chip.set = gpio_set;
  323. pio->chip.dbg_show = pio_bank_show;
  324. gpiochip_add(&pio->chip);
  325. gpio_irq_setup(pio, irq, gpio_irq_base);
  326. platform_set_drvdata(pdev, pio);
  327. printk(KERN_DEBUG "%s: base 0x%p, irq %d chains %d..%d\n",
  328. pio->name, pio->regs, irq, gpio_irq_base, gpio_irq_base + 31);
  329. return 0;
  330. }
  331. static struct platform_driver pio_driver = {
  332. .driver = {
  333. .name = "pio",
  334. },
  335. };
  336. static int __init pio_init(void)
  337. {
  338. return platform_driver_probe(&pio_driver, pio_probe);
  339. }
  340. postcore_initcall(pio_init);
  341. void __init at32_init_pio(struct platform_device *pdev)
  342. {
  343. struct resource *regs;
  344. struct pio_device *pio;
  345. if (pdev->id >= MAX_NR_PIO_DEVICES) {
  346. dev_err(&pdev->dev, "only %d PIO devices supported\n",
  347. MAX_NR_PIO_DEVICES);
  348. return;
  349. }
  350. pio = &pio_dev[pdev->id];
  351. snprintf(pio->name, sizeof(pio->name), "pio%d", pdev->id);
  352. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  353. if (!regs) {
  354. dev_err(&pdev->dev, "no mmio resource defined\n");
  355. return;
  356. }
  357. pio->clk = clk_get(&pdev->dev, "mck");
  358. if (IS_ERR(pio->clk))
  359. /*
  360. * This is a fatal error, but if we continue we might
  361. * be so lucky that we manage to initialize the
  362. * console and display this message...
  363. */
  364. dev_err(&pdev->dev, "no mck clock defined\n");
  365. else
  366. clk_enable(pio->clk);
  367. pio->pdev = pdev;
  368. pio->regs = ioremap(regs->start, resource_size(regs));
  369. /* start with irqs disabled and acked */
  370. pio_writel(pio, IDR, ~0UL);
  371. (void) pio_readl(pio, ISR);
  372. }