bcm6328.dtsi 1.4 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6328";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <160000000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips4350";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips4350";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. clocks {
  21. periph_clk: periph_clk {
  22. compatible = "fixed-clock";
  23. #clock-cells = <0>;
  24. clock-frequency = <50000000>;
  25. };
  26. };
  27. aliases {
  28. uart0 = &uart0;
  29. };
  30. cpu_intc: cpu_intc {
  31. #address-cells = <0>;
  32. compatible = "mti,cpu-interrupt-controller";
  33. interrupt-controller;
  34. #interrupt-cells = <1>;
  35. };
  36. ubus {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. compatible = "simple-bus";
  40. ranges;
  41. periph_intc: periph_intc@10000020 {
  42. compatible = "brcm,bcm3380-l2-intc";
  43. reg = <0x10000024 0x4 0x1000002c 0x4>,
  44. <0x10000020 0x4 0x10000028 0x4>;
  45. interrupt-controller;
  46. #interrupt-cells = <1>;
  47. interrupt-parent = <&cpu_intc>;
  48. interrupts = <2>;
  49. };
  50. uart0: serial@10000100 {
  51. compatible = "brcm,bcm6345-uart";
  52. reg = <0x10000100 0x18>;
  53. interrupt-parent = <&periph_intc>;
  54. interrupts = <28>;
  55. clocks = <&periph_clk>;
  56. status = "disabled";
  57. };
  58. timer: timer@10000040 {
  59. compatible = "syscon";
  60. reg = <0x10000040 0x2c>;
  61. little-endian;
  62. };
  63. reboot {
  64. compatible = "syscon-reboot";
  65. regmap = <&timer>;
  66. offset = <0x28>;
  67. mask = <0x1>;
  68. };
  69. };
  70. };