bcm7125.dtsi 2.7 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm7125";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <202500000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips4380";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips4380";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. aliases {
  21. uart0 = &uart0;
  22. };
  23. cpu_intc: cpu_intc {
  24. #address-cells = <0>;
  25. compatible = "mti,cpu-interrupt-controller";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. };
  29. clocks {
  30. uart_clk: uart_clk {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <81000000>;
  34. };
  35. };
  36. rdb {
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. compatible = "simple-bus";
  40. ranges = <0 0x10000000 0x01000000>;
  41. periph_intc: periph_intc@441400 {
  42. compatible = "brcm,bcm7038-l1-intc";
  43. reg = <0x441400 0x30>, <0x441600 0x30>;
  44. interrupt-controller;
  45. #interrupt-cells = <1>;
  46. interrupt-parent = <&cpu_intc>;
  47. interrupts = <2>, <3>;
  48. };
  49. sun_l2_intc: sun_l2_intc@401800 {
  50. compatible = "brcm,l2-intc";
  51. reg = <0x401800 0x30>;
  52. interrupt-controller;
  53. #interrupt-cells = <1>;
  54. interrupt-parent = <&periph_intc>;
  55. interrupts = <23>;
  56. };
  57. gisb-arb@400000 {
  58. compatible = "brcm,bcm7400-gisb-arb";
  59. reg = <0x400000 0xdc>;
  60. native-endian;
  61. interrupt-parent = <&sun_l2_intc>;
  62. interrupts = <0>, <2>;
  63. brcm,gisb-arb-master-mask = <0x2f7>;
  64. brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0",
  65. "bsp_0", "rdc_0", "rptd_0",
  66. "avd_0", "jtag_0";
  67. };
  68. upg_irq0_intc: upg_irq0_intc@406780 {
  69. compatible = "brcm,bcm7120-l2-intc";
  70. reg = <0x406780 0x8>;
  71. brcm,int-map-mask = <0x44>;
  72. brcm,int-fwd-mask = <0x70000>;
  73. interrupt-controller;
  74. #interrupt-cells = <1>;
  75. interrupt-parent = <&periph_intc>;
  76. interrupts = <18>;
  77. };
  78. sun_top_ctrl: syscon@404000 {
  79. compatible = "brcm,bcm7125-sun-top-ctrl", "syscon";
  80. reg = <0x404000 0x60c>;
  81. little-endian;
  82. };
  83. reboot {
  84. compatible = "brcm,bcm7038-reboot";
  85. syscon = <&sun_top_ctrl 0x8 0x14>;
  86. };
  87. uart0: serial@406b00 {
  88. compatible = "ns16550a";
  89. reg = <0x406b00 0x20>;
  90. reg-io-width = <0x4>;
  91. reg-shift = <0x2>;
  92. native-endian;
  93. interrupt-parent = <&periph_intc>;
  94. interrupts = <21>;
  95. clocks = <&uart_clk>;
  96. status = "disabled";
  97. };
  98. ehci0: usb@488300 {
  99. compatible = "brcm,bcm7125-ehci", "generic-ehci";
  100. reg = <0x488300 0x100>;
  101. native-endian;
  102. interrupt-parent = <&periph_intc>;
  103. interrupts = <60>;
  104. status = "disabled";
  105. };
  106. ohci0: usb@488400 {
  107. compatible = "brcm,bcm7125-ohci", "generic-ohci";
  108. reg = <0x488400 0x100>;
  109. native-endian;
  110. interrupt-parent = <&periph_intc>;
  111. interrupts = <61>;
  112. status = "disabled";
  113. };
  114. };
  115. };