bcm7346.dtsi 7.8 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm7346";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. mips-hpt-frequency = <163125000>;
  9. cpu@0 {
  10. compatible = "brcm,bmips5000";
  11. device_type = "cpu";
  12. reg = <0>;
  13. };
  14. cpu@1 {
  15. compatible = "brcm,bmips5000";
  16. device_type = "cpu";
  17. reg = <1>;
  18. };
  19. };
  20. aliases {
  21. uart0 = &uart0;
  22. uart1 = &uart1;
  23. uart2 = &uart2;
  24. };
  25. cpu_intc: cpu_intc {
  26. #address-cells = <0>;
  27. compatible = "mti,cpu-interrupt-controller";
  28. interrupt-controller;
  29. #interrupt-cells = <1>;
  30. };
  31. clocks {
  32. uart_clk: uart_clk {
  33. compatible = "fixed-clock";
  34. #clock-cells = <0>;
  35. clock-frequency = <81000000>;
  36. };
  37. };
  38. rdb {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. compatible = "simple-bus";
  42. ranges = <0 0x10000000 0x01000000>;
  43. periph_intc: periph_intc@411400 {
  44. compatible = "brcm,bcm7038-l1-intc";
  45. reg = <0x411400 0x30>, <0x411600 0x30>;
  46. interrupt-controller;
  47. #interrupt-cells = <1>;
  48. interrupt-parent = <&cpu_intc>;
  49. interrupts = <2>, <3>;
  50. };
  51. sun_l2_intc: sun_l2_intc@403000 {
  52. compatible = "brcm,l2-intc";
  53. reg = <0x403000 0x30>;
  54. interrupt-controller;
  55. #interrupt-cells = <1>;
  56. interrupt-parent = <&periph_intc>;
  57. interrupts = <51>;
  58. };
  59. gisb-arb@400000 {
  60. compatible = "brcm,bcm7400-gisb-arb";
  61. reg = <0x400000 0xdc>;
  62. native-endian;
  63. interrupt-parent = <&sun_l2_intc>;
  64. interrupts = <0>, <2>;
  65. brcm,gisb-arb-master-mask = <0x673>;
  66. brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  67. "rdc_0", "raaga_0",
  68. "jtag_0", "svd_0";
  69. };
  70. upg_irq0_intc: upg_irq0_intc@406780 {
  71. compatible = "brcm,bcm7120-l2-intc";
  72. reg = <0x406780 0x8>;
  73. brcm,int-map-mask = <0x44>, <0xf000000>;
  74. brcm,int-fwd-mask = <0x70000>;
  75. interrupt-controller;
  76. #interrupt-cells = <1>;
  77. interrupt-parent = <&periph_intc>;
  78. interrupts = <59>, <57>;
  79. interrupt-names = "upg_main", "upg_bsc";
  80. };
  81. upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
  82. compatible = "brcm,bcm7120-l2-intc";
  83. reg = <0x408b80 0x8>;
  84. brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
  85. brcm,int-fwd-mask = <0>;
  86. brcm,irq-can-wake;
  87. interrupt-controller;
  88. #interrupt-cells = <1>;
  89. interrupt-parent = <&periph_intc>;
  90. interrupts = <60>, <58>, <62>;
  91. interrupt-names = "upg_main_aon", "upg_bsc_aon",
  92. "upg_spi";
  93. };
  94. sun_top_ctrl: syscon@404000 {
  95. compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
  96. reg = <0x404000 0x51c>;
  97. little-endian;
  98. };
  99. reboot {
  100. compatible = "brcm,brcmstb-reboot";
  101. syscon = <&sun_top_ctrl 0x304 0x308>;
  102. };
  103. uart0: serial@406900 {
  104. compatible = "ns16550a";
  105. reg = <0x406900 0x20>;
  106. reg-io-width = <0x4>;
  107. reg-shift = <0x2>;
  108. native-endian;
  109. interrupt-parent = <&periph_intc>;
  110. interrupts = <64>;
  111. clocks = <&uart_clk>;
  112. status = "disabled";
  113. };
  114. uart1: serial@406940 {
  115. compatible = "ns16550a";
  116. reg = <0x406940 0x20>;
  117. reg-io-width = <0x4>;
  118. reg-shift = <0x2>;
  119. native-endian;
  120. interrupt-parent = <&periph_intc>;
  121. interrupts = <65>;
  122. clocks = <&uart_clk>;
  123. status = "disabled";
  124. };
  125. uart2: serial@406980 {
  126. compatible = "ns16550a";
  127. reg = <0x406980 0x20>;
  128. reg-io-width = <0x4>;
  129. reg-shift = <0x2>;
  130. native-endian;
  131. interrupt-parent = <&periph_intc>;
  132. interrupts = <66>;
  133. clocks = <&uart_clk>;
  134. status = "disabled";
  135. };
  136. bsca: i2c@406200 {
  137. clock-frequency = <390000>;
  138. compatible = "brcm,brcmstb-i2c";
  139. interrupt-parent = <&upg_irq0_intc>;
  140. reg = <0x406200 0x58>;
  141. interrupts = <24>;
  142. interrupt-names = "upg_bsca";
  143. status = "disabled";
  144. };
  145. bscb: i2c@406280 {
  146. clock-frequency = <390000>;
  147. compatible = "brcm,brcmstb-i2c";
  148. interrupt-parent = <&upg_irq0_intc>;
  149. reg = <0x406280 0x58>;
  150. interrupts = <25>;
  151. interrupt-names = "upg_bscb";
  152. status = "disabled";
  153. };
  154. bscc: i2c@406300 {
  155. clock-frequency = <390000>;
  156. compatible = "brcm,brcmstb-i2c";
  157. interrupt-parent = <&upg_irq0_intc>;
  158. reg = <0x406300 0x58>;
  159. interrupts = <26>;
  160. interrupt-names = "upg_bscc";
  161. status = "disabled";
  162. };
  163. bscd: i2c@406380 {
  164. clock-frequency = <390000>;
  165. compatible = "brcm,brcmstb-i2c";
  166. interrupt-parent = <&upg_irq0_intc>;
  167. reg = <0x406380 0x58>;
  168. interrupts = <27>;
  169. interrupt-names = "upg_bscd";
  170. status = "disabled";
  171. };
  172. bsce: i2c@408980 {
  173. clock-frequency = <390000>;
  174. compatible = "brcm,brcmstb-i2c";
  175. interrupt-parent = <&upg_aon_irq0_intc>;
  176. reg = <0x408980 0x58>;
  177. interrupts = <27>;
  178. interrupt-names = "upg_bsce";
  179. status = "disabled";
  180. };
  181. enet0: ethernet@430000 {
  182. phy-mode = "internal";
  183. phy-handle = <&phy1>;
  184. mac-address = [ 00 10 18 36 23 1a ];
  185. compatible = "brcm,genet-v2";
  186. #address-cells = <0x1>;
  187. #size-cells = <0x1>;
  188. reg = <0x430000 0x4c8c>;
  189. interrupts = <24>, <25>;
  190. interrupt-parent = <&periph_intc>;
  191. status = "disabled";
  192. mdio@e14 {
  193. compatible = "brcm,genet-mdio-v2";
  194. #address-cells = <0x1>;
  195. #size-cells = <0x0>;
  196. reg = <0xe14 0x8>;
  197. phy1: ethernet-phy@1 {
  198. max-speed = <100>;
  199. reg = <0x1>;
  200. compatible = "brcm,40nm-ephy",
  201. "ethernet-phy-ieee802.3-c22";
  202. };
  203. };
  204. };
  205. ehci0: usb@480300 {
  206. compatible = "brcm,bcm7346-ehci", "generic-ehci";
  207. reg = <0x480300 0x100>;
  208. native-endian;
  209. interrupt-parent = <&periph_intc>;
  210. interrupts = <68>;
  211. status = "disabled";
  212. };
  213. ohci0: usb@480400 {
  214. compatible = "brcm,bcm7346-ohci", "generic-ohci";
  215. reg = <0x480400 0x100>;
  216. native-endian;
  217. no-big-frame-no;
  218. interrupt-parent = <&periph_intc>;
  219. interrupts = <70>;
  220. status = "disabled";
  221. };
  222. ehci1: usb@480500 {
  223. compatible = "brcm,bcm7346-ehci", "generic-ehci";
  224. reg = <0x480500 0x100>;
  225. native-endian;
  226. interrupt-parent = <&periph_intc>;
  227. interrupts = <69>;
  228. status = "disabled";
  229. };
  230. ohci1: usb@480600 {
  231. compatible = "brcm,bcm7346-ohci", "generic-ohci";
  232. reg = <0x480600 0x100>;
  233. native-endian;
  234. no-big-frame-no;
  235. interrupt-parent = <&periph_intc>;
  236. interrupts = <71>;
  237. status = "disabled";
  238. };
  239. ehci2: usb@490300 {
  240. compatible = "brcm,bcm7346-ehci", "generic-ehci";
  241. reg = <0x490300 0x100>;
  242. native-endian;
  243. interrupt-parent = <&periph_intc>;
  244. interrupts = <73>;
  245. status = "disabled";
  246. };
  247. ohci2: usb@490400 {
  248. compatible = "brcm,bcm7346-ohci", "generic-ohci";
  249. reg = <0x490400 0x100>;
  250. native-endian;
  251. no-big-frame-no;
  252. interrupt-parent = <&periph_intc>;
  253. interrupts = <75>;
  254. status = "disabled";
  255. };
  256. ehci3: usb@490500 {
  257. compatible = "brcm,bcm7346-ehci", "generic-ehci";
  258. reg = <0x490500 0x100>;
  259. native-endian;
  260. interrupt-parent = <&periph_intc>;
  261. interrupts = <74>;
  262. status = "disabled";
  263. };
  264. ohci3: usb@490600 {
  265. compatible = "brcm,bcm7346-ohci", "generic-ohci";
  266. reg = <0x490600 0x100>;
  267. native-endian;
  268. no-big-frame-no;
  269. interrupt-parent = <&periph_intc>;
  270. interrupts = <76>;
  271. status = "disabled";
  272. };
  273. sata: sata@181000 {
  274. compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
  275. reg-names = "ahci", "top-ctrl";
  276. reg = <0x181000 0xa9c>, <0x180020 0x1c>;
  277. interrupt-parent = <&periph_intc>;
  278. interrupts = <40>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. brcm,broken-ncq;
  282. brcm,broken-phy;
  283. status = "disabled";
  284. sata0: sata-port@0 {
  285. reg = <0>;
  286. phys = <&sata_phy0>;
  287. };
  288. sata1: sata-port@1 {
  289. reg = <1>;
  290. phys = <&sata_phy1>;
  291. };
  292. };
  293. sata_phy: sata-phy@1800000 {
  294. compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
  295. reg = <0x180100 0x0eff>;
  296. reg-names = "phy";
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. status = "disabled";
  300. sata_phy0: sata-phy@0 {
  301. reg = <0>;
  302. #phy-cells = <0>;
  303. };
  304. sata_phy1: sata-phy@1 {
  305. reg = <1>;
  306. #phy-cells = <0>;
  307. };
  308. };
  309. };
  310. };