danube.dtsi 2.1 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "lantiq,xway", "lantiq,danube";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24Kc";
  8. };
  9. };
  10. biu@1F800000 {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "lantiq,biu", "simple-bus";
  14. reg = <0x1F800000 0x800000>;
  15. ranges = <0x0 0x1F800000 0x7FFFFF>;
  16. icu0: icu@80200 {
  17. #interrupt-cells = <1>;
  18. interrupt-controller;
  19. compatible = "lantiq,icu";
  20. reg = <0x80200 0x120>;
  21. };
  22. watchdog@803F0 {
  23. compatible = "lantiq,wdt";
  24. reg = <0x803F0 0x10>;
  25. };
  26. };
  27. sram@1F000000 {
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. compatible = "lantiq,sram";
  31. reg = <0x1F000000 0x800000>;
  32. ranges = <0x0 0x1F000000 0x7FFFFF>;
  33. eiu0: eiu@101000 {
  34. #interrupt-cells = <1>;
  35. interrupt-controller;
  36. interrupt-parent;
  37. compatible = "lantiq,eiu-xway";
  38. reg = <0x101000 0x1000>;
  39. };
  40. pmu0: pmu@102000 {
  41. compatible = "lantiq,pmu-xway";
  42. reg = <0x102000 0x1000>;
  43. };
  44. cgu0: cgu@103000 {
  45. compatible = "lantiq,cgu-xway";
  46. reg = <0x103000 0x1000>;
  47. #clock-cells = <1>;
  48. };
  49. rcu0: rcu@203000 {
  50. compatible = "lantiq,rcu-xway";
  51. reg = <0x203000 0x1000>;
  52. };
  53. };
  54. fpi@10000000 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "lantiq,fpi", "simple-bus";
  58. ranges = <0x0 0x10000000 0xEEFFFFF>;
  59. reg = <0x10000000 0xEF00000>;
  60. gptu@E100A00 {
  61. compatible = "lantiq,gptu-xway";
  62. reg = <0xE100A00 0x100>;
  63. };
  64. serial@E100C00 {
  65. compatible = "lantiq,asc";
  66. reg = <0xE100C00 0x400>;
  67. interrupt-parent = <&icu0>;
  68. interrupts = <112 113 114>;
  69. };
  70. dma0: dma@E104100 {
  71. compatible = "lantiq,dma-xway";
  72. reg = <0xE104100 0x800>;
  73. };
  74. ebu0: ebu@E105300 {
  75. compatible = "lantiq,ebu-xway";
  76. reg = <0xE105300 0x100>;
  77. };
  78. pci0: pci@E105400 {
  79. #address-cells = <3>;
  80. #size-cells = <2>;
  81. #interrupt-cells = <1>;
  82. compatible = "lantiq,pci-xway";
  83. bus-range = <0x0 0x0>;
  84. ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
  85. 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
  86. reg = <0x7000000 0x8000 /* config space */
  87. 0xE105400 0x400>; /* pci bridge */
  88. };
  89. };
  90. };