ar9132.dtsi 2.5 KB

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  1. / {
  2. compatible = "qca,ar9132";
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu@0 {
  9. device_type = "cpu";
  10. compatible = "mips,mips24Kc";
  11. reg = <0>;
  12. };
  13. };
  14. cpuintc: interrupt-controller {
  15. compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
  16. interrupt-controller;
  17. #interrupt-cells = <1>;
  18. qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
  19. qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
  20. <&ddr_ctrl 0>, <&ddr_ctrl 1>;
  21. };
  22. ahb {
  23. compatible = "simple-bus";
  24. ranges;
  25. #address-cells = <1>;
  26. #size-cells = <1>;
  27. interrupt-parent = <&cpuintc>;
  28. apb {
  29. compatible = "simple-bus";
  30. ranges;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. interrupt-parent = <&miscintc>;
  34. ddr_ctrl: memory-controller@18000000 {
  35. compatible = "qca,ar9132-ddr-controller",
  36. "qca,ar7240-ddr-controller";
  37. reg = <0x18000000 0x100>;
  38. #qca,ddr-wb-channel-cells = <1>;
  39. };
  40. uart@18020000 {
  41. compatible = "ns8250";
  42. reg = <0x18020000 0x20>;
  43. interrupts = <3>;
  44. clocks = <&pll 2>;
  45. clock-names = "uart";
  46. reg-io-width = <4>;
  47. reg-shift = <2>;
  48. no-loopback-test;
  49. status = "disabled";
  50. };
  51. gpio: gpio@18040000 {
  52. compatible = "qca,ar9132-gpio",
  53. "qca,ar7100-gpio";
  54. reg = <0x18040000 0x30>;
  55. interrupts = <2>;
  56. ngpios = <22>;
  57. gpio-controller;
  58. #gpio-cells = <2>;
  59. interrupt-controller;
  60. #interrupt-cells = <2>;
  61. };
  62. pll: pll-controller@18050000 {
  63. compatible = "qca,ar9132-ppl",
  64. "qca,ar9130-pll";
  65. reg = <0x18050000 0x20>;
  66. clock-names = "ref";
  67. /* The board must provides the ref clock */
  68. #clock-cells = <1>;
  69. clock-output-names = "cpu", "ddr", "ahb";
  70. };
  71. wdt@18060008 {
  72. compatible = "qca,ar7130-wdt";
  73. reg = <0x18060008 0x8>;
  74. interrupts = <4>;
  75. clocks = <&pll 2>;
  76. clock-names = "wdt";
  77. };
  78. miscintc: interrupt-controller@18060010 {
  79. compatible = "qca,ar9132-misc-intc",
  80. "qca,ar7100-misc-intc";
  81. reg = <0x18060010 0x8>;
  82. interrupt-parent = <&cpuintc>;
  83. interrupts = <6>;
  84. interrupt-controller;
  85. #interrupt-cells = <1>;
  86. };
  87. rst: reset-controller@1806001c {
  88. compatible = "qca,ar9132-reset",
  89. "qca,ar7100-reset";
  90. reg = <0x1806001c 0x4>;
  91. #reset-cells = <1>;
  92. };
  93. };
  94. spi@1f000000 {
  95. compatible = "qca,ar9132-spi", "qca,ar7100-spi";
  96. reg = <0x1f000000 0x10>;
  97. clocks = <&pll 2>;
  98. clock-names = "ahb";
  99. status = "disabled";
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. };
  103. };
  104. };