cuboot-acadia.c 4.8 KB

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  1. /*
  2. * Old U-boot compatibility for Acadia
  3. *
  4. * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
  5. *
  6. * Copyright 2008 IBM Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published
  10. * by the Free Software Foundation.
  11. */
  12. #include "ops.h"
  13. #include "io.h"
  14. #include "dcr.h"
  15. #include "stdio.h"
  16. #include "4xx.h"
  17. #include "44x.h"
  18. #include "cuboot.h"
  19. #define TARGET_4xx
  20. #include "ppcboot.h"
  21. static bd_t bd;
  22. #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
  23. #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
  24. #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
  25. #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
  26. #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
  27. #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
  28. #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
  29. #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
  30. #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
  31. #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
  32. #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
  33. #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
  34. #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
  35. static void get_clocks(void)
  36. {
  37. unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
  38. unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
  39. unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
  40. unsigned long div; /* total divisor udiv * bdiv */
  41. unsigned long umin; /* minimum udiv */
  42. unsigned short diff; /* smallest diff */
  43. unsigned long udiv; /* best udiv */
  44. unsigned short idiff; /* current diff */
  45. unsigned short ibdiv; /* current bdiv */
  46. unsigned long est; /* current estimate */
  47. unsigned long baud;
  48. void *np;
  49. /* read the sysclk value from the CPLD */
  50. sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
  51. /*
  52. * Read PLL Mode registers
  53. */
  54. cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
  55. cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
  56. /*
  57. * Determine forward divider A
  58. */
  59. pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
  60. /*
  61. * Determine forward divider B
  62. */
  63. pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
  64. if (pllFwdDivB == 0)
  65. pllFwdDivB = 8;
  66. /*
  67. * Determine FBK_DIV.
  68. */
  69. pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
  70. if (pllFbkDiv == 0)
  71. pllFbkDiv = 256;
  72. /*
  73. * Read CPR_PRIMAD register
  74. */
  75. cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
  76. /*
  77. * Determine PLB_DIV.
  78. */
  79. pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
  80. if (pllPlbDiv == 0)
  81. pllPlbDiv = 16;
  82. /*
  83. * Determine EXTBUS_DIV.
  84. */
  85. pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
  86. if (pllExtBusDiv == 0)
  87. pllExtBusDiv = 16;
  88. /*
  89. * Determine OPB_DIV.
  90. */
  91. pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
  92. if (pllOpbDiv == 0)
  93. pllOpbDiv = 16;
  94. /* There is a bug in U-Boot that prevents us from using
  95. * bd.bi_opbfreq because U-Boot doesn't populate it for
  96. * 405EZ. We get to calculate it, yay!
  97. */
  98. freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
  99. freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
  100. plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
  101. pllFwdDivB : pllFwdDiv) *
  102. pllFbkDiv) / pllFwdDivB);
  103. np = find_node_by_alias("serial0");
  104. if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
  105. fatal("no current-speed property\n\r");
  106. udiv = 256; /* Assume lowest possible serial clk */
  107. div = plloutb / (16 * baud); /* total divisor */
  108. umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */
  109. diff = 256; /* highest possible */
  110. /* i is the test udiv value -- start with the largest
  111. * possible (256) to minimize serial clock and constrain
  112. * search to umin.
  113. */
  114. for (i = 256; i > umin; i--) {
  115. ibdiv = div / i;
  116. est = i * ibdiv;
  117. idiff = (est > div) ? (est-div) : (div-est);
  118. if (idiff == 0) {
  119. udiv = i;
  120. break; /* can't do better */
  121. } else if (idiff < diff) {
  122. udiv = i; /* best so far */
  123. diff = idiff; /* update lowest diff*/
  124. }
  125. }
  126. freqUART = plloutb / udiv;
  127. dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
  128. dt_fixup_clock("/plb/ebc", freqEBC);
  129. dt_fixup_clock("/plb/opb", freqOPB);
  130. dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
  131. dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
  132. }
  133. static void acadia_fixups(void)
  134. {
  135. dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
  136. get_clocks();
  137. dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
  138. }
  139. void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  140. unsigned long r6, unsigned long r7)
  141. {
  142. CUBOOT_INIT();
  143. platform_ops.fixups = acadia_fixups;
  144. platform_ops.exit = ibm40x_dbcr_reset;
  145. fdt_init(_dtb_start);
  146. serial_console_init();
  147. }