lite5200_pm.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. #include <linux/init.h>
  2. #include <linux/suspend.h>
  3. #include <asm/io.h>
  4. #include <asm/time.h>
  5. #include <asm/mpc52xx.h>
  6. #include <asm/switch_to.h>
  7. /* defined in lite5200_sleep.S and only used here */
  8. extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
  9. static struct mpc52xx_cdm __iomem *cdm;
  10. static struct mpc52xx_intr __iomem *pic;
  11. static struct mpc52xx_sdma __iomem *bes;
  12. static struct mpc52xx_xlb __iomem *xlb;
  13. static struct mpc52xx_gpio __iomem *gps;
  14. static struct mpc52xx_gpio_wkup __iomem *gpw;
  15. static void __iomem *pci;
  16. static void __iomem *sram;
  17. static const int sram_size = 0x4000; /* 16 kBytes */
  18. static void __iomem *mbar;
  19. static suspend_state_t lite5200_pm_target_state;
  20. static int lite5200_pm_valid(suspend_state_t state)
  21. {
  22. switch (state) {
  23. case PM_SUSPEND_STANDBY:
  24. case PM_SUSPEND_MEM:
  25. return 1;
  26. default:
  27. return 0;
  28. }
  29. }
  30. static int lite5200_pm_begin(suspend_state_t state)
  31. {
  32. if (lite5200_pm_valid(state)) {
  33. lite5200_pm_target_state = state;
  34. return 0;
  35. }
  36. return -EINVAL;
  37. }
  38. static int lite5200_pm_prepare(void)
  39. {
  40. struct device_node *np;
  41. const struct of_device_id immr_ids[] = {
  42. { .compatible = "fsl,mpc5200-immr", },
  43. { .compatible = "fsl,mpc5200b-immr", },
  44. { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
  45. { .type = "builtin", .compatible = "mpc5200", }, /* efika */
  46. {}
  47. };
  48. u64 regaddr64 = 0;
  49. const u32 *regaddr_p;
  50. /* deep sleep? let mpc52xx code handle that */
  51. if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
  52. return mpc52xx_pm_prepare();
  53. if (lite5200_pm_target_state != PM_SUSPEND_MEM)
  54. return -EINVAL;
  55. /* map registers */
  56. np = of_find_matching_node(NULL, immr_ids);
  57. regaddr_p = of_get_address(np, 0, NULL, NULL);
  58. if (regaddr_p)
  59. regaddr64 = of_translate_address(np, regaddr_p);
  60. of_node_put(np);
  61. mbar = ioremap((u32) regaddr64, 0xC000);
  62. if (!mbar) {
  63. printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
  64. return -ENOSYS;
  65. }
  66. cdm = mbar + 0x200;
  67. pic = mbar + 0x500;
  68. gps = mbar + 0xb00;
  69. gpw = mbar + 0xc00;
  70. pci = mbar + 0xd00;
  71. bes = mbar + 0x1200;
  72. xlb = mbar + 0x1f00;
  73. sram = mbar + 0x8000;
  74. return 0;
  75. }
  76. /* save and restore registers not bound to any real devices */
  77. static struct mpc52xx_cdm scdm;
  78. static struct mpc52xx_intr spic;
  79. static struct mpc52xx_sdma sbes;
  80. static struct mpc52xx_xlb sxlb;
  81. static struct mpc52xx_gpio sgps;
  82. static struct mpc52xx_gpio_wkup sgpw;
  83. static char spci[0x200];
  84. static void lite5200_save_regs(void)
  85. {
  86. _memcpy_fromio(&spic, pic, sizeof(*pic));
  87. _memcpy_fromio(&sbes, bes, sizeof(*bes));
  88. _memcpy_fromio(&scdm, cdm, sizeof(*cdm));
  89. _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
  90. _memcpy_fromio(&sgps, gps, sizeof(*gps));
  91. _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
  92. _memcpy_fromio(spci, pci, 0x200);
  93. _memcpy_fromio(saved_sram, sram, sram_size);
  94. }
  95. static void lite5200_restore_regs(void)
  96. {
  97. int i;
  98. _memcpy_toio(sram, saved_sram, sram_size);
  99. /* PCI Configuration */
  100. _memcpy_toio(pci, spci, 0x200);
  101. /*
  102. * GPIOs. Interrupt Master Enable has higher address then other
  103. * registers, so just memcpy is ok.
  104. */
  105. _memcpy_toio(gpw, &sgpw, sizeof(*gpw));
  106. _memcpy_toio(gps, &sgps, sizeof(*gps));
  107. /* XLB Arbitrer */
  108. out_be32(&xlb->snoop_window, sxlb.snoop_window);
  109. out_be32(&xlb->master_priority, sxlb.master_priority);
  110. out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
  111. /* enable */
  112. out_be32(&xlb->int_enable, sxlb.int_enable);
  113. out_be32(&xlb->config, sxlb.config);
  114. /* CDM - Clock Distribution Module */
  115. out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
  116. out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
  117. out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
  118. out_8(&cdm->fd_enable, scdm.fd_enable);
  119. out_be16(&cdm->fd_counters, scdm.fd_counters);
  120. out_be32(&cdm->clk_enables, scdm.clk_enables);
  121. out_8(&cdm->osc_disable, scdm.osc_disable);
  122. out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
  123. out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
  124. out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
  125. out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
  126. /* BESTCOMM */
  127. out_be32(&bes->taskBar, sbes.taskBar);
  128. out_be32(&bes->currentPointer, sbes.currentPointer);
  129. out_be32(&bes->endPointer, sbes.endPointer);
  130. out_be32(&bes->variablePointer, sbes.variablePointer);
  131. out_8(&bes->IntVect1, sbes.IntVect1);
  132. out_8(&bes->IntVect2, sbes.IntVect2);
  133. out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
  134. for (i=0; i<32; i++)
  135. out_8(&bes->ipr[i], sbes.ipr[i]);
  136. out_be32(&bes->cReqSelect, sbes.cReqSelect);
  137. out_be32(&bes->task_size0, sbes.task_size0);
  138. out_be32(&bes->task_size1, sbes.task_size1);
  139. out_be32(&bes->MDEDebug, sbes.MDEDebug);
  140. out_be32(&bes->ADSDebug, sbes.ADSDebug);
  141. out_be32(&bes->Value1, sbes.Value1);
  142. out_be32(&bes->Value2, sbes.Value2);
  143. out_be32(&bes->Control, sbes.Control);
  144. out_be32(&bes->Status, sbes.Status);
  145. out_be32(&bes->PTDDebug, sbes.PTDDebug);
  146. /* restore tasks */
  147. for (i=0; i<16; i++)
  148. out_be16(&bes->tcr[i], sbes.tcr[i]);
  149. /* enable interrupts */
  150. out_be32(&bes->IntPend, sbes.IntPend);
  151. out_be32(&bes->IntMask, sbes.IntMask);
  152. /* PIC */
  153. out_be32(&pic->per_pri1, spic.per_pri1);
  154. out_be32(&pic->per_pri2, spic.per_pri2);
  155. out_be32(&pic->per_pri3, spic.per_pri3);
  156. out_be32(&pic->main_pri1, spic.main_pri1);
  157. out_be32(&pic->main_pri2, spic.main_pri2);
  158. out_be32(&pic->enc_status, spic.enc_status);
  159. /* unmask and enable interrupts */
  160. out_be32(&pic->per_mask, spic.per_mask);
  161. out_be32(&pic->main_mask, spic.main_mask);
  162. out_be32(&pic->ctrl, spic.ctrl);
  163. }
  164. static int lite5200_pm_enter(suspend_state_t state)
  165. {
  166. /* deep sleep? let mpc52xx code handle that */
  167. if (state == PM_SUSPEND_STANDBY) {
  168. return mpc52xx_pm_enter(state);
  169. }
  170. lite5200_save_regs();
  171. /* effectively save FP regs */
  172. enable_kernel_fp();
  173. lite5200_low_power(sram, mbar);
  174. lite5200_restore_regs();
  175. iounmap(mbar);
  176. return 0;
  177. }
  178. static void lite5200_pm_finish(void)
  179. {
  180. /* deep sleep? let mpc52xx code handle that */
  181. if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
  182. mpc52xx_pm_finish();
  183. }
  184. static void lite5200_pm_end(void)
  185. {
  186. lite5200_pm_target_state = PM_SUSPEND_ON;
  187. }
  188. static const struct platform_suspend_ops lite5200_pm_ops = {
  189. .valid = lite5200_pm_valid,
  190. .begin = lite5200_pm_begin,
  191. .prepare = lite5200_pm_prepare,
  192. .enter = lite5200_pm_enter,
  193. .finish = lite5200_pm_finish,
  194. .end = lite5200_pm_end,
  195. };
  196. int __init lite5200_pm_init(void)
  197. {
  198. suspend_set_ops(&lite5200_pm_ops);
  199. return 0;
  200. }