scoreregs.h 1.4 KB

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  1. #ifndef _ASM_SCORE_SCOREREGS_H
  2. #define _ASM_SCORE_SCOREREGS_H
  3. #include <linux/linkage.h>
  4. /* TIMER register */
  5. #define TIME0BASE 0x96080000
  6. #define P_TIMER0_CTRL (TIME0BASE + 0x00)
  7. #define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04)
  8. #define P_TIMER0_PRELOAD (TIME0BASE + 0x08)
  9. #define P_TIMER0_CPP_REG (TIME0BASE + 0x0C)
  10. #define P_TIMER0_UPCNT (TIME0BASE + 0x10)
  11. /* Timer Controller Register */
  12. /* bit 0 Timer enable */
  13. #define TMR_DISABLE 0x0000
  14. #define TMR_ENABLE 0x0001
  15. /* bit 1 Interrupt enable */
  16. #define TMR_IE_DISABLE 0x0000
  17. #define TMR_IE_ENABLE 0x0002
  18. /* bit 2 Output enable */
  19. #define TMR_OE_DISABLE 0x0004
  20. #define TMR_OE_ENABLE 0x0000
  21. /* bit4 Up/Down counting selection */
  22. #define TMR_UD_DOWN 0x0000
  23. #define TMR_UD_UP 0x0010
  24. /* bit5 Up/Down counting control selection */
  25. #define TMR_UDS_UD 0x0000
  26. #define TMR_UDS_EXTUD 0x0020
  27. /* bit6 Time output mode */
  28. #define TMR_OM_TOGGLE 0x0000
  29. #define TMR_OM_PILSE 0x0040
  30. /* bit 8..9 External input active edge selection */
  31. #define TMR_ES_PE 0x0000
  32. #define TMR_ES_NE 0x0100
  33. #define TMR_ES_BOTH 0x0200
  34. /* bit 10..11 Operating mode */
  35. #define TMR_M_FREE 0x0000 /* free running timer mode */
  36. #define TMR_M_PERIODIC 0x0400 /* periodic timer mode */
  37. #define TMR_M_FC 0x0800 /* free running counter mode */
  38. #define TMR_M_PC 0x0c00 /* periodic counter mode */
  39. #define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */
  40. #endif /* _ASM_SCORE_SCOREREGS_H */