dma-g2.c 4.7 KB

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  1. /*
  2. * arch/sh/drivers/dma/dma-g2.c
  3. *
  4. * G2 bus DMA support
  5. *
  6. * Copyright (C) 2003 - 2006 Paul Mundt
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <asm/cacheflush.h>
  17. #include <mach/sysasic.h>
  18. #include <mach/dma.h>
  19. #include <asm/dma.h>
  20. struct g2_channel {
  21. unsigned long g2_addr; /* G2 bus address */
  22. unsigned long root_addr; /* Root bus (SH-4) address */
  23. unsigned long size; /* Size (in bytes), 32-byte aligned */
  24. unsigned long direction; /* Transfer direction */
  25. unsigned long ctrl; /* Transfer control */
  26. unsigned long chan_enable; /* Channel enable */
  27. unsigned long xfer_enable; /* Transfer enable */
  28. unsigned long xfer_stat; /* Transfer status */
  29. } __attribute__ ((aligned(32)));
  30. struct g2_status {
  31. unsigned long g2_addr;
  32. unsigned long root_addr;
  33. unsigned long size;
  34. unsigned long status;
  35. } __attribute__ ((aligned(16)));
  36. struct g2_dma_info {
  37. struct g2_channel channel[G2_NR_DMA_CHANNELS];
  38. unsigned long pad1[G2_NR_DMA_CHANNELS];
  39. unsigned long wait_state;
  40. unsigned long pad2[10];
  41. unsigned long magic;
  42. struct g2_status status[G2_NR_DMA_CHANNELS];
  43. } __attribute__ ((aligned(256)));
  44. static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa05f7800;
  45. #define g2_bytes_remaining(i) \
  46. ((g2_dma->channel[i].size - \
  47. g2_dma->status[i].size) & 0x0fffffff)
  48. static irqreturn_t g2_dma_interrupt(int irq, void *dev_id)
  49. {
  50. int i;
  51. for (i = 0; i < G2_NR_DMA_CHANNELS; i++) {
  52. if (g2_dma->status[i].status & 0x20000000) {
  53. unsigned int bytes = g2_bytes_remaining(i);
  54. if (likely(bytes == 0)) {
  55. struct dma_info *info = dev_id;
  56. struct dma_channel *chan = info->channels + i;
  57. wake_up(&chan->wait_queue);
  58. return IRQ_HANDLED;
  59. }
  60. }
  61. }
  62. return IRQ_NONE;
  63. }
  64. static int g2_enable_dma(struct dma_channel *chan)
  65. {
  66. unsigned int chan_nr = chan->chan;
  67. g2_dma->channel[chan_nr].chan_enable = 1;
  68. g2_dma->channel[chan_nr].xfer_enable = 1;
  69. return 0;
  70. }
  71. static int g2_disable_dma(struct dma_channel *chan)
  72. {
  73. unsigned int chan_nr = chan->chan;
  74. g2_dma->channel[chan_nr].chan_enable = 0;
  75. g2_dma->channel[chan_nr].xfer_enable = 0;
  76. return 0;
  77. }
  78. static int g2_xfer_dma(struct dma_channel *chan)
  79. {
  80. unsigned int chan_nr = chan->chan;
  81. if (chan->sar & 31) {
  82. printk("g2dma: unaligned source 0x%lx\n", chan->sar);
  83. return -EINVAL;
  84. }
  85. if (chan->dar & 31) {
  86. printk("g2dma: unaligned dest 0x%lx\n", chan->dar);
  87. return -EINVAL;
  88. }
  89. /* Align the count */
  90. if (chan->count & 31)
  91. chan->count = (chan->count + (32 - 1)) & ~(32 - 1);
  92. /* Fixup destination */
  93. chan->dar += 0xa0800000;
  94. /* Fixup direction */
  95. chan->mode = !chan->mode;
  96. flush_icache_range((unsigned long)chan->sar, chan->count);
  97. g2_disable_dma(chan);
  98. g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0;
  99. g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0;
  100. g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000;
  101. g2_dma->channel[chan_nr].direction = chan->mode;
  102. /*
  103. * bit 0 - ???
  104. * bit 1 - if set, generate a hardware event on transfer completion
  105. * bit 2 - ??? something to do with suspend?
  106. */
  107. g2_dma->channel[chan_nr].ctrl = 5; /* ?? */
  108. g2_enable_dma(chan);
  109. /* debug cruft */
  110. pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, "
  111. "0x%08lx, %ld, %ld, %ld, %ld\n",
  112. g2_dma->channel[chan_nr].size,
  113. g2_dma->channel[chan_nr].root_addr,
  114. g2_dma->channel[chan_nr].g2_addr,
  115. g2_dma->channel[chan_nr].direction,
  116. g2_dma->channel[chan_nr].ctrl,
  117. g2_dma->channel[chan_nr].chan_enable,
  118. g2_dma->channel[chan_nr].xfer_enable);
  119. return 0;
  120. }
  121. static int g2_get_residue(struct dma_channel *chan)
  122. {
  123. return g2_bytes_remaining(chan->chan);
  124. }
  125. static struct dma_ops g2_dma_ops = {
  126. .xfer = g2_xfer_dma,
  127. .get_residue = g2_get_residue,
  128. };
  129. static struct dma_info g2_dma_info = {
  130. .name = "g2_dmac",
  131. .nr_channels = 4,
  132. .ops = &g2_dma_ops,
  133. .flags = DMAC_CHANNELS_TEI_CAPABLE,
  134. };
  135. static int __init g2_dma_init(void)
  136. {
  137. int ret;
  138. ret = request_irq(HW_EVENT_G2_DMA, g2_dma_interrupt, 0,
  139. "g2 DMA handler", &g2_dma_info);
  140. if (unlikely(ret))
  141. return -EINVAL;
  142. /* Magic */
  143. g2_dma->wait_state = 27;
  144. g2_dma->magic = 0x4659404f;
  145. ret = register_dmac(&g2_dma_info);
  146. if (unlikely(ret != 0))
  147. free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
  148. return ret;
  149. }
  150. static void __exit g2_dma_exit(void)
  151. {
  152. free_irq(HW_EVENT_G2_DMA, &g2_dma_info);
  153. unregister_dmac(&g2_dma_info);
  154. }
  155. subsys_initcall(g2_dma_init);
  156. module_exit(g2_dma_exit);
  157. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
  158. MODULE_DESCRIPTION("G2 bus DMA driver");
  159. MODULE_LICENSE("GPL");