pm.c 4.3 KB

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  1. /*
  2. * arch/sh/kernel/cpu/shmobile/pm.c
  3. *
  4. * Power management support code for SuperH Mobile
  5. *
  6. * Copyright (C) 2009 Magnus Damm
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/io.h>
  15. #include <linux/suspend.h>
  16. #include <asm/suspend.h>
  17. #include <asm/uaccess.h>
  18. #include <asm/cacheflush.h>
  19. #include <asm/bl_bit.h>
  20. /*
  21. * Notifier lists for pre/post sleep notification
  22. */
  23. ATOMIC_NOTIFIER_HEAD(sh_mobile_pre_sleep_notifier_list);
  24. ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
  25. /*
  26. * Sleep modes available on SuperH Mobile:
  27. *
  28. * Sleep mode is just plain "sleep" instruction
  29. * Sleep Self-Refresh mode is above plus RAM put in Self-Refresh
  30. * Standby Self-Refresh mode is above plus stopped clocks
  31. */
  32. #define SUSP_MODE_SLEEP (SUSP_SH_SLEEP)
  33. #define SUSP_MODE_SLEEP_SF (SUSP_SH_SLEEP | SUSP_SH_SF)
  34. #define SUSP_MODE_STANDBY_SF (SUSP_SH_STANDBY | SUSP_SH_SF)
  35. #define SUSP_MODE_RSTANDBY_SF \
  36. (SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_REGS | SUSP_SH_SF)
  37. /*
  38. * U-standby mode is unsupported since it needs bootloader hacks
  39. */
  40. #ifdef CONFIG_CPU_SUBTYPE_SH7724
  41. #define RAM_BASE 0xfd800000 /* RSMEM */
  42. #else
  43. #define RAM_BASE 0xe5200000 /* ILRAM */
  44. #endif
  45. void sh_mobile_call_standby(unsigned long mode)
  46. {
  47. void *onchip_mem = (void *)RAM_BASE;
  48. struct sh_sleep_data *sdp = onchip_mem;
  49. void (*standby_onchip_mem)(unsigned long, unsigned long);
  50. /* code located directly after data structure */
  51. standby_onchip_mem = (void *)(sdp + 1);
  52. atomic_notifier_call_chain(&sh_mobile_pre_sleep_notifier_list,
  53. mode, NULL);
  54. /* flush the caches if MMU flag is set */
  55. if (mode & SUSP_SH_MMU)
  56. flush_cache_all();
  57. /* Let assembly snippet in on-chip memory handle the rest */
  58. standby_onchip_mem(mode, RAM_BASE);
  59. atomic_notifier_call_chain(&sh_mobile_post_sleep_notifier_list,
  60. mode, NULL);
  61. }
  62. extern char sh_mobile_sleep_enter_start;
  63. extern char sh_mobile_sleep_enter_end;
  64. extern char sh_mobile_sleep_resume_start;
  65. extern char sh_mobile_sleep_resume_end;
  66. unsigned long sh_mobile_sleep_supported = SUSP_SH_SLEEP;
  67. void sh_mobile_register_self_refresh(unsigned long flags,
  68. void *pre_start, void *pre_end,
  69. void *post_start, void *post_end)
  70. {
  71. void *onchip_mem = (void *)RAM_BASE;
  72. void *vp;
  73. struct sh_sleep_data *sdp;
  74. int n;
  75. /* part 0: data area */
  76. sdp = onchip_mem;
  77. sdp->addr.stbcr = 0xa4150020; /* STBCR */
  78. sdp->addr.bar = 0xa4150040; /* BAR */
  79. sdp->addr.pteh = 0xff000000; /* PTEH */
  80. sdp->addr.ptel = 0xff000004; /* PTEL */
  81. sdp->addr.ttb = 0xff000008; /* TTB */
  82. sdp->addr.tea = 0xff00000c; /* TEA */
  83. sdp->addr.mmucr = 0xff000010; /* MMUCR */
  84. sdp->addr.ptea = 0xff000034; /* PTEA */
  85. sdp->addr.pascr = 0xff000070; /* PASCR */
  86. sdp->addr.irmcr = 0xff000078; /* IRMCR */
  87. sdp->addr.ccr = 0xff00001c; /* CCR */
  88. sdp->addr.ramcr = 0xff000074; /* RAMCR */
  89. vp = sdp + 1;
  90. /* part 1: common code to enter sleep mode */
  91. n = &sh_mobile_sleep_enter_end - &sh_mobile_sleep_enter_start;
  92. memcpy(vp, &sh_mobile_sleep_enter_start, n);
  93. vp += roundup(n, 4);
  94. /* part 2: board specific code to enter self-refresh mode */
  95. n = pre_end - pre_start;
  96. memcpy(vp, pre_start, n);
  97. sdp->sf_pre = (unsigned long)vp;
  98. vp += roundup(n, 4);
  99. /* part 3: board specific code to resume from self-refresh mode */
  100. n = post_end - post_start;
  101. memcpy(vp, post_start, n);
  102. sdp->sf_post = (unsigned long)vp;
  103. vp += roundup(n, 4);
  104. /* part 4: common code to resume from sleep mode */
  105. WARN_ON(vp > (onchip_mem + 0x600));
  106. vp = onchip_mem + 0x600; /* located at interrupt vector */
  107. n = &sh_mobile_sleep_resume_end - &sh_mobile_sleep_resume_start;
  108. memcpy(vp, &sh_mobile_sleep_resume_start, n);
  109. sdp->resume = (unsigned long)vp;
  110. sh_mobile_sleep_supported |= flags;
  111. }
  112. static int sh_pm_enter(suspend_state_t state)
  113. {
  114. if (!(sh_mobile_sleep_supported & SUSP_MODE_STANDBY_SF))
  115. return -ENXIO;
  116. local_irq_disable();
  117. set_bl_bit();
  118. sh_mobile_call_standby(SUSP_MODE_STANDBY_SF);
  119. local_irq_disable();
  120. clear_bl_bit();
  121. return 0;
  122. }
  123. static const struct platform_suspend_ops sh_pm_ops = {
  124. .enter = sh_pm_enter,
  125. .valid = suspend_valid_only_mem,
  126. };
  127. static int __init sh_pm_init(void)
  128. {
  129. suspend_set_ops(&sh_pm_ops);
  130. return sh_mobile_setup_cpuidle();
  131. }
  132. late_initcall(sh_pm_init);