udivsi3.S 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. /* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
  2. 2004, 2005
  3. Free Software Foundation, Inc.
  4. This file is free software; you can redistribute it and/or modify it
  5. under the terms of the GNU General Public License as published by the
  6. Free Software Foundation; either version 2, or (at your option) any
  7. later version.
  8. In addition to the permissions in the GNU General Public License, the
  9. Free Software Foundation gives you unlimited permission to link the
  10. compiled version of this file into combinations with other programs,
  11. and to distribute those combinations without any restriction coming
  12. from the use of this file. (The General Public License restrictions
  13. do apply in other respects; for example, they cover modification of
  14. the file, and distribution when not linked into a combine
  15. executable.)
  16. This file is distributed in the hope that it will be useful, but
  17. WITHOUT ANY WARRANTY; without even the implied warranty of
  18. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. General Public License for more details.
  20. You should have received a copy of the GNU General Public License
  21. along with this program; see the file COPYING. If not, write to
  22. the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  23. Boston, MA 02110-1301, USA. */
  24. !! libgcc routines for the Renesas / SuperH SH CPUs.
  25. !! Contributed by Steve Chamberlain.
  26. !! sac@cygnus.com
  27. .balign 4
  28. .global __udivsi3
  29. .type __udivsi3, @function
  30. div8:
  31. div1 r5,r4
  32. div7:
  33. div1 r5,r4; div1 r5,r4; div1 r5,r4
  34. div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
  35. divx4:
  36. div1 r5,r4; rotcl r0
  37. div1 r5,r4; rotcl r0
  38. div1 r5,r4; rotcl r0
  39. rts; div1 r5,r4
  40. __udivsi3:
  41. sts.l pr,@-r15
  42. extu.w r5,r0
  43. cmp/eq r5,r0
  44. bf/s large_divisor
  45. div0u
  46. swap.w r4,r0
  47. shlr16 r4
  48. bsr div8
  49. shll16 r5
  50. bsr div7
  51. div1 r5,r4
  52. xtrct r4,r0
  53. xtrct r0,r4
  54. bsr div8
  55. swap.w r4,r4
  56. bsr div7
  57. div1 r5,r4
  58. lds.l @r15+,pr
  59. xtrct r4,r0
  60. swap.w r0,r0
  61. rotcl r0
  62. rts
  63. shlr16 r5
  64. large_divisor:
  65. mov #0,r0
  66. xtrct r4,r0
  67. xtrct r0,r4
  68. bsr divx4
  69. rotcl r0
  70. bsr divx4
  71. rotcl r0
  72. bsr divx4
  73. rotcl r0
  74. bsr divx4
  75. rotcl r0
  76. lds.l @r15+,pr
  77. rts
  78. rotcl r0