intel_pmic_crc.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211
  1. /*
  2. * intel_pmic_crc.c - Intel CrystalCove PMIC operation region driver
  3. *
  4. * Copyright (C) 2014 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/acpi.h>
  17. #include <linux/mfd/intel_soc_pmic.h>
  18. #include <linux/regmap.h>
  19. #include <linux/platform_device.h>
  20. #include "intel_pmic.h"
  21. #define PWR_SOURCE_SELECT BIT(1)
  22. #define PMIC_A0LOCK_REG 0xc5
  23. static struct pmic_table power_table[] = {
  24. {
  25. .address = 0x24,
  26. .reg = 0x66,
  27. .bit = 0x00,
  28. },
  29. {
  30. .address = 0x48,
  31. .reg = 0x5d,
  32. .bit = 0x00,
  33. },
  34. };
  35. static struct pmic_table thermal_table[] = {
  36. {
  37. .address = 0x00,
  38. .reg = 0x75
  39. },
  40. {
  41. .address = 0x04,
  42. .reg = 0x95
  43. },
  44. {
  45. .address = 0x08,
  46. .reg = 0x97
  47. },
  48. {
  49. .address = 0x0c,
  50. .reg = 0x77
  51. },
  52. {
  53. .address = 0x10,
  54. .reg = 0x9a
  55. },
  56. {
  57. .address = 0x14,
  58. .reg = 0x9c
  59. },
  60. {
  61. .address = 0x18,
  62. .reg = 0x79
  63. },
  64. {
  65. .address = 0x1c,
  66. .reg = 0x9f
  67. },
  68. {
  69. .address = 0x20,
  70. .reg = 0xa1
  71. },
  72. {
  73. .address = 0x48,
  74. .reg = 0x94
  75. },
  76. {
  77. .address = 0x4c,
  78. .reg = 0x99
  79. },
  80. {
  81. .address = 0x50,
  82. .reg = 0x9e
  83. },
  84. };
  85. static int intel_crc_pmic_get_power(struct regmap *regmap, int reg,
  86. int bit, u64 *value)
  87. {
  88. int data;
  89. if (regmap_read(regmap, reg, &data))
  90. return -EIO;
  91. *value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0;
  92. return 0;
  93. }
  94. static int intel_crc_pmic_update_power(struct regmap *regmap, int reg,
  95. int bit, bool on)
  96. {
  97. int data;
  98. if (regmap_read(regmap, reg, &data))
  99. return -EIO;
  100. if (on) {
  101. data |= PWR_SOURCE_SELECT | BIT(bit);
  102. } else {
  103. data &= ~BIT(bit);
  104. data |= PWR_SOURCE_SELECT;
  105. }
  106. if (regmap_write(regmap, reg, data))
  107. return -EIO;
  108. return 0;
  109. }
  110. static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg)
  111. {
  112. int temp_l, temp_h;
  113. /*
  114. * Raw temperature value is 10bits: 8bits in reg
  115. * and 2bits in reg-1: bit0,1
  116. */
  117. if (regmap_read(regmap, reg, &temp_l) ||
  118. regmap_read(regmap, reg - 1, &temp_h))
  119. return -EIO;
  120. return temp_l | (temp_h & 0x3) << 8;
  121. }
  122. static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw)
  123. {
  124. return regmap_write(regmap, reg, raw) ||
  125. regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0;
  126. }
  127. static int intel_crc_pmic_get_policy(struct regmap *regmap, int reg, u64 *value)
  128. {
  129. int pen;
  130. if (regmap_read(regmap, reg, &pen))
  131. return -EIO;
  132. *value = pen >> 7;
  133. return 0;
  134. }
  135. static int intel_crc_pmic_update_policy(struct regmap *regmap,
  136. int reg, int enable)
  137. {
  138. int alert0;
  139. /* Update to policy enable bit requires unlocking a0lock */
  140. if (regmap_read(regmap, PMIC_A0LOCK_REG, &alert0))
  141. return -EIO;
  142. if (regmap_update_bits(regmap, PMIC_A0LOCK_REG, 0x01, 0))
  143. return -EIO;
  144. if (regmap_update_bits(regmap, reg, 0x80, enable << 7))
  145. return -EIO;
  146. /* restore alert0 */
  147. if (regmap_write(regmap, PMIC_A0LOCK_REG, alert0))
  148. return -EIO;
  149. return 0;
  150. }
  151. static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
  152. .get_power = intel_crc_pmic_get_power,
  153. .update_power = intel_crc_pmic_update_power,
  154. .get_raw_temp = intel_crc_pmic_get_raw_temp,
  155. .update_aux = intel_crc_pmic_update_aux,
  156. .get_policy = intel_crc_pmic_get_policy,
  157. .update_policy = intel_crc_pmic_update_policy,
  158. .power_table = power_table,
  159. .power_table_count= ARRAY_SIZE(power_table),
  160. .thermal_table = thermal_table,
  161. .thermal_table_count = ARRAY_SIZE(thermal_table),
  162. };
  163. static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
  164. {
  165. struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
  166. return intel_pmic_install_opregion_handler(&pdev->dev,
  167. ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
  168. &intel_crc_pmic_opregion_data);
  169. }
  170. static struct platform_driver intel_crc_pmic_opregion_driver = {
  171. .probe = intel_crc_pmic_opregion_probe,
  172. .driver = {
  173. .name = "crystal_cove_pmic",
  174. },
  175. };
  176. static int __init intel_crc_pmic_opregion_driver_init(void)
  177. {
  178. return platform_driver_register(&intel_crc_pmic_opregion_driver);
  179. }
  180. module_init(intel_crc_pmic_opregion_driver_init);
  181. MODULE_DESCRIPTION("CrystalCove ACPI operation region driver");
  182. MODULE_LICENSE("GPL");