pata_ns87415.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422
  1. /*
  2. * pata_ns87415.c - NS87415 (non PARISC) PATA
  3. *
  4. * (C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
  5. *
  6. * This is a fairly generic MWDMA controller. It has some limitations
  7. * as it requires timing reloads on PIO/DMA transitions but it is otherwise
  8. * fairly well designed.
  9. *
  10. * This driver assumes the firmware has left the chip in a valid ST506
  11. * compliant state, either legacy IRQ 14/15 or native INTA shared. You
  12. * may need to add platform code if your system fails to do this.
  13. *
  14. * The same cell appears in the 87560 controller used by some PARISC
  15. * systems. This has its own special mountain of errata.
  16. *
  17. * TODO:
  18. * Test PARISC SuperIO
  19. * Get someone to test on SPARC
  20. * Implement lazy pio/dma switching for better performance
  21. * 8bit shared timing.
  22. * See if we need to kill the FIFO for ATAPI
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/blkdev.h>
  28. #include <linux/delay.h>
  29. #include <linux/device.h>
  30. #include <scsi/scsi_host.h>
  31. #include <linux/libata.h>
  32. #include <linux/ata.h>
  33. #define DRV_NAME "pata_ns87415"
  34. #define DRV_VERSION "0.0.1"
  35. /**
  36. * ns87415_set_mode - Initialize host controller mode timings
  37. * @ap: Port whose timings we are configuring
  38. * @adev: Device whose timings we are configuring
  39. * @mode: Mode to set
  40. *
  41. * Program the mode registers for this controller, channel and
  42. * device. Because the chip is quite an old design we have to do this
  43. * for PIO/DMA switches.
  44. *
  45. * LOCKING:
  46. * None (inherited from caller).
  47. */
  48. static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
  49. {
  50. struct pci_dev *dev = to_pci_dev(ap->host->dev);
  51. int unit = 2 * ap->port_no + adev->devno;
  52. int timing = 0x44 + 2 * unit;
  53. unsigned long T = 1000000000 / 33333; /* PCI clocks */
  54. struct ata_timing t;
  55. u16 clocking;
  56. u8 iordy;
  57. u8 status;
  58. /* Timing register format is 17 - low nybble read timing with
  59. the high nybble being 16 - x for recovery time in PCI clocks */
  60. ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
  61. clocking = 17 - clamp_val(t.active, 2, 17);
  62. clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
  63. /* Use the same timing for read and write bytes */
  64. clocking |= (clocking << 8);
  65. pci_write_config_word(dev, timing, clocking);
  66. /* Set the IORDY enable versus DMA enable on or off properly */
  67. pci_read_config_byte(dev, 0x42, &iordy);
  68. iordy &= ~(1 << (4 + unit));
  69. if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev))
  70. iordy |= (1 << (4 + unit));
  71. /* Paranoia: We shouldn't ever get here with busy write buffers
  72. but if so wait */
  73. pci_read_config_byte(dev, 0x43, &status);
  74. while (status & 0x03) {
  75. udelay(1);
  76. pci_read_config_byte(dev, 0x43, &status);
  77. }
  78. /* Flip the IORDY/DMA bits now we are sure the write buffers are
  79. clear */
  80. pci_write_config_byte(dev, 0x42, iordy);
  81. /* TODO: Set byte 54 command timing to the best 8bit
  82. mode shared by all four devices */
  83. }
  84. /**
  85. * ns87415_set_piomode - Initialize host controller PATA PIO timings
  86. * @ap: Port whose timings we are configuring
  87. * @adev: Device to program
  88. *
  89. * Set PIO mode for device, in host controller PCI config space.
  90. *
  91. * LOCKING:
  92. * None (inherited from caller).
  93. */
  94. static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
  95. {
  96. ns87415_set_mode(ap, adev, adev->pio_mode);
  97. }
  98. /**
  99. * ns87415_bmdma_setup - Set up DMA
  100. * @qc: Command block
  101. *
  102. * Set up for bus masterng DMA. We have to do this ourselves
  103. * rather than use the helper due to a chip erratum
  104. */
  105. static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
  106. {
  107. struct ata_port *ap = qc->ap;
  108. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  109. u8 dmactl;
  110. /* load PRD table addr. */
  111. mb(); /* make sure PRD table writes are visible to controller */
  112. iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
  113. /* specify data direction, triple-check start bit is clear */
  114. dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  115. dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
  116. /* Due to an erratum we need to write these bits to the wrong
  117. place - which does save us an I/O bizarrely */
  118. dmactl |= ATA_DMA_INTR | ATA_DMA_ERR;
  119. if (!rw)
  120. dmactl |= ATA_DMA_WR;
  121. iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
  122. /* issue r/w command */
  123. ap->ops->sff_exec_command(ap, &qc->tf);
  124. }
  125. /**
  126. * ns87415_bmdma_start - Begin DMA transfer
  127. * @qc: Command block
  128. *
  129. * Switch the timings for the chip and set up for a DMA transfer
  130. * before the DMA burst begins.
  131. *
  132. * FIXME: We should do lazy switching on bmdma_start versus
  133. * ata_pio_data_xfer for better performance.
  134. */
  135. static void ns87415_bmdma_start(struct ata_queued_cmd *qc)
  136. {
  137. ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode);
  138. ata_bmdma_start(qc);
  139. }
  140. /**
  141. * ns87415_bmdma_stop - End DMA transfer
  142. * @qc: Command block
  143. *
  144. * End DMA mode and switch the controller back into PIO mode
  145. */
  146. static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
  147. {
  148. ata_bmdma_stop(qc);
  149. ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode);
  150. }
  151. /**
  152. * ns87415_irq_clear - Clear interrupt
  153. * @ap: Channel to clear
  154. *
  155. * Erratum: Due to a chip bug regisers 02 and 0A bit 1 and 2 (the
  156. * error bits) are reset by writing to register 00 or 08.
  157. */
  158. static void ns87415_irq_clear(struct ata_port *ap)
  159. {
  160. void __iomem *mmio = ap->ioaddr.bmdma_addr;
  161. if (!mmio)
  162. return;
  163. iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR),
  164. mmio + ATA_DMA_CMD);
  165. }
  166. /**
  167. * ns87415_check_atapi_dma - ATAPI DMA filter
  168. * @qc: Command block
  169. *
  170. * Disable ATAPI DMA (for now). We may be able to do DMA if we
  171. * kill the prefetching. This isn't clear.
  172. */
  173. static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc)
  174. {
  175. return -EOPNOTSUPP;
  176. }
  177. #if defined(CONFIG_SUPERIO)
  178. /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  179. * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  180. * which use the integrated NS87514 cell for CD-ROM support.
  181. * i.e we have to support for CD-ROM installs.
  182. * See drivers/parisc/superio.c for more gory details.
  183. *
  184. * Workarounds taken from drivers/ide/pci/ns87415.c
  185. */
  186. #include <asm/superio.h>
  187. #define SUPERIO_IDE_MAX_RETRIES 25
  188. /**
  189. * ns87560_read_buggy - workaround buggy Super I/O chip
  190. * @port: Port to read
  191. *
  192. * Work around chipset problems in the 87560 SuperIO chip
  193. */
  194. static u8 ns87560_read_buggy(void __iomem *port)
  195. {
  196. u8 tmp;
  197. int retries = SUPERIO_IDE_MAX_RETRIES;
  198. do {
  199. tmp = ioread8(port);
  200. if (tmp != 0)
  201. return tmp;
  202. udelay(50);
  203. } while(retries-- > 0);
  204. return tmp;
  205. }
  206. /**
  207. * ns87560_check_status
  208. * @ap: channel to check
  209. *
  210. * Return the status of the channel working around the
  211. * 87560 flaws.
  212. */
  213. static u8 ns87560_check_status(struct ata_port *ap)
  214. {
  215. return ns87560_read_buggy(ap->ioaddr.status_addr);
  216. }
  217. /**
  218. * ns87560_tf_read - input device's ATA taskfile shadow registers
  219. * @ap: Port from which input is read
  220. * @tf: ATA taskfile register set for storing input
  221. *
  222. * Reads ATA taskfile registers for currently-selected device
  223. * into @tf. Work around the 87560 bugs.
  224. *
  225. * LOCKING:
  226. * Inherited from caller.
  227. */
  228. void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  229. {
  230. struct ata_ioports *ioaddr = &ap->ioaddr;
  231. tf->command = ns87560_check_status(ap);
  232. tf->feature = ioread8(ioaddr->error_addr);
  233. tf->nsect = ioread8(ioaddr->nsect_addr);
  234. tf->lbal = ioread8(ioaddr->lbal_addr);
  235. tf->lbam = ioread8(ioaddr->lbam_addr);
  236. tf->lbah = ioread8(ioaddr->lbah_addr);
  237. tf->device = ns87560_read_buggy(ioaddr->device_addr);
  238. if (tf->flags & ATA_TFLAG_LBA48) {
  239. iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
  240. tf->hob_feature = ioread8(ioaddr->error_addr);
  241. tf->hob_nsect = ioread8(ioaddr->nsect_addr);
  242. tf->hob_lbal = ioread8(ioaddr->lbal_addr);
  243. tf->hob_lbam = ioread8(ioaddr->lbam_addr);
  244. tf->hob_lbah = ioread8(ioaddr->lbah_addr);
  245. iowrite8(tf->ctl, ioaddr->ctl_addr);
  246. ap->last_ctl = tf->ctl;
  247. }
  248. }
  249. /**
  250. * ns87560_bmdma_status
  251. * @ap: channel to check
  252. *
  253. * Return the DMA status of the channel working around the
  254. * 87560 flaws.
  255. */
  256. static u8 ns87560_bmdma_status(struct ata_port *ap)
  257. {
  258. return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
  259. }
  260. #endif /* 87560 SuperIO Support */
  261. static struct ata_port_operations ns87415_pata_ops = {
  262. .inherits = &ata_bmdma_port_ops,
  263. .check_atapi_dma = ns87415_check_atapi_dma,
  264. .bmdma_setup = ns87415_bmdma_setup,
  265. .bmdma_start = ns87415_bmdma_start,
  266. .bmdma_stop = ns87415_bmdma_stop,
  267. .sff_irq_clear = ns87415_irq_clear,
  268. .cable_detect = ata_cable_40wire,
  269. .set_piomode = ns87415_set_piomode,
  270. };
  271. #if defined(CONFIG_SUPERIO)
  272. static struct ata_port_operations ns87560_pata_ops = {
  273. .inherits = &ns87415_pata_ops,
  274. .sff_tf_read = ns87560_tf_read,
  275. .sff_check_status = ns87560_check_status,
  276. .bmdma_status = ns87560_bmdma_status,
  277. };
  278. #endif
  279. static struct scsi_host_template ns87415_sht = {
  280. ATA_BMDMA_SHT(DRV_NAME),
  281. };
  282. static void ns87415_fixup(struct pci_dev *pdev)
  283. {
  284. /* Select 512 byte sectors */
  285. pci_write_config_byte(pdev, 0x55, 0xEE);
  286. /* Select PIO0 8bit clocking */
  287. pci_write_config_byte(pdev, 0x54, 0xB7);
  288. }
  289. /**
  290. * ns87415_init_one - Register 87415 ATA PCI device with kernel services
  291. * @pdev: PCI device to register
  292. * @ent: Entry in ns87415_pci_tbl matching with @pdev
  293. *
  294. * Called from kernel PCI layer. We probe for combined mode (sigh),
  295. * and then hand over control to libata, for it to do the rest.
  296. *
  297. * LOCKING:
  298. * Inherited from PCI layer (may sleep).
  299. *
  300. * RETURNS:
  301. * Zero on success, or -ERRNO value.
  302. */
  303. static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  304. {
  305. static const struct ata_port_info info = {
  306. .flags = ATA_FLAG_SLAVE_POSS,
  307. .pio_mask = ATA_PIO4,
  308. .mwdma_mask = ATA_MWDMA2,
  309. .port_ops = &ns87415_pata_ops,
  310. };
  311. const struct ata_port_info *ppi[] = { &info, NULL };
  312. int rc;
  313. #if defined(CONFIG_SUPERIO)
  314. static const struct ata_port_info info87560 = {
  315. .flags = ATA_FLAG_SLAVE_POSS,
  316. .pio_mask = ATA_PIO4,
  317. .mwdma_mask = ATA_MWDMA2,
  318. .port_ops = &ns87560_pata_ops,
  319. };
  320. if (PCI_SLOT(pdev->devfn) == 0x0E)
  321. ppi[0] = &info87560;
  322. #endif
  323. ata_print_version_once(&pdev->dev, DRV_VERSION);
  324. rc = pcim_enable_device(pdev);
  325. if (rc)
  326. return rc;
  327. ns87415_fixup(pdev);
  328. return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
  329. }
  330. static const struct pci_device_id ns87415_pci_tbl[] = {
  331. { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), },
  332. { } /* terminate list */
  333. };
  334. #ifdef CONFIG_PM_SLEEP
  335. static int ns87415_reinit_one(struct pci_dev *pdev)
  336. {
  337. struct ata_host *host = pci_get_drvdata(pdev);
  338. int rc;
  339. rc = ata_pci_device_do_resume(pdev);
  340. if (rc)
  341. return rc;
  342. ns87415_fixup(pdev);
  343. ata_host_resume(host);
  344. return 0;
  345. }
  346. #endif
  347. static struct pci_driver ns87415_pci_driver = {
  348. .name = DRV_NAME,
  349. .id_table = ns87415_pci_tbl,
  350. .probe = ns87415_init_one,
  351. .remove = ata_pci_remove_one,
  352. #ifdef CONFIG_PM_SLEEP
  353. .suspend = ata_pci_device_suspend,
  354. .resume = ns87415_reinit_one,
  355. #endif
  356. };
  357. module_pci_driver(ns87415_pci_driver);
  358. MODULE_AUTHOR("Alan Cox");
  359. MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
  360. MODULE_LICENSE("GPL");
  361. MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
  362. MODULE_VERSION(DRV_VERSION);