he.h 20 KB

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  1. /*
  2. he.h
  3. ForeRunnerHE ATM Adapter driver for ATM on Linux
  4. Copyright (C) 1999-2001 Naval Research Laboratory
  5. This library is free software; you can redistribute it and/or
  6. modify it under the terms of the GNU Lesser General Public
  7. License as published by the Free Software Foundation; either
  8. version 2.1 of the License, or (at your option) any later version.
  9. This library is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. Lesser General Public License for more details.
  13. You should have received a copy of the GNU Lesser General Public
  14. License along with this library; if not, write to the Free Software
  15. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. /*
  18. he.h
  19. ForeRunnerHE ATM Adapter driver for ATM on Linux
  20. Copyright (C) 1999-2000 Naval Research Laboratory
  21. Permission to use, copy, modify and distribute this software and its
  22. documentation is hereby granted, provided that both the copyright
  23. notice and this permission notice appear in all copies of the software,
  24. derivative works or modified versions, and any portions thereof, and
  25. that both notices appear in supporting documentation.
  26. NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
  27. DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
  28. RESULTING FROM THE USE OF THIS SOFTWARE.
  29. */
  30. #ifndef _HE_H_
  31. #define _HE_H_
  32. #define DEV_LABEL "he"
  33. #define CONFIG_DEFAULT_VCIBITS 12
  34. #define CONFIG_DEFAULT_VPIBITS 0
  35. #define CONFIG_IRQ_SIZE 128
  36. #define CONFIG_IRQ_THRESH (CONFIG_IRQ_SIZE/2)
  37. #define CONFIG_TPDRQ_SIZE 512
  38. #define TPDRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TPDRQ_SIZE<<3)-1))
  39. #define CONFIG_RBRQ_SIZE 512
  40. #define CONFIG_RBRQ_THRESH 400
  41. #define RBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_RBRQ_SIZE<<3)-1))
  42. #define CONFIG_TBRQ_SIZE 512
  43. #define CONFIG_TBRQ_THRESH 400
  44. #define TBRQ_MASK(x) (((unsigned long)(x))&((CONFIG_TBRQ_SIZE<<2)-1))
  45. #define CONFIG_RBPL_SIZE 512
  46. #define CONFIG_RBPL_THRESH 64
  47. #define CONFIG_RBPL_BUFSIZE 4096
  48. #define RBPL_MASK(x) (((unsigned long)(x))&((CONFIG_RBPL_SIZE<<3)-1))
  49. /* 5.1.3 initialize connection memory */
  50. #define CONFIG_RSRA 0x00000
  51. #define CONFIG_RCMLBM 0x08000
  52. #define CONFIG_RCMABR 0x0d800
  53. #define CONFIG_RSRB 0x0e000
  54. #define CONFIG_TSRA 0x00000
  55. #define CONFIG_TSRB 0x08000
  56. #define CONFIG_TSRC 0x0c000
  57. #define CONFIG_TSRD 0x0e000
  58. #define CONFIG_TMABR 0x0f000
  59. #define CONFIG_TPDBA 0x10000
  60. #define HE_MAXCIDBITS 12
  61. /* 2.9.3.3 interrupt encodings */
  62. struct he_irq {
  63. volatile u32 isw;
  64. };
  65. #define IRQ_ALIGNMENT 0x1000
  66. #define NEXT_ENTRY(base, tail, mask) \
  67. (((unsigned long)base)|(((unsigned long)(tail+1))&mask))
  68. #define ITYPE_INVALID 0xffffffff
  69. #define ITYPE_TBRQ_THRESH (0<<3)
  70. #define ITYPE_TPD_COMPLETE (1<<3)
  71. #define ITYPE_RBPS_THRESH (2<<3)
  72. #define ITYPE_RBPL_THRESH (3<<3)
  73. #define ITYPE_RBRQ_THRESH (4<<3)
  74. #define ITYPE_RBRQ_TIMER (5<<3)
  75. #define ITYPE_PHY (6<<3)
  76. #define ITYPE_OTHER 0x80
  77. #define ITYPE_PARITY 0x81
  78. #define ITYPE_ABORT 0x82
  79. #define ITYPE_GROUP(x) (x & 0x7)
  80. #define ITYPE_TYPE(x) (x & 0xf8)
  81. #define HE_NUM_GROUPS 8
  82. /* 2.1.4 transmit packet descriptor */
  83. struct he_tpd {
  84. /* read by the adapter */
  85. volatile u32 status;
  86. volatile u32 reserved;
  87. #define TPD_MAXIOV 3
  88. struct {
  89. u32 addr, len;
  90. } iovec[TPD_MAXIOV];
  91. #define address0 iovec[0].addr
  92. #define length0 iovec[0].len
  93. /* linux-atm extensions */
  94. struct sk_buff *skb;
  95. struct atm_vcc *vcc;
  96. struct list_head entry;
  97. };
  98. #define TPD_ALIGNMENT 64
  99. #define TPD_LEN_MASK 0xffff
  100. #define TPD_ADDR_SHIFT 6
  101. #define TPD_MASK 0xffffffc0
  102. #define TPD_ADDR(x) ((x) & TPD_MASK)
  103. #define TPD_INDEX(x) (TPD_ADDR(x) >> TPD_ADDR_SHIFT)
  104. /* table 2.3 transmit buffer return elements */
  105. struct he_tbrq {
  106. volatile u32 tbre;
  107. };
  108. #define TBRQ_ALIGNMENT CONFIG_TBRQ_SIZE
  109. #define TBRQ_TPD(tbrq) ((tbrq)->tbre & 0xffffffc0)
  110. #define TBRQ_EOS(tbrq) ((tbrq)->tbre & (1<<3))
  111. #define TBRQ_MULTIPLE(tbrq) ((tbrq)->tbre & (1))
  112. /* table 2.21 receive buffer return queue element field organization */
  113. struct he_rbrq {
  114. volatile u32 addr;
  115. volatile u32 cidlen;
  116. };
  117. #define RBRQ_ALIGNMENT CONFIG_RBRQ_SIZE
  118. #define RBRQ_ADDR(rbrq) ((rbrq)->addr & 0xffffffc0)
  119. #define RBRQ_CRC_ERR(rbrq) ((rbrq)->addr & (1<<5))
  120. #define RBRQ_LEN_ERR(rbrq) ((rbrq)->addr & (1<<4))
  121. #define RBRQ_END_PDU(rbrq) ((rbrq)->addr & (1<<3))
  122. #define RBRQ_AAL5_PROT(rbrq) ((rbrq)->addr & (1<<2))
  123. #define RBRQ_CON_CLOSED(rbrq) ((rbrq)->addr & (1<<1))
  124. #define RBRQ_HBUF_ERR(rbrq) ((rbrq)->addr & 1)
  125. #define RBRQ_CID(rbrq) (((rbrq)->cidlen >> 16) & 0x1fff)
  126. #define RBRQ_BUFLEN(rbrq) ((rbrq)->cidlen & 0xffff)
  127. /* figure 2.3 transmit packet descriptor ready queue */
  128. struct he_tpdrq {
  129. volatile u32 tpd;
  130. volatile u32 cid;
  131. };
  132. #define TPDRQ_ALIGNMENT CONFIG_TPDRQ_SIZE
  133. /* table 2.30 host status page detail */
  134. #define HSP_ALIGNMENT 0x400 /* must align on 1k boundary */
  135. struct he_hsp {
  136. struct he_hsp_entry {
  137. volatile u32 tbrq_tail;
  138. volatile u32 reserved1[15];
  139. volatile u32 rbrq_tail;
  140. volatile u32 reserved2[15];
  141. } group[HE_NUM_GROUPS];
  142. };
  143. /*
  144. * figure 2.9 receive buffer pools
  145. *
  146. * since a virtual address might be more than 32 bits, we store an index
  147. * in the virt member of he_rbp. NOTE: the lower six bits in the rbrq
  148. * addr member are used for buffer status further limiting us to 26 bits.
  149. */
  150. struct he_rbp {
  151. volatile u32 phys;
  152. volatile u32 idx; /* virt */
  153. };
  154. #define RBP_IDX_OFFSET 6
  155. /*
  156. * the he dma engine will try to hold an extra 16 buffers in its local
  157. * caches. and add a couple buffers for safety.
  158. */
  159. #define RBPL_TABLE_SIZE (CONFIG_RBPL_SIZE + 16 + 2)
  160. struct he_buff {
  161. struct list_head entry;
  162. dma_addr_t mapping;
  163. unsigned long len;
  164. u8 data[];
  165. };
  166. #ifdef notyet
  167. struct he_group {
  168. u32 rpbl_size, rpbl_qsize;
  169. struct he_rpb_entry *rbpl_ba;
  170. };
  171. #endif
  172. #define HE_LOOKUP_VCC(dev, cid) ((dev)->he_vcc_table[(cid)].vcc)
  173. struct he_vcc_table
  174. {
  175. struct atm_vcc *vcc;
  176. };
  177. struct he_cs_stper
  178. {
  179. long pcr;
  180. int inuse;
  181. };
  182. #define HE_NUM_CS_STPER 16
  183. struct he_dev {
  184. unsigned int number;
  185. unsigned int irq;
  186. void __iomem *membase;
  187. char prod_id[30];
  188. char mac_addr[6];
  189. int media;
  190. unsigned int vcibits, vpibits;
  191. unsigned int cells_per_row;
  192. unsigned int bytes_per_row;
  193. unsigned int cells_per_lbuf;
  194. unsigned int r0_numrows, r0_startrow, r0_numbuffs;
  195. unsigned int r1_numrows, r1_startrow, r1_numbuffs;
  196. unsigned int tx_numrows, tx_startrow, tx_numbuffs;
  197. unsigned int buffer_limit;
  198. struct he_vcc_table *he_vcc_table;
  199. #ifdef notyet
  200. struct he_group group[HE_NUM_GROUPS];
  201. #endif
  202. struct he_cs_stper cs_stper[HE_NUM_CS_STPER];
  203. unsigned total_bw;
  204. dma_addr_t irq_phys;
  205. struct he_irq *irq_base, *irq_head, *irq_tail;
  206. volatile unsigned *irq_tailoffset;
  207. int irq_peak;
  208. struct tasklet_struct tasklet;
  209. struct dma_pool *tpd_pool;
  210. struct list_head outstanding_tpds;
  211. dma_addr_t tpdrq_phys;
  212. struct he_tpdrq *tpdrq_base, *tpdrq_tail, *tpdrq_head;
  213. spinlock_t global_lock; /* 8.1.5 pci transaction ordering
  214. error problem */
  215. dma_addr_t rbrq_phys;
  216. struct he_rbrq *rbrq_base, *rbrq_head;
  217. int rbrq_peak;
  218. struct he_buff **rbpl_virt;
  219. unsigned long *rbpl_table;
  220. unsigned long rbpl_hint;
  221. struct dma_pool *rbpl_pool;
  222. dma_addr_t rbpl_phys;
  223. struct he_rbp *rbpl_base, *rbpl_tail;
  224. struct list_head rbpl_outstanding;
  225. int rbpl_peak;
  226. dma_addr_t tbrq_phys;
  227. struct he_tbrq *tbrq_base, *tbrq_head;
  228. int tbrq_peak;
  229. dma_addr_t hsp_phys;
  230. struct he_hsp *hsp;
  231. struct pci_dev *pci_dev;
  232. struct atm_dev *atm_dev;
  233. struct he_dev *next;
  234. };
  235. #define HE_MAXIOV 20
  236. struct he_vcc
  237. {
  238. struct list_head buffers;
  239. int pdu_len;
  240. int rc_index;
  241. wait_queue_head_t rx_waitq;
  242. wait_queue_head_t tx_waitq;
  243. };
  244. #define HE_VCC(vcc) ((struct he_vcc *)(vcc->dev_data))
  245. #define PCI_VENDOR_ID_FORE 0x1127
  246. #define PCI_DEVICE_ID_FORE_HE 0x400
  247. #define GEN_CNTL_0 0x40
  248. #define INT_PROC_ENBL (1<<25)
  249. #define SLAVE_ENDIAN_MODE (1<<16)
  250. #define MRL_ENB (1<<5)
  251. #define MRM_ENB (1<<4)
  252. #define INIT_ENB (1<<2)
  253. #define IGNORE_TIMEOUT (1<<1)
  254. #define ENBL_64 (1<<0)
  255. #define MIN_PCI_LATENCY 32 /* errata 8.1.3 */
  256. #define HE_DEV(dev) ((struct he_dev *) (dev)->dev_data)
  257. #define he_is622(dev) ((dev)->media & 0x1)
  258. #define he_isMM(dev) ((dev)->media & 0x20)
  259. #define HE_REGMAP_SIZE 0x100000
  260. #define RESET_CNTL 0x80000
  261. #define BOARD_RST_STATUS (1<<6)
  262. #define HOST_CNTL 0x80004
  263. #define PCI_BUS_SIZE64 (1<<27)
  264. #define DESC_RD_STATIC_64 (1<<26)
  265. #define DATA_RD_STATIC_64 (1<<25)
  266. #define DATA_WR_STATIC_64 (1<<24)
  267. #define ID_CS (1<<12)
  268. #define ID_WREN (1<<11)
  269. #define ID_DOUT (1<<10)
  270. #define ID_DOFFSET 10
  271. #define ID_DIN (1<<9)
  272. #define ID_CLOCK (1<<8)
  273. #define QUICK_RD_RETRY (1<<7)
  274. #define QUICK_WR_RETRY (1<<6)
  275. #define OUTFF_ENB (1<<5)
  276. #define CMDFF_ENB (1<<4)
  277. #define PERR_INT_ENB (1<<2)
  278. #define IGNORE_INTR (1<<0)
  279. #define LB_SWAP 0x80008
  280. #define SWAP_RNUM_MAX(x) (x<<27)
  281. #define DATA_WR_SWAP (1<<20)
  282. #define DESC_RD_SWAP (1<<19)
  283. #define DATA_RD_SWAP (1<<18)
  284. #define INTR_SWAP (1<<17)
  285. #define DESC_WR_SWAP (1<<16)
  286. #define SDRAM_INIT (1<<15)
  287. #define BIG_ENDIAN_HOST (1<<14)
  288. #define XFER_SIZE (1<<7)
  289. #define LB_MEM_ADDR 0x8000c
  290. #define LB_MEM_DATA 0x80010
  291. #define LB_MEM_ACCESS 0x80014
  292. #define LB_MEM_HNDSHK (1<<30)
  293. #define LM_MEM_WRITE (0x7)
  294. #define LM_MEM_READ (0x3)
  295. #define SDRAM_CTL 0x80018
  296. #define LB_64_ENB (1<<3)
  297. #define LB_TWR (1<<2)
  298. #define LB_TRP (1<<1)
  299. #define LB_TRAS (1<<0)
  300. #define INT_FIFO 0x8001c
  301. #define INT_MASK_D (1<<15)
  302. #define INT_MASK_C (1<<14)
  303. #define INT_MASK_B (1<<13)
  304. #define INT_MASK_A (1<<12)
  305. #define INT_CLEAR_D (1<<11)
  306. #define INT_CLEAR_C (1<<10)
  307. #define INT_CLEAR_B (1<<9)
  308. #define INT_CLEAR_A (1<<8)
  309. #define ABORT_ADDR 0x80020
  310. #define IRQ0_BASE 0x80080
  311. #define IRQ_BASE(x) (x<<12)
  312. #define IRQ_MASK ((CONFIG_IRQ_SIZE<<2)-1) /* was 0x3ff */
  313. #define IRQ_TAIL(x) (((unsigned long)(x)) & IRQ_MASK)
  314. #define IRQ0_HEAD 0x80084
  315. #define IRQ_SIZE(x) (x<<22)
  316. #define IRQ_THRESH(x) (x<<12)
  317. #define IRQ_HEAD(x) (x<<2)
  318. /* #define IRQ_PENDING (1) conflict with linux/irq.h */
  319. #define IRQ0_CNTL 0x80088
  320. #define IRQ_ADDRSEL(x) (x<<2)
  321. #define IRQ_INT_A (0<<2)
  322. #define IRQ_INT_B (1<<2)
  323. #define IRQ_INT_C (2<<2)
  324. #define IRQ_INT_D (3<<2)
  325. #define IRQ_TYPE_ADDR 0x1
  326. #define IRQ_TYPE_LINE 0x0
  327. #define IRQ0_DATA 0x8008c
  328. #define IRQ1_BASE 0x80090
  329. #define IRQ1_HEAD 0x80094
  330. #define IRQ1_CNTL 0x80098
  331. #define IRQ1_DATA 0x8009c
  332. #define IRQ2_BASE 0x800a0
  333. #define IRQ2_HEAD 0x800a4
  334. #define IRQ2_CNTL 0x800a8
  335. #define IRQ2_DATA 0x800ac
  336. #define IRQ3_BASE 0x800b0
  337. #define IRQ3_HEAD 0x800b4
  338. #define IRQ3_CNTL 0x800b8
  339. #define IRQ3_DATA 0x800bc
  340. #define GRP_10_MAP 0x800c0
  341. #define GRP_32_MAP 0x800c4
  342. #define GRP_54_MAP 0x800c8
  343. #define GRP_76_MAP 0x800cc
  344. #define G0_RBPS_S 0x80400
  345. #define G0_RBPS_T 0x80404
  346. #define RBP_TAIL(x) ((x)<<3)
  347. #define RBP_MASK(x) ((x)|0x1fff)
  348. #define G0_RBPS_QI 0x80408
  349. #define RBP_QSIZE(x) ((x)<<14)
  350. #define RBP_INT_ENB (1<<13)
  351. #define RBP_THRESH(x) (x)
  352. #define G0_RBPS_BS 0x8040c
  353. #define G0_RBPL_S 0x80410
  354. #define G0_RBPL_T 0x80414
  355. #define G0_RBPL_QI 0x80418
  356. #define G0_RBPL_BS 0x8041c
  357. #define G1_RBPS_S 0x80420
  358. #define G1_RBPS_T 0x80424
  359. #define G1_RBPS_QI 0x80428
  360. #define G1_RBPS_BS 0x8042c
  361. #define G1_RBPL_S 0x80430
  362. #define G1_RBPL_T 0x80434
  363. #define G1_RBPL_QI 0x80438
  364. #define G1_RBPL_BS 0x8043c
  365. #define G2_RBPS_S 0x80440
  366. #define G2_RBPS_T 0x80444
  367. #define G2_RBPS_QI 0x80448
  368. #define G2_RBPS_BS 0x8044c
  369. #define G2_RBPL_S 0x80450
  370. #define G2_RBPL_T 0x80454
  371. #define G2_RBPL_QI 0x80458
  372. #define G2_RBPL_BS 0x8045c
  373. #define G3_RBPS_S 0x80460
  374. #define G3_RBPS_T 0x80464
  375. #define G3_RBPS_QI 0x80468
  376. #define G3_RBPS_BS 0x8046c
  377. #define G3_RBPL_S 0x80470
  378. #define G3_RBPL_T 0x80474
  379. #define G3_RBPL_QI 0x80478
  380. #define G3_RBPL_BS 0x8047c
  381. #define G4_RBPS_S 0x80480
  382. #define G4_RBPS_T 0x80484
  383. #define G4_RBPS_QI 0x80488
  384. #define G4_RBPS_BS 0x8048c
  385. #define G4_RBPL_S 0x80490
  386. #define G4_RBPL_T 0x80494
  387. #define G4_RBPL_QI 0x80498
  388. #define G4_RBPL_BS 0x8049c
  389. #define G5_RBPS_S 0x804a0
  390. #define G5_RBPS_T 0x804a4
  391. #define G5_RBPS_QI 0x804a8
  392. #define G5_RBPS_BS 0x804ac
  393. #define G5_RBPL_S 0x804b0
  394. #define G5_RBPL_T 0x804b4
  395. #define G5_RBPL_QI 0x804b8
  396. #define G5_RBPL_BS 0x804bc
  397. #define G6_RBPS_S 0x804c0
  398. #define G6_RBPS_T 0x804c4
  399. #define G6_RBPS_QI 0x804c8
  400. #define G6_RBPS_BS 0x804cc
  401. #define G6_RBPL_S 0x804d0
  402. #define G6_RBPL_T 0x804d4
  403. #define G6_RBPL_QI 0x804d8
  404. #define G6_RBPL_BS 0x804dc
  405. #define G7_RBPS_S 0x804e0
  406. #define G7_RBPS_T 0x804e4
  407. #define G7_RBPS_QI 0x804e8
  408. #define G7_RBPS_BS 0x804ec
  409. #define G7_RBPL_S 0x804f0
  410. #define G7_RBPL_T 0x804f4
  411. #define G7_RBPL_QI 0x804f8
  412. #define G7_RBPL_BS 0x804fc
  413. #define G0_RBRQ_ST 0x80500
  414. #define G0_RBRQ_H 0x80504
  415. #define G0_RBRQ_Q 0x80508
  416. #define RBRQ_THRESH(x) ((x)<<13)
  417. #define RBRQ_SIZE(x) (x)
  418. #define G0_RBRQ_I 0x8050c
  419. #define RBRQ_TIME(x) ((x)<<8)
  420. #define RBRQ_COUNT(x) (x)
  421. /* fill in 1 ... 7 later */
  422. #define G0_TBRQ_B_T 0x80600
  423. #define G0_TBRQ_H 0x80604
  424. #define G0_TBRQ_S 0x80608
  425. #define G0_TBRQ_THRESH 0x8060c
  426. #define TBRQ_THRESH(x) (x)
  427. /* fill in 1 ... 7 later */
  428. #define RH_CONFIG 0x805c0
  429. #define PHY_INT_ENB (1<<10)
  430. #define OAM_GID(x) (x<<7)
  431. #define PTMR_PRE(x) (x)
  432. #define G0_INMQ_S 0x80580
  433. #define G0_INMQ_L 0x80584
  434. #define G1_INMQ_S 0x80588
  435. #define G1_INMQ_L 0x8058c
  436. #define G2_INMQ_S 0x80590
  437. #define G2_INMQ_L 0x80594
  438. #define G3_INMQ_S 0x80598
  439. #define G3_INMQ_L 0x8059c
  440. #define G4_INMQ_S 0x805a0
  441. #define G4_INMQ_L 0x805a4
  442. #define G5_INMQ_S 0x805a8
  443. #define G5_INMQ_L 0x805ac
  444. #define G6_INMQ_S 0x805b0
  445. #define G6_INMQ_L 0x805b4
  446. #define G7_INMQ_S 0x805b8
  447. #define G7_INMQ_L 0x805bc
  448. #define TPDRQ_B_H 0x80680
  449. #define TPDRQ_T 0x80684
  450. #define TPDRQ_S 0x80688
  451. #define UBUFF_BA 0x8068c
  452. #define RLBF0_H 0x806c0
  453. #define RLBF0_T 0x806c4
  454. #define RLBF1_H 0x806c8
  455. #define RLBF1_T 0x806cc
  456. #define RLBC_H 0x806d0
  457. #define RLBC_T 0x806d4
  458. #define RLBC_H2 0x806d8
  459. #define TLBF_H 0x806e0
  460. #define TLBF_T 0x806e4
  461. #define RLBF0_C 0x806e8
  462. #define RLBF1_C 0x806ec
  463. #define RXTHRSH 0x806f0
  464. #define LITHRSH 0x806f4
  465. #define LBARB 0x80700
  466. #define SLICE_X(x) (x<<28)
  467. #define ARB_RNUM_MAX(x) (x<<23)
  468. #define TH_PRTY(x) (x<<21)
  469. #define RH_PRTY(x) (x<<19)
  470. #define TL_PRTY(x) (x<<17)
  471. #define RL_PRTY(x) (x<<15)
  472. #define BUS_MULTI(x) (x<<8)
  473. #define NET_PREF(x) (x)
  474. #define SDRAMCON 0x80704
  475. #define BANK_ON (1<<14)
  476. #define WIDE_DATA (1<<13)
  477. #define TWR_WAIT (1<<12)
  478. #define TRP_WAIT (1<<11)
  479. #define TRAS_WAIT (1<<10)
  480. #define REF_RATE(x) (x)
  481. #define LBSTAT 0x80708
  482. #define RCC_STAT 0x8070c
  483. #define RCC_BUSY (1)
  484. #define TCMCONFIG 0x80740
  485. #define TM_DESL2 (1<<10)
  486. #define TM_BANK_WAIT(x) (x<<6)
  487. #define TM_ADD_BANK4(x) (x<<4)
  488. #define TM_PAR_CHECK(x) (x<<3)
  489. #define TM_RW_WAIT(x) (x<<2)
  490. #define TM_SRAM_TYPE(x) (x)
  491. #define TSRB_BA 0x80744
  492. #define TSRC_BA 0x80748
  493. #define TMABR_BA 0x8074c
  494. #define TPD_BA 0x80750
  495. #define TSRD_BA 0x80758
  496. #define TX_CONFIG 0x80760
  497. #define DRF_THRESH(x) (x<<22)
  498. #define TX_UT_MODE(x) (x<<21)
  499. #define TX_VCI_MASK(x) (x<<17)
  500. #define LBFREE_CNT(x) (x)
  501. #define TXAAL5_PROTO 0x80764
  502. #define CPCS_UU(x) (x<<8)
  503. #define CPI(x) (x)
  504. #define RCMCONFIG 0x80780
  505. #define RM_DESL2(x) (x<<10)
  506. #define RM_BANK_WAIT(x) (x<<6)
  507. #define RM_ADD_BANK(x) (x<<4)
  508. #define RM_PAR_CHECK(x) (x<<3)
  509. #define RM_RW_WAIT(x) (x<<2)
  510. #define RM_SRAM_TYPE(x) (x)
  511. #define RCMRSRB_BA 0x80784
  512. #define RCMLBM_BA 0x80788
  513. #define RCMABR_BA 0x8078c
  514. #define RC_CONFIG 0x807c0
  515. #define UT_RD_DELAY(x) (x<<11)
  516. #define WRAP_MODE(x) (x<<10)
  517. #define RC_UT_MODE(x) (x<<9)
  518. #define RX_ENABLE (1<<8)
  519. #define RX_VALVP(x) (x<<4)
  520. #define RX_VALVC(x) (x)
  521. #define MCC 0x807c4
  522. #define OEC 0x807c8
  523. #define DCC 0x807cc
  524. #define CEC 0x807d0
  525. #define HSP_BA 0x807f0
  526. #define LB_CONFIG 0x807f4
  527. #define LB_SIZE(x) (x)
  528. #define CON_DAT 0x807f8
  529. #define CON_CTL 0x807fc
  530. #define CON_CTL_MBOX (2<<30)
  531. #define CON_CTL_TCM (1<<30)
  532. #define CON_CTL_RCM (0<<30)
  533. #define CON_CTL_WRITE (1<<29)
  534. #define CON_CTL_READ (0<<29)
  535. #define CON_CTL_BUSY (1<<28)
  536. #define CON_BYTE_DISABLE_3 (1<<22) /* 24..31 */
  537. #define CON_BYTE_DISABLE_2 (1<<21) /* 16..23 */
  538. #define CON_BYTE_DISABLE_1 (1<<20) /* 8..15 */
  539. #define CON_BYTE_DISABLE_0 (1<<19) /* 0..7 */
  540. #define CON_CTL_ADDR(x) (x)
  541. #define FRAMER 0x80800 /* to 0x80bfc */
  542. /* 3.3 network controller (internal) mailbox registers */
  543. #define CS_STPER0 0x0
  544. /* ... */
  545. #define CS_STPER31 0x01f
  546. #define CS_STTIM0 0x020
  547. /* ... */
  548. #define CS_STTIM31 0x03f
  549. #define CS_TGRLD0 0x040
  550. /* ... */
  551. #define CS_TGRLD15 0x04f
  552. #define CS_ERTHR0 0x050
  553. #define CS_ERTHR1 0x051
  554. #define CS_ERTHR2 0x052
  555. #define CS_ERTHR3 0x053
  556. #define CS_ERTHR4 0x054
  557. #define CS_ERCTL0 0x055
  558. #define TX_ENABLE (1<<28)
  559. #define ER_ENABLE (1<<27)
  560. #define CS_ERCTL1 0x056
  561. #define CS_ERCTL2 0x057
  562. #define CS_ERSTAT0 0x058
  563. #define CS_ERSTAT1 0x059
  564. #define CS_RTCCT 0x060
  565. #define CS_RTFWC 0x061
  566. #define CS_RTFWR 0x062
  567. #define CS_RTFTC 0x063
  568. #define CS_RTATR 0x064
  569. #define CS_TFBSET 0x070
  570. #define CS_TFBADD 0x071
  571. #define CS_TFBSUB 0x072
  572. #define CS_WCRMAX 0x073
  573. #define CS_WCRMIN 0x074
  574. #define CS_WCRINC 0x075
  575. #define CS_WCRDEC 0x076
  576. #define CS_WCRCEIL 0x077
  577. #define CS_BWDCNT 0x078
  578. #define CS_OTPPER 0x080
  579. #define CS_OTWPER 0x081
  580. #define CS_OTTLIM 0x082
  581. #define CS_OTTCNT 0x083
  582. #define CS_HGRRT0 0x090
  583. /* ... */
  584. #define CS_HGRRT7 0x097
  585. #define CS_ORPTRS 0x0a0
  586. #define RXCON_CLOSE 0x100
  587. #define RCM_MEM_SIZE 0x10000 /* 1M of 32-bit registers */
  588. #define TCM_MEM_SIZE 0x20000 /* 2M of 32-bit registers */
  589. /* 2.5 transmit connection memory registers */
  590. #define TSR0_CONN_STATE(x) ((x>>28) & 0x7)
  591. #define TSR0_USE_WMIN (1<<23)
  592. #define TSR0_GROUP(x) ((x & 0x7)<<18)
  593. #define TSR0_ABR (2<<16)
  594. #define TSR0_UBR (1<<16)
  595. #define TSR0_CBR (0<<16)
  596. #define TSR0_PROT (1<<15)
  597. #define TSR0_AAL0_SDU (2<<12)
  598. #define TSR0_AAL0 (1<<12)
  599. #define TSR0_AAL5 (0<<12)
  600. #define TSR0_HALT_ER (1<<11)
  601. #define TSR0_MARK_CI (1<<10)
  602. #define TSR0_MARK_ER (1<<9)
  603. #define TSR0_UPDATE_GER (1<<8)
  604. #define TSR0_RC_INDEX(x) (x & 0x1F)
  605. #define TSR1_PCR(x) ((x & 0x7FFF)<<16)
  606. #define TSR1_MCR(x) (x & 0x7FFF)
  607. #define TSR2_ACR(x) ((x & 0x7FFF)<<16)
  608. #define TSR3_NRM_CNT(x) ((x & 0xFF)<<24)
  609. #define TSR3_CRM_CNT(x) (x & 0xFFFF)
  610. #define TSR4_FLUSH_CONN (1<<31)
  611. #define TSR4_SESSION_ENDED (1<<30)
  612. #define TSR4_CRC10 (1<<28)
  613. #define TSR4_NULL_CRC10 (1<<27)
  614. #define TSR4_PROT (1<<26)
  615. #define TSR4_AAL0_SDU (2<<23)
  616. #define TSR4_AAL0 (1<<23)
  617. #define TSR4_AAL5 (0<<23)
  618. #define TSR9_OPEN_CONN (1<<20)
  619. #define TSR11_ICR(x) ((x & 0x7FFF)<<16)
  620. #define TSR11_TRM(x) ((x & 0x7)<<13)
  621. #define TSR11_NRM(x) ((x & 0x7)<<10)
  622. #define TSR11_ADTF(x) (x & 0x3FF)
  623. #define TSR13_RDF(x) ((x & 0xF)<<23)
  624. #define TSR13_RIF(x) ((x & 0xF)<<19)
  625. #define TSR13_CDF(x) ((x & 0x7)<<16)
  626. #define TSR13_CRM(x) (x & 0xFFFF)
  627. #define TSR14_DELETE (1<<31)
  628. #define TSR14_ABR_CLOSE (1<<16)
  629. /* 2.7.1 per connection receieve state registers */
  630. #define RSR0_START_PDU (1<<10)
  631. #define RSR0_OPEN_CONN (1<<6)
  632. #define RSR0_CLOSE_CONN (0<<6)
  633. #define RSR0_PPD_ENABLE (1<<5)
  634. #define RSR0_EPD_ENABLE (1<<4)
  635. #define RSR0_TCP_CKSUM (1<<3)
  636. #define RSR0_AAL5 (0)
  637. #define RSR0_AAL0 (1)
  638. #define RSR0_AAL0_SDU (2)
  639. #define RSR0_RAWCELL (3)
  640. #define RSR0_RAWCELL_CRC10 (4)
  641. #define RSR1_AQI_ENABLE (1<<20)
  642. #define RSR1_RBPL_ONLY (1<<19)
  643. #define RSR1_GROUP(x) ((x)<<16)
  644. #define RSR4_AQI_ENABLE (1<<30)
  645. #define RSR4_GROUP(x) ((x)<<27)
  646. #define RSR4_RBPL_ONLY (1<<26)
  647. /* 2.1.4 transmit packet descriptor */
  648. #define TPD_USERCELL 0x0
  649. #define TPD_SEGMENT_OAMF5 0x4
  650. #define TPD_END2END_OAMF5 0x5
  651. #define TPD_RMCELL 0x6
  652. #define TPD_CELLTYPE(x) (x<<3)
  653. #define TPD_EOS (1<<2)
  654. #define TPD_CLP (1<<1)
  655. #define TPD_INT (1<<0)
  656. #define TPD_LST (1<<31)
  657. /* table 4.3 serial eeprom information */
  658. #define PROD_ID 0x08 /* char[] */
  659. #define PROD_ID_LEN 30
  660. #define HW_REV 0x26 /* char[] */
  661. #define M_SN 0x3a /* integer */
  662. #define MEDIA 0x3e /* integer */
  663. #define HE155MM 0x26
  664. #define HE622MM 0x27
  665. #define HE155SM 0x46
  666. #define HE622SM 0x47
  667. #define MAC_ADDR 0x42 /* char[] */
  668. #define CS_LOW 0x0
  669. #define CS_HIGH ID_CS /* HOST_CNTL_ID_PROM_SEL */
  670. #define CLK_LOW 0x0
  671. #define CLK_HIGH ID_CLOCK /* HOST_CNTL_ID_PROM_CLOCK */
  672. #define SI_HIGH ID_DIN /* HOST_CNTL_ID_PROM_DATA_IN */
  673. #define EEPROM_DELAY 400 /* microseconds */
  674. #endif /* _HE_H_ */