intel-agp.h 6.6 KB

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  1. /*
  2. * Common Intel AGPGART and GTT definitions.
  3. */
  4. #ifndef _INTEL_AGP_H
  5. #define _INTEL_AGP_H
  6. /* Intel registers */
  7. #define INTEL_APSIZE 0xb4
  8. #define INTEL_ATTBASE 0xb8
  9. #define INTEL_AGPCTRL 0xb0
  10. #define INTEL_NBXCFG 0x50
  11. #define INTEL_ERRSTS 0x91
  12. /* Intel i830 registers */
  13. #define I830_GMCH_CTRL 0x52
  14. #define I830_GMCH_ENABLED 0x4
  15. #define I830_GMCH_MEM_MASK 0x1
  16. #define I830_GMCH_MEM_64M 0x1
  17. #define I830_GMCH_MEM_128M 0
  18. #define I830_GMCH_GMS_MASK 0x70
  19. #define I830_GMCH_GMS_DISABLED 0x00
  20. #define I830_GMCH_GMS_LOCAL 0x10
  21. #define I830_GMCH_GMS_STOLEN_512 0x20
  22. #define I830_GMCH_GMS_STOLEN_1024 0x30
  23. #define I830_GMCH_GMS_STOLEN_8192 0x40
  24. #define I830_RDRAM_CHANNEL_TYPE 0x03010
  25. #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
  26. #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
  27. /* This one is for I830MP w. an external graphic card */
  28. #define INTEL_I830_ERRSTS 0x92
  29. /* Intel 855GM/852GM registers */
  30. #define I855_GMCH_GMS_MASK 0xF0
  31. #define I855_GMCH_GMS_STOLEN_0M 0x0
  32. #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
  33. #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
  34. #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
  35. #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
  36. #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
  37. #define I85X_CAPID 0x44
  38. #define I85X_VARIANT_MASK 0x7
  39. #define I85X_VARIANT_SHIFT 5
  40. #define I855_GME 0x0
  41. #define I855_GM 0x4
  42. #define I852_GME 0x2
  43. #define I852_GM 0x5
  44. /* Intel i845 registers */
  45. #define INTEL_I845_AGPM 0x51
  46. #define INTEL_I845_ERRSTS 0xc8
  47. /* Intel i860 registers */
  48. #define INTEL_I860_MCHCFG 0x50
  49. #define INTEL_I860_ERRSTS 0xc8
  50. /* Intel i810 registers */
  51. #define I810_GMADR_BAR 0
  52. #define I810_MMADR_BAR 1
  53. #define I810_PTE_BASE 0x10000
  54. #define I810_PTE_MAIN_UNCACHED 0x00000000
  55. #define I810_PTE_LOCAL 0x00000002
  56. #define I810_PTE_VALID 0x00000001
  57. #define I830_PTE_SYSTEM_CACHED 0x00000006
  58. #define I810_SMRAM_MISCC 0x70
  59. #define I810_GFX_MEM_WIN_SIZE 0x00010000
  60. #define I810_GFX_MEM_WIN_32M 0x00010000
  61. #define I810_GMS 0x000000c0
  62. #define I810_GMS_DISABLE 0x00000000
  63. #define I810_PGETBL_CTL 0x2020
  64. #define I810_PGETBL_ENABLED 0x00000001
  65. /* Note: PGETBL_CTL2 has a different offset on G33. */
  66. #define I965_PGETBL_CTL2 0x20c4
  67. #define I965_PGETBL_SIZE_MASK 0x0000000e
  68. #define I965_PGETBL_SIZE_512KB (0 << 1)
  69. #define I965_PGETBL_SIZE_256KB (1 << 1)
  70. #define I965_PGETBL_SIZE_128KB (2 << 1)
  71. #define I965_PGETBL_SIZE_1MB (3 << 1)
  72. #define I965_PGETBL_SIZE_2MB (4 << 1)
  73. #define I965_PGETBL_SIZE_1_5MB (5 << 1)
  74. #define G33_GMCH_SIZE_MASK (3 << 8)
  75. #define G33_GMCH_SIZE_1M (1 << 8)
  76. #define G33_GMCH_SIZE_2M (2 << 8)
  77. #define G4x_GMCH_SIZE_MASK (0xf << 8)
  78. #define G4x_GMCH_SIZE_1M (0x1 << 8)
  79. #define G4x_GMCH_SIZE_2M (0x3 << 8)
  80. #define G4x_GMCH_SIZE_VT_EN (0x8 << 8)
  81. #define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
  82. #define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
  83. #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
  84. #define GFX_FLSH_CNTL 0x2170 /* 915+ */
  85. #define I810_DRAM_CTL 0x3000
  86. #define I810_DRAM_ROW_0 0x00000001
  87. #define I810_DRAM_ROW_0_SDRAM 0x00000001
  88. /* Intel 815 register */
  89. #define INTEL_815_APCONT 0x51
  90. #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
  91. /* Intel i820 registers */
  92. #define INTEL_I820_RDCR 0x51
  93. #define INTEL_I820_ERRSTS 0xc8
  94. /* Intel i840 registers */
  95. #define INTEL_I840_MCHCFG 0x50
  96. #define INTEL_I840_ERRSTS 0xc8
  97. /* Intel i850 registers */
  98. #define INTEL_I850_MCHCFG 0x50
  99. #define INTEL_I850_ERRSTS 0xc8
  100. /* intel 915G registers */
  101. #define I915_GMADR_BAR 2
  102. #define I915_MMADR_BAR 0
  103. #define I915_PTE_BAR 3
  104. #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
  105. #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
  106. #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
  107. #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
  108. #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
  109. #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
  110. #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
  111. #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
  112. #define I915_IFPADDR 0x60
  113. #define I830_HIC 0x70
  114. /* Intel 965G registers */
  115. #define I965_MSAC 0x62
  116. #define I965_IFPADDR 0x70
  117. /* Intel 7505 registers */
  118. #define INTEL_I7505_APSIZE 0x74
  119. #define INTEL_I7505_NCAPID 0x60
  120. #define INTEL_I7505_NISTAT 0x6c
  121. #define INTEL_I7505_ATTBASE 0x78
  122. #define INTEL_I7505_ERRSTS 0x42
  123. #define INTEL_I7505_AGPCTRL 0x70
  124. #define INTEL_I7505_MCHCFG 0x50
  125. /* pci devices ids */
  126. #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
  127. #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
  128. #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
  129. #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
  130. #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
  131. #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
  132. #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
  133. #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
  134. #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
  135. #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
  136. #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
  137. #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
  138. #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
  139. #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
  140. #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
  141. #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
  142. #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
  143. #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
  144. #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
  145. #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
  146. #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
  147. #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
  148. #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
  149. #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
  150. #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
  151. #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
  152. #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
  153. #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
  154. #define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90
  155. #define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92
  156. #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
  157. #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
  158. #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
  159. #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
  160. #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
  161. #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
  162. #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
  163. #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
  164. #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
  165. #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
  166. #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
  167. #define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
  168. #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
  169. #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
  170. #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
  171. #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
  172. #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
  173. #endif