synclink_cs.c 109 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/io.h>
  60. #include <asm/irq.h>
  61. #include <asm/dma.h>
  62. #include <linux/bitops.h>
  63. #include <asm/types.h>
  64. #include <linux/termios.h>
  65. #include <linux/workqueue.h>
  66. #include <linux/hdlc.h>
  67. #include <pcmcia/cistpl.h>
  68. #include <pcmcia/cisreg.h>
  69. #include <pcmcia/ds.h>
  70. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  71. #define SYNCLINK_GENERIC_HDLC 1
  72. #else
  73. #define SYNCLINK_GENERIC_HDLC 0
  74. #endif
  75. #define GET_USER(error,value,addr) error = get_user(value,addr)
  76. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79. #include <asm/uaccess.h>
  80. static MGSL_PARAMS default_params = {
  81. MGSL_MODE_HDLC, /* unsigned long mode */
  82. 0, /* unsigned char loopback; */
  83. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  84. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  85. 0, /* unsigned long clock_speed; */
  86. 0xff, /* unsigned char addr_filter; */
  87. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  88. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  89. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  90. 9600, /* unsigned long data_rate; */
  91. 8, /* unsigned char data_bits; */
  92. 1, /* unsigned char stop_bits; */
  93. ASYNC_PARITY_NONE /* unsigned char parity; */
  94. };
  95. typedef struct {
  96. int count;
  97. unsigned char status;
  98. char data[1];
  99. } RXBUF;
  100. /* The queue of BH actions to be performed */
  101. #define BH_RECEIVE 1
  102. #define BH_TRANSMIT 2
  103. #define BH_STATUS 4
  104. #define IO_PIN_SHUTDOWN_LIMIT 100
  105. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  106. struct _input_signal_events {
  107. int ri_up;
  108. int ri_down;
  109. int dsr_up;
  110. int dsr_down;
  111. int dcd_up;
  112. int dcd_down;
  113. int cts_up;
  114. int cts_down;
  115. };
  116. /*
  117. * Device instance data structure
  118. */
  119. typedef struct _mgslpc_info {
  120. struct tty_port port;
  121. void *if_ptr; /* General purpose pointer (used by SPPP) */
  122. int magic;
  123. int line;
  124. struct mgsl_icount icount;
  125. int timeout;
  126. int x_char; /* xon/xoff character */
  127. unsigned char read_status_mask;
  128. unsigned char ignore_status_mask;
  129. unsigned char *tx_buf;
  130. int tx_put;
  131. int tx_get;
  132. int tx_count;
  133. /* circular list of fixed length rx buffers */
  134. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  135. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  136. int rx_put; /* index of next empty rx buffer */
  137. int rx_get; /* index of next full rx buffer */
  138. int rx_buf_size; /* size in bytes of single rx buffer */
  139. int rx_buf_count; /* total number of rx buffers */
  140. int rx_frame_count; /* number of full rx buffers */
  141. wait_queue_head_t status_event_wait_q;
  142. wait_queue_head_t event_wait_q;
  143. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  144. struct _mgslpc_info *next_device; /* device list link */
  145. unsigned short imra_value;
  146. unsigned short imrb_value;
  147. unsigned char pim_value;
  148. spinlock_t lock;
  149. struct work_struct task; /* task structure for scheduling bh */
  150. u32 max_frame_size;
  151. u32 pending_bh;
  152. bool bh_running;
  153. bool bh_requested;
  154. int dcd_chkcount; /* check counts to prevent */
  155. int cts_chkcount; /* too many IRQs if a signal */
  156. int dsr_chkcount; /* is floating */
  157. int ri_chkcount;
  158. bool rx_enabled;
  159. bool rx_overflow;
  160. bool tx_enabled;
  161. bool tx_active;
  162. bool tx_aborting;
  163. u32 idle_mode;
  164. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  165. char device_name[25]; /* device instance name */
  166. unsigned int io_base; /* base I/O address of adapter */
  167. unsigned int irq_level;
  168. MGSL_PARAMS params; /* communications parameters */
  169. unsigned char serial_signals; /* current serial signal states */
  170. bool irq_occurred; /* for diagnostics use */
  171. char testing_irq;
  172. unsigned int init_error; /* startup error (DIAGS) */
  173. char *flag_buf;
  174. bool drop_rts_on_tx_done;
  175. struct _input_signal_events input_signal_events;
  176. /* PCMCIA support */
  177. struct pcmcia_device *p_dev;
  178. int stop;
  179. /* SPPP/Cisco HDLC device parts */
  180. int netcount;
  181. spinlock_t netlock;
  182. #if SYNCLINK_GENERIC_HDLC
  183. struct net_device *netdev;
  184. #endif
  185. } MGSLPC_INFO;
  186. #define MGSLPC_MAGIC 0x5402
  187. /*
  188. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  189. */
  190. #define TXBUFSIZE 4096
  191. #define CHA 0x00 /* channel A offset */
  192. #define CHB 0x40 /* channel B offset */
  193. /*
  194. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  195. */
  196. #undef PVR
  197. #define RXFIFO 0
  198. #define TXFIFO 0
  199. #define STAR 0x20
  200. #define CMDR 0x20
  201. #define RSTA 0x21
  202. #define PRE 0x21
  203. #define MODE 0x22
  204. #define TIMR 0x23
  205. #define XAD1 0x24
  206. #define XAD2 0x25
  207. #define RAH1 0x26
  208. #define RAH2 0x27
  209. #define DAFO 0x27
  210. #define RAL1 0x28
  211. #define RFC 0x28
  212. #define RHCR 0x29
  213. #define RAL2 0x29
  214. #define RBCL 0x2a
  215. #define XBCL 0x2a
  216. #define RBCH 0x2b
  217. #define XBCH 0x2b
  218. #define CCR0 0x2c
  219. #define CCR1 0x2d
  220. #define CCR2 0x2e
  221. #define CCR3 0x2f
  222. #define VSTR 0x34
  223. #define BGR 0x34
  224. #define RLCR 0x35
  225. #define AML 0x36
  226. #define AMH 0x37
  227. #define GIS 0x38
  228. #define IVA 0x38
  229. #define IPC 0x39
  230. #define ISR 0x3a
  231. #define IMR 0x3a
  232. #define PVR 0x3c
  233. #define PIS 0x3d
  234. #define PIM 0x3d
  235. #define PCR 0x3e
  236. #define CCR4 0x3f
  237. // IMR/ISR
  238. #define IRQ_BREAK_ON BIT15 // rx break detected
  239. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  240. #define IRQ_ALLSENT BIT13 // all sent
  241. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  242. #define IRQ_TIMER BIT11 // timer interrupt
  243. #define IRQ_CTS BIT10 // CTS status change
  244. #define IRQ_TXREPEAT BIT9 // tx message repeat
  245. #define IRQ_TXFIFO BIT8 // transmit pool ready
  246. #define IRQ_RXEOM BIT7 // receive message end
  247. #define IRQ_EXITHUNT BIT6 // receive frame start
  248. #define IRQ_RXTIME BIT6 // rx char timeout
  249. #define IRQ_DCD BIT2 // carrier detect status change
  250. #define IRQ_OVERRUN BIT1 // receive frame overflow
  251. #define IRQ_RXFIFO BIT0 // receive pool full
  252. // STAR
  253. #define XFW BIT6 // transmit FIFO write enable
  254. #define CEC BIT2 // command executing
  255. #define CTS BIT1 // CTS state
  256. #define PVR_DTR BIT0
  257. #define PVR_DSR BIT1
  258. #define PVR_RI BIT2
  259. #define PVR_AUTOCTS BIT3
  260. #define PVR_RS232 0x20 /* 0010b */
  261. #define PVR_V35 0xe0 /* 1110b */
  262. #define PVR_RS422 0x40 /* 0100b */
  263. /* Register access functions */
  264. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  265. #define read_reg(info, reg) inb((info)->io_base + (reg))
  266. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  267. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  268. #define set_reg_bits(info, reg, mask) \
  269. write_reg(info, (reg), \
  270. (unsigned char) (read_reg(info, (reg)) | (mask)))
  271. #define clear_reg_bits(info, reg, mask) \
  272. write_reg(info, (reg), \
  273. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  274. /*
  275. * interrupt enable/disable routines
  276. */
  277. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  278. {
  279. if (channel == CHA) {
  280. info->imra_value |= mask;
  281. write_reg16(info, CHA + IMR, info->imra_value);
  282. } else {
  283. info->imrb_value |= mask;
  284. write_reg16(info, CHB + IMR, info->imrb_value);
  285. }
  286. }
  287. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  288. {
  289. if (channel == CHA) {
  290. info->imra_value &= ~mask;
  291. write_reg16(info, CHA + IMR, info->imra_value);
  292. } else {
  293. info->imrb_value &= ~mask;
  294. write_reg16(info, CHB + IMR, info->imrb_value);
  295. }
  296. }
  297. #define port_irq_disable(info, mask) \
  298. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  299. #define port_irq_enable(info, mask) \
  300. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  301. static void rx_start(MGSLPC_INFO *info);
  302. static void rx_stop(MGSLPC_INFO *info);
  303. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  304. static void tx_stop(MGSLPC_INFO *info);
  305. static void tx_set_idle(MGSLPC_INFO *info);
  306. static void get_signals(MGSLPC_INFO *info);
  307. static void set_signals(MGSLPC_INFO *info);
  308. static void reset_device(MGSLPC_INFO *info);
  309. static void hdlc_mode(MGSLPC_INFO *info);
  310. static void async_mode(MGSLPC_INFO *info);
  311. static void tx_timeout(unsigned long context);
  312. static int carrier_raised(struct tty_port *port);
  313. static void dtr_rts(struct tty_port *port, int onoff);
  314. #if SYNCLINK_GENERIC_HDLC
  315. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  316. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  317. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  318. static int hdlcdev_init(MGSLPC_INFO *info);
  319. static void hdlcdev_exit(MGSLPC_INFO *info);
  320. #endif
  321. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  322. static bool register_test(MGSLPC_INFO *info);
  323. static bool irq_test(MGSLPC_INFO *info);
  324. static int adapter_test(MGSLPC_INFO *info);
  325. static int claim_resources(MGSLPC_INFO *info);
  326. static void release_resources(MGSLPC_INFO *info);
  327. static int mgslpc_add_device(MGSLPC_INFO *info);
  328. static void mgslpc_remove_device(MGSLPC_INFO *info);
  329. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  330. static void rx_reset_buffers(MGSLPC_INFO *info);
  331. static int rx_alloc_buffers(MGSLPC_INFO *info);
  332. static void rx_free_buffers(MGSLPC_INFO *info);
  333. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  334. /*
  335. * Bottom half interrupt handlers
  336. */
  337. static void bh_handler(struct work_struct *work);
  338. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  339. static void bh_status(MGSLPC_INFO *info);
  340. /*
  341. * ioctl handlers
  342. */
  343. static int tiocmget(struct tty_struct *tty);
  344. static int tiocmset(struct tty_struct *tty,
  345. unsigned int set, unsigned int clear);
  346. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  347. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  348. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  349. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  350. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  351. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  352. static int tx_abort(MGSLPC_INFO *info);
  353. static int set_rxenable(MGSLPC_INFO *info, int enable);
  354. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  355. static MGSLPC_INFO *mgslpc_device_list = NULL;
  356. static int mgslpc_device_count = 0;
  357. /*
  358. * Set this param to non-zero to load eax with the
  359. * .text section address and breakpoint on module load.
  360. * This is useful for use with gdb and add-symbol-file command.
  361. */
  362. static bool break_on_load;
  363. /*
  364. * Driver major number, defaults to zero to get auto
  365. * assigned major number. May be forced as module parameter.
  366. */
  367. static int ttymajor=0;
  368. static int debug_level = 0;
  369. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  370. module_param(break_on_load, bool, 0);
  371. module_param(ttymajor, int, 0);
  372. module_param(debug_level, int, 0);
  373. module_param_array(maxframe, int, NULL, 0);
  374. MODULE_LICENSE("GPL");
  375. static char *driver_name = "SyncLink PC Card driver";
  376. static char *driver_version = "$Revision: 4.34 $";
  377. static struct tty_driver *serial_driver;
  378. /* number of characters left in xmit buffer before we ask for more */
  379. #define WAKEUP_CHARS 256
  380. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  381. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  382. /* PCMCIA prototypes */
  383. static int mgslpc_config(struct pcmcia_device *link);
  384. static void mgslpc_release(u_long arg);
  385. static void mgslpc_detach(struct pcmcia_device *p_dev);
  386. /*
  387. * 1st function defined in .text section. Calling this function in
  388. * init_module() followed by a breakpoint allows a remote debugger
  389. * (gdb) to get the .text address for the add-symbol-file command.
  390. * This allows remote debugging of dynamically loadable modules.
  391. */
  392. static void* mgslpc_get_text_ptr(void)
  393. {
  394. return mgslpc_get_text_ptr;
  395. }
  396. /**
  397. * line discipline callback wrappers
  398. *
  399. * The wrappers maintain line discipline references
  400. * while calling into the line discipline.
  401. *
  402. * ldisc_receive_buf - pass receive data to line discipline
  403. */
  404. static void ldisc_receive_buf(struct tty_struct *tty,
  405. const __u8 *data, char *flags, int count)
  406. {
  407. struct tty_ldisc *ld;
  408. if (!tty)
  409. return;
  410. ld = tty_ldisc_ref(tty);
  411. if (ld) {
  412. if (ld->ops->receive_buf)
  413. ld->ops->receive_buf(tty, data, flags, count);
  414. tty_ldisc_deref(ld);
  415. }
  416. }
  417. static const struct tty_port_operations mgslpc_port_ops = {
  418. .carrier_raised = carrier_raised,
  419. .dtr_rts = dtr_rts
  420. };
  421. static int mgslpc_probe(struct pcmcia_device *link)
  422. {
  423. MGSLPC_INFO *info;
  424. int ret;
  425. if (debug_level >= DEBUG_LEVEL_INFO)
  426. printk("mgslpc_attach\n");
  427. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  428. if (!info) {
  429. printk("Error can't allocate device instance data\n");
  430. return -ENOMEM;
  431. }
  432. info->magic = MGSLPC_MAGIC;
  433. tty_port_init(&info->port);
  434. info->port.ops = &mgslpc_port_ops;
  435. INIT_WORK(&info->task, bh_handler);
  436. info->max_frame_size = 4096;
  437. info->port.close_delay = 5*HZ/10;
  438. info->port.closing_wait = 30*HZ;
  439. init_waitqueue_head(&info->status_event_wait_q);
  440. init_waitqueue_head(&info->event_wait_q);
  441. spin_lock_init(&info->lock);
  442. spin_lock_init(&info->netlock);
  443. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  444. info->idle_mode = HDLC_TXIDLE_FLAGS;
  445. info->imra_value = 0xffff;
  446. info->imrb_value = 0xffff;
  447. info->pim_value = 0xff;
  448. info->p_dev = link;
  449. link->priv = info;
  450. /* Initialize the struct pcmcia_device structure */
  451. ret = mgslpc_config(link);
  452. if (ret != 0)
  453. goto failed;
  454. ret = mgslpc_add_device(info);
  455. if (ret != 0)
  456. goto failed_release;
  457. return 0;
  458. failed_release:
  459. mgslpc_release((u_long)link);
  460. failed:
  461. tty_port_destroy(&info->port);
  462. kfree(info);
  463. return ret;
  464. }
  465. /* Card has been inserted.
  466. */
  467. static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
  468. {
  469. return pcmcia_request_io(p_dev);
  470. }
  471. static int mgslpc_config(struct pcmcia_device *link)
  472. {
  473. MGSLPC_INFO *info = link->priv;
  474. int ret;
  475. if (debug_level >= DEBUG_LEVEL_INFO)
  476. printk("mgslpc_config(0x%p)\n", link);
  477. link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
  478. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  479. if (ret != 0)
  480. goto failed;
  481. link->config_index = 8;
  482. link->config_regs = PRESENT_OPTION;
  483. ret = pcmcia_request_irq(link, mgslpc_isr);
  484. if (ret)
  485. goto failed;
  486. ret = pcmcia_enable_device(link);
  487. if (ret)
  488. goto failed;
  489. info->io_base = link->resource[0]->start;
  490. info->irq_level = link->irq;
  491. return 0;
  492. failed:
  493. mgslpc_release((u_long)link);
  494. return -ENODEV;
  495. }
  496. /* Card has been removed.
  497. * Unregister device and release PCMCIA configuration.
  498. * If device is open, postpone until it is closed.
  499. */
  500. static void mgslpc_release(u_long arg)
  501. {
  502. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  503. if (debug_level >= DEBUG_LEVEL_INFO)
  504. printk("mgslpc_release(0x%p)\n", link);
  505. pcmcia_disable_device(link);
  506. }
  507. static void mgslpc_detach(struct pcmcia_device *link)
  508. {
  509. if (debug_level >= DEBUG_LEVEL_INFO)
  510. printk("mgslpc_detach(0x%p)\n", link);
  511. ((MGSLPC_INFO *)link->priv)->stop = 1;
  512. mgslpc_release((u_long)link);
  513. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  514. }
  515. static int mgslpc_suspend(struct pcmcia_device *link)
  516. {
  517. MGSLPC_INFO *info = link->priv;
  518. info->stop = 1;
  519. return 0;
  520. }
  521. static int mgslpc_resume(struct pcmcia_device *link)
  522. {
  523. MGSLPC_INFO *info = link->priv;
  524. info->stop = 0;
  525. return 0;
  526. }
  527. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  528. char *name, const char *routine)
  529. {
  530. #ifdef MGSLPC_PARANOIA_CHECK
  531. static const char *badmagic =
  532. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  533. static const char *badinfo =
  534. "Warning: null mgslpc_info for (%s) in %s\n";
  535. if (!info) {
  536. printk(badinfo, name, routine);
  537. return true;
  538. }
  539. if (info->magic != MGSLPC_MAGIC) {
  540. printk(badmagic, name, routine);
  541. return true;
  542. }
  543. #else
  544. if (!info)
  545. return true;
  546. #endif
  547. return false;
  548. }
  549. #define CMD_RXFIFO BIT7 // release current rx FIFO
  550. #define CMD_RXRESET BIT6 // receiver reset
  551. #define CMD_RXFIFO_READ BIT5
  552. #define CMD_START_TIMER BIT4
  553. #define CMD_TXFIFO BIT3 // release current tx FIFO
  554. #define CMD_TXEOM BIT1 // transmit end message
  555. #define CMD_TXRESET BIT0 // transmit reset
  556. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  557. {
  558. int i = 0;
  559. /* wait for command completion */
  560. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  561. udelay(1);
  562. if (i++ == 1000)
  563. return false;
  564. }
  565. return true;
  566. }
  567. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  568. {
  569. wait_command_complete(info, channel);
  570. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  571. }
  572. static void tx_pause(struct tty_struct *tty)
  573. {
  574. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  575. unsigned long flags;
  576. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  577. return;
  578. if (debug_level >= DEBUG_LEVEL_INFO)
  579. printk("tx_pause(%s)\n", info->device_name);
  580. spin_lock_irqsave(&info->lock, flags);
  581. if (info->tx_enabled)
  582. tx_stop(info);
  583. spin_unlock_irqrestore(&info->lock, flags);
  584. }
  585. static void tx_release(struct tty_struct *tty)
  586. {
  587. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  588. unsigned long flags;
  589. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  590. return;
  591. if (debug_level >= DEBUG_LEVEL_INFO)
  592. printk("tx_release(%s)\n", info->device_name);
  593. spin_lock_irqsave(&info->lock, flags);
  594. if (!info->tx_enabled)
  595. tx_start(info, tty);
  596. spin_unlock_irqrestore(&info->lock, flags);
  597. }
  598. /* Return next bottom half action to perform.
  599. * or 0 if nothing to do.
  600. */
  601. static int bh_action(MGSLPC_INFO *info)
  602. {
  603. unsigned long flags;
  604. int rc = 0;
  605. spin_lock_irqsave(&info->lock, flags);
  606. if (info->pending_bh & BH_RECEIVE) {
  607. info->pending_bh &= ~BH_RECEIVE;
  608. rc = BH_RECEIVE;
  609. } else if (info->pending_bh & BH_TRANSMIT) {
  610. info->pending_bh &= ~BH_TRANSMIT;
  611. rc = BH_TRANSMIT;
  612. } else if (info->pending_bh & BH_STATUS) {
  613. info->pending_bh &= ~BH_STATUS;
  614. rc = BH_STATUS;
  615. }
  616. if (!rc) {
  617. /* Mark BH routine as complete */
  618. info->bh_running = false;
  619. info->bh_requested = false;
  620. }
  621. spin_unlock_irqrestore(&info->lock, flags);
  622. return rc;
  623. }
  624. static void bh_handler(struct work_struct *work)
  625. {
  626. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  627. struct tty_struct *tty;
  628. int action;
  629. if (debug_level >= DEBUG_LEVEL_BH)
  630. printk("%s(%d):bh_handler(%s) entry\n",
  631. __FILE__,__LINE__,info->device_name);
  632. info->bh_running = true;
  633. tty = tty_port_tty_get(&info->port);
  634. while((action = bh_action(info)) != 0) {
  635. /* Process work item */
  636. if (debug_level >= DEBUG_LEVEL_BH)
  637. printk("%s(%d):bh_handler() work item action=%d\n",
  638. __FILE__,__LINE__,action);
  639. switch (action) {
  640. case BH_RECEIVE:
  641. while(rx_get_frame(info, tty));
  642. break;
  643. case BH_TRANSMIT:
  644. bh_transmit(info, tty);
  645. break;
  646. case BH_STATUS:
  647. bh_status(info);
  648. break;
  649. default:
  650. /* unknown work item ID */
  651. printk("Unknown work item ID=%08X!\n", action);
  652. break;
  653. }
  654. }
  655. tty_kref_put(tty);
  656. if (debug_level >= DEBUG_LEVEL_BH)
  657. printk("%s(%d):bh_handler(%s) exit\n",
  658. __FILE__,__LINE__,info->device_name);
  659. }
  660. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  661. {
  662. if (debug_level >= DEBUG_LEVEL_BH)
  663. printk("bh_transmit() entry on %s\n", info->device_name);
  664. if (tty)
  665. tty_wakeup(tty);
  666. }
  667. static void bh_status(MGSLPC_INFO *info)
  668. {
  669. info->ri_chkcount = 0;
  670. info->dsr_chkcount = 0;
  671. info->dcd_chkcount = 0;
  672. info->cts_chkcount = 0;
  673. }
  674. /* eom: non-zero = end of frame */
  675. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  676. {
  677. unsigned char data[2];
  678. unsigned char fifo_count, read_count, i;
  679. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  680. if (debug_level >= DEBUG_LEVEL_ISR)
  681. printk("%s(%d):rx_ready_hdlc(eom=%d)\n", __FILE__, __LINE__, eom);
  682. if (!info->rx_enabled)
  683. return;
  684. if (info->rx_frame_count >= info->rx_buf_count) {
  685. /* no more free buffers */
  686. issue_command(info, CHA, CMD_RXRESET);
  687. info->pending_bh |= BH_RECEIVE;
  688. info->rx_overflow = true;
  689. info->icount.buf_overrun++;
  690. return;
  691. }
  692. if (eom) {
  693. /* end of frame, get FIFO count from RBCL register */
  694. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  695. if (fifo_count == 0)
  696. fifo_count = 32;
  697. } else
  698. fifo_count = 32;
  699. do {
  700. if (fifo_count == 1) {
  701. read_count = 1;
  702. data[0] = read_reg(info, CHA + RXFIFO);
  703. } else {
  704. read_count = 2;
  705. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  706. }
  707. fifo_count -= read_count;
  708. if (!fifo_count && eom)
  709. buf->status = data[--read_count];
  710. for (i = 0; i < read_count; i++) {
  711. if (buf->count >= info->max_frame_size) {
  712. /* frame too large, reset receiver and reset current buffer */
  713. issue_command(info, CHA, CMD_RXRESET);
  714. buf->count = 0;
  715. return;
  716. }
  717. *(buf->data + buf->count) = data[i];
  718. buf->count++;
  719. }
  720. } while (fifo_count);
  721. if (eom) {
  722. info->pending_bh |= BH_RECEIVE;
  723. info->rx_frame_count++;
  724. info->rx_put++;
  725. if (info->rx_put >= info->rx_buf_count)
  726. info->rx_put = 0;
  727. }
  728. issue_command(info, CHA, CMD_RXFIFO);
  729. }
  730. static void rx_ready_async(MGSLPC_INFO *info, int tcd)
  731. {
  732. struct tty_port *port = &info->port;
  733. unsigned char data, status, flag;
  734. int fifo_count;
  735. int work = 0;
  736. struct mgsl_icount *icount = &info->icount;
  737. if (tcd) {
  738. /* early termination, get FIFO count from RBCL register */
  739. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  740. /* Zero fifo count could mean 0 or 32 bytes available.
  741. * If BIT5 of STAR is set then at least 1 byte is available.
  742. */
  743. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  744. fifo_count = 32;
  745. } else
  746. fifo_count = 32;
  747. tty_buffer_request_room(port, fifo_count);
  748. /* Flush received async data to receive data buffer. */
  749. while (fifo_count) {
  750. data = read_reg(info, CHA + RXFIFO);
  751. status = read_reg(info, CHA + RXFIFO);
  752. fifo_count -= 2;
  753. icount->rx++;
  754. flag = TTY_NORMAL;
  755. // if no frameing/crc error then save data
  756. // BIT7:parity error
  757. // BIT6:framing error
  758. if (status & (BIT7 + BIT6)) {
  759. if (status & BIT7)
  760. icount->parity++;
  761. else
  762. icount->frame++;
  763. /* discard char if tty control flags say so */
  764. if (status & info->ignore_status_mask)
  765. continue;
  766. status &= info->read_status_mask;
  767. if (status & BIT7)
  768. flag = TTY_PARITY;
  769. else if (status & BIT6)
  770. flag = TTY_FRAME;
  771. }
  772. work += tty_insert_flip_char(port, data, flag);
  773. }
  774. issue_command(info, CHA, CMD_RXFIFO);
  775. if (debug_level >= DEBUG_LEVEL_ISR) {
  776. printk("%s(%d):rx_ready_async",
  777. __FILE__,__LINE__);
  778. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  779. __FILE__,__LINE__,icount->rx,icount->brk,
  780. icount->parity,icount->frame,icount->overrun);
  781. }
  782. if (work)
  783. tty_flip_buffer_push(port);
  784. }
  785. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  786. {
  787. if (!info->tx_active)
  788. return;
  789. info->tx_active = false;
  790. info->tx_aborting = false;
  791. if (info->params.mode == MGSL_MODE_ASYNC)
  792. return;
  793. info->tx_count = info->tx_put = info->tx_get = 0;
  794. del_timer(&info->tx_timer);
  795. if (info->drop_rts_on_tx_done) {
  796. get_signals(info);
  797. if (info->serial_signals & SerialSignal_RTS) {
  798. info->serial_signals &= ~SerialSignal_RTS;
  799. set_signals(info);
  800. }
  801. info->drop_rts_on_tx_done = false;
  802. }
  803. #if SYNCLINK_GENERIC_HDLC
  804. if (info->netcount)
  805. hdlcdev_tx_done(info);
  806. else
  807. #endif
  808. {
  809. if (tty && (tty->stopped || tty->hw_stopped)) {
  810. tx_stop(info);
  811. return;
  812. }
  813. info->pending_bh |= BH_TRANSMIT;
  814. }
  815. }
  816. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  817. {
  818. unsigned char fifo_count = 32;
  819. int c;
  820. if (debug_level >= DEBUG_LEVEL_ISR)
  821. printk("%s(%d):tx_ready(%s)\n", __FILE__, __LINE__, info->device_name);
  822. if (info->params.mode == MGSL_MODE_HDLC) {
  823. if (!info->tx_active)
  824. return;
  825. } else {
  826. if (tty && (tty->stopped || tty->hw_stopped)) {
  827. tx_stop(info);
  828. return;
  829. }
  830. if (!info->tx_count)
  831. info->tx_active = false;
  832. }
  833. if (!info->tx_count)
  834. return;
  835. while (info->tx_count && fifo_count) {
  836. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  837. if (c == 1) {
  838. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  839. } else {
  840. write_reg16(info, CHA + TXFIFO,
  841. *((unsigned short*)(info->tx_buf + info->tx_get)));
  842. }
  843. info->tx_count -= c;
  844. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  845. fifo_count -= c;
  846. }
  847. if (info->params.mode == MGSL_MODE_ASYNC) {
  848. if (info->tx_count < WAKEUP_CHARS)
  849. info->pending_bh |= BH_TRANSMIT;
  850. issue_command(info, CHA, CMD_TXFIFO);
  851. } else {
  852. if (info->tx_count)
  853. issue_command(info, CHA, CMD_TXFIFO);
  854. else
  855. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  856. }
  857. }
  858. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  859. {
  860. get_signals(info);
  861. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  862. irq_disable(info, CHB, IRQ_CTS);
  863. info->icount.cts++;
  864. if (info->serial_signals & SerialSignal_CTS)
  865. info->input_signal_events.cts_up++;
  866. else
  867. info->input_signal_events.cts_down++;
  868. wake_up_interruptible(&info->status_event_wait_q);
  869. wake_up_interruptible(&info->event_wait_q);
  870. if (tty && tty_port_cts_enabled(&info->port)) {
  871. if (tty->hw_stopped) {
  872. if (info->serial_signals & SerialSignal_CTS) {
  873. if (debug_level >= DEBUG_LEVEL_ISR)
  874. printk("CTS tx start...");
  875. tty->hw_stopped = 0;
  876. tx_start(info, tty);
  877. info->pending_bh |= BH_TRANSMIT;
  878. return;
  879. }
  880. } else {
  881. if (!(info->serial_signals & SerialSignal_CTS)) {
  882. if (debug_level >= DEBUG_LEVEL_ISR)
  883. printk("CTS tx stop...");
  884. tty->hw_stopped = 1;
  885. tx_stop(info);
  886. }
  887. }
  888. }
  889. info->pending_bh |= BH_STATUS;
  890. }
  891. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  892. {
  893. get_signals(info);
  894. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  895. irq_disable(info, CHB, IRQ_DCD);
  896. info->icount.dcd++;
  897. if (info->serial_signals & SerialSignal_DCD) {
  898. info->input_signal_events.dcd_up++;
  899. }
  900. else
  901. info->input_signal_events.dcd_down++;
  902. #if SYNCLINK_GENERIC_HDLC
  903. if (info->netcount) {
  904. if (info->serial_signals & SerialSignal_DCD)
  905. netif_carrier_on(info->netdev);
  906. else
  907. netif_carrier_off(info->netdev);
  908. }
  909. #endif
  910. wake_up_interruptible(&info->status_event_wait_q);
  911. wake_up_interruptible(&info->event_wait_q);
  912. if (info->port.flags & ASYNC_CHECK_CD) {
  913. if (debug_level >= DEBUG_LEVEL_ISR)
  914. printk("%s CD now %s...", info->device_name,
  915. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  916. if (info->serial_signals & SerialSignal_DCD)
  917. wake_up_interruptible(&info->port.open_wait);
  918. else {
  919. if (debug_level >= DEBUG_LEVEL_ISR)
  920. printk("doing serial hangup...");
  921. if (tty)
  922. tty_hangup(tty);
  923. }
  924. }
  925. info->pending_bh |= BH_STATUS;
  926. }
  927. static void dsr_change(MGSLPC_INFO *info)
  928. {
  929. get_signals(info);
  930. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  931. port_irq_disable(info, PVR_DSR);
  932. info->icount.dsr++;
  933. if (info->serial_signals & SerialSignal_DSR)
  934. info->input_signal_events.dsr_up++;
  935. else
  936. info->input_signal_events.dsr_down++;
  937. wake_up_interruptible(&info->status_event_wait_q);
  938. wake_up_interruptible(&info->event_wait_q);
  939. info->pending_bh |= BH_STATUS;
  940. }
  941. static void ri_change(MGSLPC_INFO *info)
  942. {
  943. get_signals(info);
  944. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  945. port_irq_disable(info, PVR_RI);
  946. info->icount.rng++;
  947. if (info->serial_signals & SerialSignal_RI)
  948. info->input_signal_events.ri_up++;
  949. else
  950. info->input_signal_events.ri_down++;
  951. wake_up_interruptible(&info->status_event_wait_q);
  952. wake_up_interruptible(&info->event_wait_q);
  953. info->pending_bh |= BH_STATUS;
  954. }
  955. /* Interrupt service routine entry point.
  956. *
  957. * Arguments:
  958. *
  959. * irq interrupt number that caused interrupt
  960. * dev_id device ID supplied during interrupt registration
  961. */
  962. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  963. {
  964. MGSLPC_INFO *info = dev_id;
  965. struct tty_struct *tty;
  966. unsigned short isr;
  967. unsigned char gis, pis;
  968. int count=0;
  969. if (debug_level >= DEBUG_LEVEL_ISR)
  970. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  971. if (!(info->p_dev->_locked))
  972. return IRQ_HANDLED;
  973. tty = tty_port_tty_get(&info->port);
  974. spin_lock(&info->lock);
  975. while ((gis = read_reg(info, CHA + GIS))) {
  976. if (debug_level >= DEBUG_LEVEL_ISR)
  977. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  978. if ((gis & 0x70) || count > 1000) {
  979. printk("synclink_cs:hardware failed or ejected\n");
  980. break;
  981. }
  982. count++;
  983. if (gis & (BIT1 | BIT0)) {
  984. isr = read_reg16(info, CHB + ISR);
  985. if (isr & IRQ_DCD)
  986. dcd_change(info, tty);
  987. if (isr & IRQ_CTS)
  988. cts_change(info, tty);
  989. }
  990. if (gis & (BIT3 | BIT2))
  991. {
  992. isr = read_reg16(info, CHA + ISR);
  993. if (isr & IRQ_TIMER) {
  994. info->irq_occurred = true;
  995. irq_disable(info, CHA, IRQ_TIMER);
  996. }
  997. /* receive IRQs */
  998. if (isr & IRQ_EXITHUNT) {
  999. info->icount.exithunt++;
  1000. wake_up_interruptible(&info->event_wait_q);
  1001. }
  1002. if (isr & IRQ_BREAK_ON) {
  1003. info->icount.brk++;
  1004. if (info->port.flags & ASYNC_SAK)
  1005. do_SAK(tty);
  1006. }
  1007. if (isr & IRQ_RXTIME) {
  1008. issue_command(info, CHA, CMD_RXFIFO_READ);
  1009. }
  1010. if (isr & (IRQ_RXEOM | IRQ_RXFIFO)) {
  1011. if (info->params.mode == MGSL_MODE_HDLC)
  1012. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1013. else
  1014. rx_ready_async(info, isr & IRQ_RXEOM);
  1015. }
  1016. /* transmit IRQs */
  1017. if (isr & IRQ_UNDERRUN) {
  1018. if (info->tx_aborting)
  1019. info->icount.txabort++;
  1020. else
  1021. info->icount.txunder++;
  1022. tx_done(info, tty);
  1023. }
  1024. else if (isr & IRQ_ALLSENT) {
  1025. info->icount.txok++;
  1026. tx_done(info, tty);
  1027. }
  1028. else if (isr & IRQ_TXFIFO)
  1029. tx_ready(info, tty);
  1030. }
  1031. if (gis & BIT7) {
  1032. pis = read_reg(info, CHA + PIS);
  1033. if (pis & BIT1)
  1034. dsr_change(info);
  1035. if (pis & BIT2)
  1036. ri_change(info);
  1037. }
  1038. }
  1039. /* Request bottom half processing if there's something
  1040. * for it to do and the bh is not already running
  1041. */
  1042. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1043. if (debug_level >= DEBUG_LEVEL_ISR)
  1044. printk("%s(%d):%s queueing bh task.\n",
  1045. __FILE__,__LINE__,info->device_name);
  1046. schedule_work(&info->task);
  1047. info->bh_requested = true;
  1048. }
  1049. spin_unlock(&info->lock);
  1050. tty_kref_put(tty);
  1051. if (debug_level >= DEBUG_LEVEL_ISR)
  1052. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1053. __FILE__, __LINE__, info->irq_level);
  1054. return IRQ_HANDLED;
  1055. }
  1056. /* Initialize and start device.
  1057. */
  1058. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1059. {
  1060. int retval = 0;
  1061. if (debug_level >= DEBUG_LEVEL_INFO)
  1062. printk("%s(%d):startup(%s)\n", __FILE__, __LINE__, info->device_name);
  1063. if (info->port.flags & ASYNC_INITIALIZED)
  1064. return 0;
  1065. if (!info->tx_buf) {
  1066. /* allocate a page of memory for a transmit buffer */
  1067. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1068. if (!info->tx_buf) {
  1069. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1070. __FILE__, __LINE__, info->device_name);
  1071. return -ENOMEM;
  1072. }
  1073. }
  1074. info->pending_bh = 0;
  1075. memset(&info->icount, 0, sizeof(info->icount));
  1076. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1077. /* Allocate and claim adapter resources */
  1078. retval = claim_resources(info);
  1079. /* perform existence check and diagnostics */
  1080. if (!retval)
  1081. retval = adapter_test(info);
  1082. if (retval) {
  1083. if (capable(CAP_SYS_ADMIN) && tty)
  1084. set_bit(TTY_IO_ERROR, &tty->flags);
  1085. release_resources(info);
  1086. return retval;
  1087. }
  1088. /* program hardware for current parameters */
  1089. mgslpc_change_params(info, tty);
  1090. if (tty)
  1091. clear_bit(TTY_IO_ERROR, &tty->flags);
  1092. info->port.flags |= ASYNC_INITIALIZED;
  1093. return 0;
  1094. }
  1095. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1096. */
  1097. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1098. {
  1099. unsigned long flags;
  1100. if (!(info->port.flags & ASYNC_INITIALIZED))
  1101. return;
  1102. if (debug_level >= DEBUG_LEVEL_INFO)
  1103. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1104. __FILE__, __LINE__, info->device_name);
  1105. /* clear status wait queue because status changes */
  1106. /* can't happen after shutting down the hardware */
  1107. wake_up_interruptible(&info->status_event_wait_q);
  1108. wake_up_interruptible(&info->event_wait_q);
  1109. del_timer_sync(&info->tx_timer);
  1110. if (info->tx_buf) {
  1111. free_page((unsigned long) info->tx_buf);
  1112. info->tx_buf = NULL;
  1113. }
  1114. spin_lock_irqsave(&info->lock, flags);
  1115. rx_stop(info);
  1116. tx_stop(info);
  1117. /* TODO:disable interrupts instead of reset to preserve signal states */
  1118. reset_device(info);
  1119. if (!tty || tty->termios.c_cflag & HUPCL) {
  1120. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1121. set_signals(info);
  1122. }
  1123. spin_unlock_irqrestore(&info->lock, flags);
  1124. release_resources(info);
  1125. if (tty)
  1126. set_bit(TTY_IO_ERROR, &tty->flags);
  1127. info->port.flags &= ~ASYNC_INITIALIZED;
  1128. }
  1129. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1130. {
  1131. unsigned long flags;
  1132. spin_lock_irqsave(&info->lock, flags);
  1133. rx_stop(info);
  1134. tx_stop(info);
  1135. info->tx_count = info->tx_put = info->tx_get = 0;
  1136. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1137. hdlc_mode(info);
  1138. else
  1139. async_mode(info);
  1140. set_signals(info);
  1141. info->dcd_chkcount = 0;
  1142. info->cts_chkcount = 0;
  1143. info->ri_chkcount = 0;
  1144. info->dsr_chkcount = 0;
  1145. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1146. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1147. get_signals(info);
  1148. if (info->netcount || (tty && (tty->termios.c_cflag & CREAD)))
  1149. rx_start(info);
  1150. spin_unlock_irqrestore(&info->lock, flags);
  1151. }
  1152. /* Reconfigure adapter based on new parameters
  1153. */
  1154. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1155. {
  1156. unsigned cflag;
  1157. int bits_per_char;
  1158. if (!tty)
  1159. return;
  1160. if (debug_level >= DEBUG_LEVEL_INFO)
  1161. printk("%s(%d):mgslpc_change_params(%s)\n",
  1162. __FILE__, __LINE__, info->device_name);
  1163. cflag = tty->termios.c_cflag;
  1164. /* if B0 rate (hangup) specified then negate RTS and DTR */
  1165. /* otherwise assert RTS and DTR */
  1166. if (cflag & CBAUD)
  1167. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  1168. else
  1169. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1170. /* byte size and parity */
  1171. switch (cflag & CSIZE) {
  1172. case CS5: info->params.data_bits = 5; break;
  1173. case CS6: info->params.data_bits = 6; break;
  1174. case CS7: info->params.data_bits = 7; break;
  1175. case CS8: info->params.data_bits = 8; break;
  1176. default: info->params.data_bits = 7; break;
  1177. }
  1178. if (cflag & CSTOPB)
  1179. info->params.stop_bits = 2;
  1180. else
  1181. info->params.stop_bits = 1;
  1182. info->params.parity = ASYNC_PARITY_NONE;
  1183. if (cflag & PARENB) {
  1184. if (cflag & PARODD)
  1185. info->params.parity = ASYNC_PARITY_ODD;
  1186. else
  1187. info->params.parity = ASYNC_PARITY_EVEN;
  1188. #ifdef CMSPAR
  1189. if (cflag & CMSPAR)
  1190. info->params.parity = ASYNC_PARITY_SPACE;
  1191. #endif
  1192. }
  1193. /* calculate number of jiffies to transmit a full
  1194. * FIFO (32 bytes) at specified data rate
  1195. */
  1196. bits_per_char = info->params.data_bits +
  1197. info->params.stop_bits + 1;
  1198. /* if port data rate is set to 460800 or less then
  1199. * allow tty settings to override, otherwise keep the
  1200. * current data rate.
  1201. */
  1202. if (info->params.data_rate <= 460800) {
  1203. info->params.data_rate = tty_get_baud_rate(tty);
  1204. }
  1205. if (info->params.data_rate) {
  1206. info->timeout = (32*HZ*bits_per_char) /
  1207. info->params.data_rate;
  1208. }
  1209. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1210. if (cflag & CRTSCTS)
  1211. info->port.flags |= ASYNC_CTS_FLOW;
  1212. else
  1213. info->port.flags &= ~ASYNC_CTS_FLOW;
  1214. if (cflag & CLOCAL)
  1215. info->port.flags &= ~ASYNC_CHECK_CD;
  1216. else
  1217. info->port.flags |= ASYNC_CHECK_CD;
  1218. /* process tty input control flags */
  1219. info->read_status_mask = 0;
  1220. if (I_INPCK(tty))
  1221. info->read_status_mask |= BIT7 | BIT6;
  1222. if (I_IGNPAR(tty))
  1223. info->ignore_status_mask |= BIT7 | BIT6;
  1224. mgslpc_program_hw(info, tty);
  1225. }
  1226. /* Add a character to the transmit buffer
  1227. */
  1228. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1229. {
  1230. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1231. unsigned long flags;
  1232. if (debug_level >= DEBUG_LEVEL_INFO) {
  1233. printk("%s(%d):mgslpc_put_char(%d) on %s\n",
  1234. __FILE__, __LINE__, ch, info->device_name);
  1235. }
  1236. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1237. return 0;
  1238. if (!info->tx_buf)
  1239. return 0;
  1240. spin_lock_irqsave(&info->lock, flags);
  1241. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1242. if (info->tx_count < TXBUFSIZE - 1) {
  1243. info->tx_buf[info->tx_put++] = ch;
  1244. info->tx_put &= TXBUFSIZE-1;
  1245. info->tx_count++;
  1246. }
  1247. }
  1248. spin_unlock_irqrestore(&info->lock, flags);
  1249. return 1;
  1250. }
  1251. /* Enable transmitter so remaining characters in the
  1252. * transmit buffer are sent.
  1253. */
  1254. static void mgslpc_flush_chars(struct tty_struct *tty)
  1255. {
  1256. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1257. unsigned long flags;
  1258. if (debug_level >= DEBUG_LEVEL_INFO)
  1259. printk("%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1260. __FILE__, __LINE__, info->device_name, info->tx_count);
  1261. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1262. return;
  1263. if (info->tx_count <= 0 || tty->stopped ||
  1264. tty->hw_stopped || !info->tx_buf)
  1265. return;
  1266. if (debug_level >= DEBUG_LEVEL_INFO)
  1267. printk("%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1268. __FILE__, __LINE__, info->device_name);
  1269. spin_lock_irqsave(&info->lock, flags);
  1270. if (!info->tx_active)
  1271. tx_start(info, tty);
  1272. spin_unlock_irqrestore(&info->lock, flags);
  1273. }
  1274. /* Send a block of data
  1275. *
  1276. * Arguments:
  1277. *
  1278. * tty pointer to tty information structure
  1279. * buf pointer to buffer containing send data
  1280. * count size of send data in bytes
  1281. *
  1282. * Returns: number of characters written
  1283. */
  1284. static int mgslpc_write(struct tty_struct * tty,
  1285. const unsigned char *buf, int count)
  1286. {
  1287. int c, ret = 0;
  1288. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1289. unsigned long flags;
  1290. if (debug_level >= DEBUG_LEVEL_INFO)
  1291. printk("%s(%d):mgslpc_write(%s) count=%d\n",
  1292. __FILE__, __LINE__, info->device_name, count);
  1293. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1294. !info->tx_buf)
  1295. goto cleanup;
  1296. if (info->params.mode == MGSL_MODE_HDLC) {
  1297. if (count > TXBUFSIZE) {
  1298. ret = -EIO;
  1299. goto cleanup;
  1300. }
  1301. if (info->tx_active)
  1302. goto cleanup;
  1303. else if (info->tx_count)
  1304. goto start;
  1305. }
  1306. for (;;) {
  1307. c = min(count,
  1308. min(TXBUFSIZE - info->tx_count - 1,
  1309. TXBUFSIZE - info->tx_put));
  1310. if (c <= 0)
  1311. break;
  1312. memcpy(info->tx_buf + info->tx_put, buf, c);
  1313. spin_lock_irqsave(&info->lock, flags);
  1314. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1315. info->tx_count += c;
  1316. spin_unlock_irqrestore(&info->lock, flags);
  1317. buf += c;
  1318. count -= c;
  1319. ret += c;
  1320. }
  1321. start:
  1322. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1323. spin_lock_irqsave(&info->lock, flags);
  1324. if (!info->tx_active)
  1325. tx_start(info, tty);
  1326. spin_unlock_irqrestore(&info->lock, flags);
  1327. }
  1328. cleanup:
  1329. if (debug_level >= DEBUG_LEVEL_INFO)
  1330. printk("%s(%d):mgslpc_write(%s) returning=%d\n",
  1331. __FILE__, __LINE__, info->device_name, ret);
  1332. return ret;
  1333. }
  1334. /* Return the count of free bytes in transmit buffer
  1335. */
  1336. static int mgslpc_write_room(struct tty_struct *tty)
  1337. {
  1338. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1339. int ret;
  1340. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1341. return 0;
  1342. if (info->params.mode == MGSL_MODE_HDLC) {
  1343. /* HDLC (frame oriented) mode */
  1344. if (info->tx_active)
  1345. return 0;
  1346. else
  1347. return HDLC_MAX_FRAME_SIZE;
  1348. } else {
  1349. ret = TXBUFSIZE - info->tx_count - 1;
  1350. if (ret < 0)
  1351. ret = 0;
  1352. }
  1353. if (debug_level >= DEBUG_LEVEL_INFO)
  1354. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1355. __FILE__, __LINE__, info->device_name, ret);
  1356. return ret;
  1357. }
  1358. /* Return the count of bytes in transmit buffer
  1359. */
  1360. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1361. {
  1362. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1363. int rc;
  1364. if (debug_level >= DEBUG_LEVEL_INFO)
  1365. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1366. __FILE__, __LINE__, info->device_name);
  1367. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1368. return 0;
  1369. if (info->params.mode == MGSL_MODE_HDLC)
  1370. rc = info->tx_active ? info->max_frame_size : 0;
  1371. else
  1372. rc = info->tx_count;
  1373. if (debug_level >= DEBUG_LEVEL_INFO)
  1374. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1375. __FILE__, __LINE__, info->device_name, rc);
  1376. return rc;
  1377. }
  1378. /* Discard all data in the send buffer
  1379. */
  1380. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1381. {
  1382. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1383. unsigned long flags;
  1384. if (debug_level >= DEBUG_LEVEL_INFO)
  1385. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1386. __FILE__, __LINE__, info->device_name);
  1387. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1388. return;
  1389. spin_lock_irqsave(&info->lock, flags);
  1390. info->tx_count = info->tx_put = info->tx_get = 0;
  1391. del_timer(&info->tx_timer);
  1392. spin_unlock_irqrestore(&info->lock, flags);
  1393. wake_up_interruptible(&tty->write_wait);
  1394. tty_wakeup(tty);
  1395. }
  1396. /* Send a high-priority XON/XOFF character
  1397. */
  1398. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1399. {
  1400. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1401. unsigned long flags;
  1402. if (debug_level >= DEBUG_LEVEL_INFO)
  1403. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1404. __FILE__, __LINE__, info->device_name, ch);
  1405. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1406. return;
  1407. info->x_char = ch;
  1408. if (ch) {
  1409. spin_lock_irqsave(&info->lock, flags);
  1410. if (!info->tx_enabled)
  1411. tx_start(info, tty);
  1412. spin_unlock_irqrestore(&info->lock, flags);
  1413. }
  1414. }
  1415. /* Signal remote device to throttle send data (our receive data)
  1416. */
  1417. static void mgslpc_throttle(struct tty_struct * tty)
  1418. {
  1419. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1420. unsigned long flags;
  1421. if (debug_level >= DEBUG_LEVEL_INFO)
  1422. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1423. __FILE__, __LINE__, info->device_name);
  1424. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1425. return;
  1426. if (I_IXOFF(tty))
  1427. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1428. if (tty->termios.c_cflag & CRTSCTS) {
  1429. spin_lock_irqsave(&info->lock, flags);
  1430. info->serial_signals &= ~SerialSignal_RTS;
  1431. set_signals(info);
  1432. spin_unlock_irqrestore(&info->lock, flags);
  1433. }
  1434. }
  1435. /* Signal remote device to stop throttling send data (our receive data)
  1436. */
  1437. static void mgslpc_unthrottle(struct tty_struct * tty)
  1438. {
  1439. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1440. unsigned long flags;
  1441. if (debug_level >= DEBUG_LEVEL_INFO)
  1442. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1443. __FILE__, __LINE__, info->device_name);
  1444. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1445. return;
  1446. if (I_IXOFF(tty)) {
  1447. if (info->x_char)
  1448. info->x_char = 0;
  1449. else
  1450. mgslpc_send_xchar(tty, START_CHAR(tty));
  1451. }
  1452. if (tty->termios.c_cflag & CRTSCTS) {
  1453. spin_lock_irqsave(&info->lock, flags);
  1454. info->serial_signals |= SerialSignal_RTS;
  1455. set_signals(info);
  1456. spin_unlock_irqrestore(&info->lock, flags);
  1457. }
  1458. }
  1459. /* get the current serial statistics
  1460. */
  1461. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1462. {
  1463. int err;
  1464. if (debug_level >= DEBUG_LEVEL_INFO)
  1465. printk("get_params(%s)\n", info->device_name);
  1466. if (!user_icount) {
  1467. memset(&info->icount, 0, sizeof(info->icount));
  1468. } else {
  1469. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1470. if (err)
  1471. return -EFAULT;
  1472. }
  1473. return 0;
  1474. }
  1475. /* get the current serial parameters
  1476. */
  1477. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1478. {
  1479. int err;
  1480. if (debug_level >= DEBUG_LEVEL_INFO)
  1481. printk("get_params(%s)\n", info->device_name);
  1482. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1483. if (err)
  1484. return -EFAULT;
  1485. return 0;
  1486. }
  1487. /* set the serial parameters
  1488. *
  1489. * Arguments:
  1490. *
  1491. * info pointer to device instance data
  1492. * new_params user buffer containing new serial params
  1493. *
  1494. * Returns: 0 if success, otherwise error code
  1495. */
  1496. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1497. {
  1498. unsigned long flags;
  1499. MGSL_PARAMS tmp_params;
  1500. int err;
  1501. if (debug_level >= DEBUG_LEVEL_INFO)
  1502. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1503. info->device_name);
  1504. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1505. if (err) {
  1506. if (debug_level >= DEBUG_LEVEL_INFO)
  1507. printk("%s(%d):set_params(%s) user buffer copy failed\n",
  1508. __FILE__, __LINE__, info->device_name);
  1509. return -EFAULT;
  1510. }
  1511. spin_lock_irqsave(&info->lock, flags);
  1512. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1513. spin_unlock_irqrestore(&info->lock, flags);
  1514. mgslpc_change_params(info, tty);
  1515. return 0;
  1516. }
  1517. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1518. {
  1519. int err;
  1520. if (debug_level >= DEBUG_LEVEL_INFO)
  1521. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1522. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1523. if (err)
  1524. return -EFAULT;
  1525. return 0;
  1526. }
  1527. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1528. {
  1529. unsigned long flags;
  1530. if (debug_level >= DEBUG_LEVEL_INFO)
  1531. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1532. spin_lock_irqsave(&info->lock, flags);
  1533. info->idle_mode = idle_mode;
  1534. tx_set_idle(info);
  1535. spin_unlock_irqrestore(&info->lock, flags);
  1536. return 0;
  1537. }
  1538. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1539. {
  1540. int err;
  1541. if (debug_level >= DEBUG_LEVEL_INFO)
  1542. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1543. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1544. if (err)
  1545. return -EFAULT;
  1546. return 0;
  1547. }
  1548. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1549. {
  1550. unsigned long flags;
  1551. unsigned char val;
  1552. if (debug_level >= DEBUG_LEVEL_INFO)
  1553. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1554. spin_lock_irqsave(&info->lock, flags);
  1555. info->if_mode = if_mode;
  1556. val = read_reg(info, PVR) & 0x0f;
  1557. switch (info->if_mode)
  1558. {
  1559. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1560. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1561. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1562. }
  1563. write_reg(info, PVR, val);
  1564. spin_unlock_irqrestore(&info->lock, flags);
  1565. return 0;
  1566. }
  1567. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1568. {
  1569. unsigned long flags;
  1570. if (debug_level >= DEBUG_LEVEL_INFO)
  1571. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1572. spin_lock_irqsave(&info->lock, flags);
  1573. if (enable) {
  1574. if (!info->tx_enabled)
  1575. tx_start(info, tty);
  1576. } else {
  1577. if (info->tx_enabled)
  1578. tx_stop(info);
  1579. }
  1580. spin_unlock_irqrestore(&info->lock, flags);
  1581. return 0;
  1582. }
  1583. static int tx_abort(MGSLPC_INFO * info)
  1584. {
  1585. unsigned long flags;
  1586. if (debug_level >= DEBUG_LEVEL_INFO)
  1587. printk("tx_abort(%s)\n", info->device_name);
  1588. spin_lock_irqsave(&info->lock, flags);
  1589. if (info->tx_active && info->tx_count &&
  1590. info->params.mode == MGSL_MODE_HDLC) {
  1591. /* clear data count so FIFO is not filled on next IRQ.
  1592. * This results in underrun and abort transmission.
  1593. */
  1594. info->tx_count = info->tx_put = info->tx_get = 0;
  1595. info->tx_aborting = true;
  1596. }
  1597. spin_unlock_irqrestore(&info->lock, flags);
  1598. return 0;
  1599. }
  1600. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1601. {
  1602. unsigned long flags;
  1603. if (debug_level >= DEBUG_LEVEL_INFO)
  1604. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1605. spin_lock_irqsave(&info->lock, flags);
  1606. if (enable) {
  1607. if (!info->rx_enabled)
  1608. rx_start(info);
  1609. } else {
  1610. if (info->rx_enabled)
  1611. rx_stop(info);
  1612. }
  1613. spin_unlock_irqrestore(&info->lock, flags);
  1614. return 0;
  1615. }
  1616. /* wait for specified event to occur
  1617. *
  1618. * Arguments: info pointer to device instance data
  1619. * mask pointer to bitmask of events to wait for
  1620. * Return Value: 0 if successful and bit mask updated with
  1621. * of events triggerred,
  1622. * otherwise error code
  1623. */
  1624. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1625. {
  1626. unsigned long flags;
  1627. int s;
  1628. int rc=0;
  1629. struct mgsl_icount cprev, cnow;
  1630. int events;
  1631. int mask;
  1632. struct _input_signal_events oldsigs, newsigs;
  1633. DECLARE_WAITQUEUE(wait, current);
  1634. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1635. if (rc)
  1636. return -EFAULT;
  1637. if (debug_level >= DEBUG_LEVEL_INFO)
  1638. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1639. spin_lock_irqsave(&info->lock, flags);
  1640. /* return immediately if state matches requested events */
  1641. get_signals(info);
  1642. s = info->serial_signals;
  1643. events = mask &
  1644. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1645. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1646. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1647. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1648. if (events) {
  1649. spin_unlock_irqrestore(&info->lock, flags);
  1650. goto exit;
  1651. }
  1652. /* save current irq counts */
  1653. cprev = info->icount;
  1654. oldsigs = info->input_signal_events;
  1655. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1656. (mask & MgslEvent_ExitHuntMode))
  1657. irq_enable(info, CHA, IRQ_EXITHUNT);
  1658. set_current_state(TASK_INTERRUPTIBLE);
  1659. add_wait_queue(&info->event_wait_q, &wait);
  1660. spin_unlock_irqrestore(&info->lock, flags);
  1661. for(;;) {
  1662. schedule();
  1663. if (signal_pending(current)) {
  1664. rc = -ERESTARTSYS;
  1665. break;
  1666. }
  1667. /* get current irq counts */
  1668. spin_lock_irqsave(&info->lock, flags);
  1669. cnow = info->icount;
  1670. newsigs = info->input_signal_events;
  1671. set_current_state(TASK_INTERRUPTIBLE);
  1672. spin_unlock_irqrestore(&info->lock, flags);
  1673. /* if no change, wait aborted for some reason */
  1674. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1675. newsigs.dsr_down == oldsigs.dsr_down &&
  1676. newsigs.dcd_up == oldsigs.dcd_up &&
  1677. newsigs.dcd_down == oldsigs.dcd_down &&
  1678. newsigs.cts_up == oldsigs.cts_up &&
  1679. newsigs.cts_down == oldsigs.cts_down &&
  1680. newsigs.ri_up == oldsigs.ri_up &&
  1681. newsigs.ri_down == oldsigs.ri_down &&
  1682. cnow.exithunt == cprev.exithunt &&
  1683. cnow.rxidle == cprev.rxidle) {
  1684. rc = -EIO;
  1685. break;
  1686. }
  1687. events = mask &
  1688. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1689. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1690. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1691. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1692. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1693. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1694. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1695. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1696. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1697. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1698. if (events)
  1699. break;
  1700. cprev = cnow;
  1701. oldsigs = newsigs;
  1702. }
  1703. remove_wait_queue(&info->event_wait_q, &wait);
  1704. set_current_state(TASK_RUNNING);
  1705. if (mask & MgslEvent_ExitHuntMode) {
  1706. spin_lock_irqsave(&info->lock, flags);
  1707. if (!waitqueue_active(&info->event_wait_q))
  1708. irq_disable(info, CHA, IRQ_EXITHUNT);
  1709. spin_unlock_irqrestore(&info->lock, flags);
  1710. }
  1711. exit:
  1712. if (rc == 0)
  1713. PUT_USER(rc, events, mask_ptr);
  1714. return rc;
  1715. }
  1716. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1717. {
  1718. unsigned long flags;
  1719. int rc;
  1720. struct mgsl_icount cprev, cnow;
  1721. DECLARE_WAITQUEUE(wait, current);
  1722. /* save current irq counts */
  1723. spin_lock_irqsave(&info->lock, flags);
  1724. cprev = info->icount;
  1725. add_wait_queue(&info->status_event_wait_q, &wait);
  1726. set_current_state(TASK_INTERRUPTIBLE);
  1727. spin_unlock_irqrestore(&info->lock, flags);
  1728. for(;;) {
  1729. schedule();
  1730. if (signal_pending(current)) {
  1731. rc = -ERESTARTSYS;
  1732. break;
  1733. }
  1734. /* get new irq counts */
  1735. spin_lock_irqsave(&info->lock, flags);
  1736. cnow = info->icount;
  1737. set_current_state(TASK_INTERRUPTIBLE);
  1738. spin_unlock_irqrestore(&info->lock, flags);
  1739. /* if no change, wait aborted for some reason */
  1740. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1741. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1742. rc = -EIO;
  1743. break;
  1744. }
  1745. /* check for change in caller specified modem input */
  1746. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1747. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1748. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1749. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1750. rc = 0;
  1751. break;
  1752. }
  1753. cprev = cnow;
  1754. }
  1755. remove_wait_queue(&info->status_event_wait_q, &wait);
  1756. set_current_state(TASK_RUNNING);
  1757. return rc;
  1758. }
  1759. /* return the state of the serial control and status signals
  1760. */
  1761. static int tiocmget(struct tty_struct *tty)
  1762. {
  1763. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1764. unsigned int result;
  1765. unsigned long flags;
  1766. spin_lock_irqsave(&info->lock, flags);
  1767. get_signals(info);
  1768. spin_unlock_irqrestore(&info->lock, flags);
  1769. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1770. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1771. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1772. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1773. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1774. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1775. if (debug_level >= DEBUG_LEVEL_INFO)
  1776. printk("%s(%d):%s tiocmget() value=%08X\n",
  1777. __FILE__, __LINE__, info->device_name, result);
  1778. return result;
  1779. }
  1780. /* set modem control signals (DTR/RTS)
  1781. */
  1782. static int tiocmset(struct tty_struct *tty,
  1783. unsigned int set, unsigned int clear)
  1784. {
  1785. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1786. unsigned long flags;
  1787. if (debug_level >= DEBUG_LEVEL_INFO)
  1788. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1789. __FILE__, __LINE__, info->device_name, set, clear);
  1790. if (set & TIOCM_RTS)
  1791. info->serial_signals |= SerialSignal_RTS;
  1792. if (set & TIOCM_DTR)
  1793. info->serial_signals |= SerialSignal_DTR;
  1794. if (clear & TIOCM_RTS)
  1795. info->serial_signals &= ~SerialSignal_RTS;
  1796. if (clear & TIOCM_DTR)
  1797. info->serial_signals &= ~SerialSignal_DTR;
  1798. spin_lock_irqsave(&info->lock, flags);
  1799. set_signals(info);
  1800. spin_unlock_irqrestore(&info->lock, flags);
  1801. return 0;
  1802. }
  1803. /* Set or clear transmit break condition
  1804. *
  1805. * Arguments: tty pointer to tty instance data
  1806. * break_state -1=set break condition, 0=clear
  1807. */
  1808. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1809. {
  1810. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1811. unsigned long flags;
  1812. if (debug_level >= DEBUG_LEVEL_INFO)
  1813. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1814. __FILE__, __LINE__, info->device_name, break_state);
  1815. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1816. return -EINVAL;
  1817. spin_lock_irqsave(&info->lock, flags);
  1818. if (break_state == -1)
  1819. set_reg_bits(info, CHA+DAFO, BIT6);
  1820. else
  1821. clear_reg_bits(info, CHA+DAFO, BIT6);
  1822. spin_unlock_irqrestore(&info->lock, flags);
  1823. return 0;
  1824. }
  1825. static int mgslpc_get_icount(struct tty_struct *tty,
  1826. struct serial_icounter_struct *icount)
  1827. {
  1828. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1829. struct mgsl_icount cnow; /* kernel counter temps */
  1830. unsigned long flags;
  1831. spin_lock_irqsave(&info->lock, flags);
  1832. cnow = info->icount;
  1833. spin_unlock_irqrestore(&info->lock, flags);
  1834. icount->cts = cnow.cts;
  1835. icount->dsr = cnow.dsr;
  1836. icount->rng = cnow.rng;
  1837. icount->dcd = cnow.dcd;
  1838. icount->rx = cnow.rx;
  1839. icount->tx = cnow.tx;
  1840. icount->frame = cnow.frame;
  1841. icount->overrun = cnow.overrun;
  1842. icount->parity = cnow.parity;
  1843. icount->brk = cnow.brk;
  1844. icount->buf_overrun = cnow.buf_overrun;
  1845. return 0;
  1846. }
  1847. /* Service an IOCTL request
  1848. *
  1849. * Arguments:
  1850. *
  1851. * tty pointer to tty instance data
  1852. * cmd IOCTL command code
  1853. * arg command argument/context
  1854. *
  1855. * Return Value: 0 if success, otherwise error code
  1856. */
  1857. static int mgslpc_ioctl(struct tty_struct *tty,
  1858. unsigned int cmd, unsigned long arg)
  1859. {
  1860. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1861. void __user *argp = (void __user *)arg;
  1862. if (debug_level >= DEBUG_LEVEL_INFO)
  1863. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__, __LINE__,
  1864. info->device_name, cmd);
  1865. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1866. return -ENODEV;
  1867. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1868. (cmd != TIOCMIWAIT)) {
  1869. if (tty->flags & (1 << TTY_IO_ERROR))
  1870. return -EIO;
  1871. }
  1872. switch (cmd) {
  1873. case MGSL_IOCGPARAMS:
  1874. return get_params(info, argp);
  1875. case MGSL_IOCSPARAMS:
  1876. return set_params(info, argp, tty);
  1877. case MGSL_IOCGTXIDLE:
  1878. return get_txidle(info, argp);
  1879. case MGSL_IOCSTXIDLE:
  1880. return set_txidle(info, (int)arg);
  1881. case MGSL_IOCGIF:
  1882. return get_interface(info, argp);
  1883. case MGSL_IOCSIF:
  1884. return set_interface(info,(int)arg);
  1885. case MGSL_IOCTXENABLE:
  1886. return set_txenable(info,(int)arg, tty);
  1887. case MGSL_IOCRXENABLE:
  1888. return set_rxenable(info,(int)arg);
  1889. case MGSL_IOCTXABORT:
  1890. return tx_abort(info);
  1891. case MGSL_IOCGSTATS:
  1892. return get_stats(info, argp);
  1893. case MGSL_IOCWAITEVENT:
  1894. return wait_events(info, argp);
  1895. case TIOCMIWAIT:
  1896. return modem_input_wait(info,(int)arg);
  1897. default:
  1898. return -ENOIOCTLCMD;
  1899. }
  1900. return 0;
  1901. }
  1902. /* Set new termios settings
  1903. *
  1904. * Arguments:
  1905. *
  1906. * tty pointer to tty structure
  1907. * termios pointer to buffer to hold returned old termios
  1908. */
  1909. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1910. {
  1911. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1912. unsigned long flags;
  1913. if (debug_level >= DEBUG_LEVEL_INFO)
  1914. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__, __LINE__,
  1915. tty->driver->name);
  1916. /* just return if nothing has changed */
  1917. if ((tty->termios.c_cflag == old_termios->c_cflag)
  1918. && (RELEVANT_IFLAG(tty->termios.c_iflag)
  1919. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1920. return;
  1921. mgslpc_change_params(info, tty);
  1922. /* Handle transition to B0 status */
  1923. if (old_termios->c_cflag & CBAUD &&
  1924. !(tty->termios.c_cflag & CBAUD)) {
  1925. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  1926. spin_lock_irqsave(&info->lock, flags);
  1927. set_signals(info);
  1928. spin_unlock_irqrestore(&info->lock, flags);
  1929. }
  1930. /* Handle transition away from B0 status */
  1931. if (!(old_termios->c_cflag & CBAUD) &&
  1932. tty->termios.c_cflag & CBAUD) {
  1933. info->serial_signals |= SerialSignal_DTR;
  1934. if (!(tty->termios.c_cflag & CRTSCTS) ||
  1935. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1936. info->serial_signals |= SerialSignal_RTS;
  1937. }
  1938. spin_lock_irqsave(&info->lock, flags);
  1939. set_signals(info);
  1940. spin_unlock_irqrestore(&info->lock, flags);
  1941. }
  1942. /* Handle turning off CRTSCTS */
  1943. if (old_termios->c_cflag & CRTSCTS &&
  1944. !(tty->termios.c_cflag & CRTSCTS)) {
  1945. tty->hw_stopped = 0;
  1946. tx_release(tty);
  1947. }
  1948. }
  1949. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1950. {
  1951. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1952. struct tty_port *port = &info->port;
  1953. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1954. return;
  1955. if (debug_level >= DEBUG_LEVEL_INFO)
  1956. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1957. __FILE__, __LINE__, info->device_name, port->count);
  1958. if (tty_port_close_start(port, tty, filp) == 0)
  1959. goto cleanup;
  1960. if (port->flags & ASYNC_INITIALIZED)
  1961. mgslpc_wait_until_sent(tty, info->timeout);
  1962. mgslpc_flush_buffer(tty);
  1963. tty_ldisc_flush(tty);
  1964. shutdown(info, tty);
  1965. tty_port_close_end(port, tty);
  1966. tty_port_tty_set(port, NULL);
  1967. cleanup:
  1968. if (debug_level >= DEBUG_LEVEL_INFO)
  1969. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__, __LINE__,
  1970. tty->driver->name, port->count);
  1971. }
  1972. /* Wait until the transmitter is empty.
  1973. */
  1974. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  1975. {
  1976. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1977. unsigned long orig_jiffies, char_time;
  1978. if (!info)
  1979. return;
  1980. if (debug_level >= DEBUG_LEVEL_INFO)
  1981. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  1982. __FILE__, __LINE__, info->device_name);
  1983. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  1984. return;
  1985. if (!(info->port.flags & ASYNC_INITIALIZED))
  1986. goto exit;
  1987. orig_jiffies = jiffies;
  1988. /* Set check interval to 1/5 of estimated time to
  1989. * send a character, and make it at least 1. The check
  1990. * interval should also be less than the timeout.
  1991. * Note: use tight timings here to satisfy the NIST-PCTS.
  1992. */
  1993. if (info->params.data_rate) {
  1994. char_time = info->timeout/(32 * 5);
  1995. if (!char_time)
  1996. char_time++;
  1997. } else
  1998. char_time = 1;
  1999. if (timeout)
  2000. char_time = min_t(unsigned long, char_time, timeout);
  2001. if (info->params.mode == MGSL_MODE_HDLC) {
  2002. while (info->tx_active) {
  2003. msleep_interruptible(jiffies_to_msecs(char_time));
  2004. if (signal_pending(current))
  2005. break;
  2006. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2007. break;
  2008. }
  2009. } else {
  2010. while ((info->tx_count || info->tx_active) &&
  2011. info->tx_enabled) {
  2012. msleep_interruptible(jiffies_to_msecs(char_time));
  2013. if (signal_pending(current))
  2014. break;
  2015. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2016. break;
  2017. }
  2018. }
  2019. exit:
  2020. if (debug_level >= DEBUG_LEVEL_INFO)
  2021. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2022. __FILE__, __LINE__, info->device_name);
  2023. }
  2024. /* Called by tty_hangup() when a hangup is signaled.
  2025. * This is the same as closing all open files for the port.
  2026. */
  2027. static void mgslpc_hangup(struct tty_struct *tty)
  2028. {
  2029. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2030. if (debug_level >= DEBUG_LEVEL_INFO)
  2031. printk("%s(%d):mgslpc_hangup(%s)\n",
  2032. __FILE__, __LINE__, info->device_name);
  2033. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2034. return;
  2035. mgslpc_flush_buffer(tty);
  2036. shutdown(info, tty);
  2037. tty_port_hangup(&info->port);
  2038. }
  2039. static int carrier_raised(struct tty_port *port)
  2040. {
  2041. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2042. unsigned long flags;
  2043. spin_lock_irqsave(&info->lock, flags);
  2044. get_signals(info);
  2045. spin_unlock_irqrestore(&info->lock, flags);
  2046. if (info->serial_signals & SerialSignal_DCD)
  2047. return 1;
  2048. return 0;
  2049. }
  2050. static void dtr_rts(struct tty_port *port, int onoff)
  2051. {
  2052. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2053. unsigned long flags;
  2054. spin_lock_irqsave(&info->lock, flags);
  2055. if (onoff)
  2056. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  2057. else
  2058. info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
  2059. set_signals(info);
  2060. spin_unlock_irqrestore(&info->lock, flags);
  2061. }
  2062. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2063. {
  2064. MGSLPC_INFO *info;
  2065. struct tty_port *port;
  2066. int retval, line;
  2067. unsigned long flags;
  2068. /* verify range of specified line number */
  2069. line = tty->index;
  2070. if (line >= mgslpc_device_count) {
  2071. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2072. __FILE__, __LINE__, line);
  2073. return -ENODEV;
  2074. }
  2075. /* find the info structure for the specified line */
  2076. info = mgslpc_device_list;
  2077. while(info && info->line != line)
  2078. info = info->next_device;
  2079. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2080. return -ENODEV;
  2081. port = &info->port;
  2082. tty->driver_data = info;
  2083. tty_port_tty_set(port, tty);
  2084. if (debug_level >= DEBUG_LEVEL_INFO)
  2085. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2086. __FILE__, __LINE__, tty->driver->name, port->count);
  2087. port->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2088. spin_lock_irqsave(&info->netlock, flags);
  2089. if (info->netcount) {
  2090. retval = -EBUSY;
  2091. spin_unlock_irqrestore(&info->netlock, flags);
  2092. goto cleanup;
  2093. }
  2094. spin_lock(&port->lock);
  2095. port->count++;
  2096. spin_unlock(&port->lock);
  2097. spin_unlock_irqrestore(&info->netlock, flags);
  2098. if (port->count == 1) {
  2099. /* 1st open on this device, init hardware */
  2100. retval = startup(info, tty);
  2101. if (retval < 0)
  2102. goto cleanup;
  2103. }
  2104. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2105. if (retval) {
  2106. if (debug_level >= DEBUG_LEVEL_INFO)
  2107. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2108. __FILE__, __LINE__, info->device_name, retval);
  2109. goto cleanup;
  2110. }
  2111. if (debug_level >= DEBUG_LEVEL_INFO)
  2112. printk("%s(%d):mgslpc_open(%s) success\n",
  2113. __FILE__, __LINE__, info->device_name);
  2114. retval = 0;
  2115. cleanup:
  2116. return retval;
  2117. }
  2118. /*
  2119. * /proc fs routines....
  2120. */
  2121. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2122. {
  2123. char stat_buf[30];
  2124. unsigned long flags;
  2125. seq_printf(m, "%s:io:%04X irq:%d",
  2126. info->device_name, info->io_base, info->irq_level);
  2127. /* output current serial signal states */
  2128. spin_lock_irqsave(&info->lock, flags);
  2129. get_signals(info);
  2130. spin_unlock_irqrestore(&info->lock, flags);
  2131. stat_buf[0] = 0;
  2132. stat_buf[1] = 0;
  2133. if (info->serial_signals & SerialSignal_RTS)
  2134. strcat(stat_buf, "|RTS");
  2135. if (info->serial_signals & SerialSignal_CTS)
  2136. strcat(stat_buf, "|CTS");
  2137. if (info->serial_signals & SerialSignal_DTR)
  2138. strcat(stat_buf, "|DTR");
  2139. if (info->serial_signals & SerialSignal_DSR)
  2140. strcat(stat_buf, "|DSR");
  2141. if (info->serial_signals & SerialSignal_DCD)
  2142. strcat(stat_buf, "|CD");
  2143. if (info->serial_signals & SerialSignal_RI)
  2144. strcat(stat_buf, "|RI");
  2145. if (info->params.mode == MGSL_MODE_HDLC) {
  2146. seq_printf(m, " HDLC txok:%d rxok:%d",
  2147. info->icount.txok, info->icount.rxok);
  2148. if (info->icount.txunder)
  2149. seq_printf(m, " txunder:%d", info->icount.txunder);
  2150. if (info->icount.txabort)
  2151. seq_printf(m, " txabort:%d", info->icount.txabort);
  2152. if (info->icount.rxshort)
  2153. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2154. if (info->icount.rxlong)
  2155. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2156. if (info->icount.rxover)
  2157. seq_printf(m, " rxover:%d", info->icount.rxover);
  2158. if (info->icount.rxcrc)
  2159. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2160. } else {
  2161. seq_printf(m, " ASYNC tx:%d rx:%d",
  2162. info->icount.tx, info->icount.rx);
  2163. if (info->icount.frame)
  2164. seq_printf(m, " fe:%d", info->icount.frame);
  2165. if (info->icount.parity)
  2166. seq_printf(m, " pe:%d", info->icount.parity);
  2167. if (info->icount.brk)
  2168. seq_printf(m, " brk:%d", info->icount.brk);
  2169. if (info->icount.overrun)
  2170. seq_printf(m, " oe:%d", info->icount.overrun);
  2171. }
  2172. /* Append serial signal status to end */
  2173. seq_printf(m, " %s\n", stat_buf+1);
  2174. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2175. info->tx_active,info->bh_requested,info->bh_running,
  2176. info->pending_bh);
  2177. }
  2178. /* Called to print information about devices
  2179. */
  2180. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2181. {
  2182. MGSLPC_INFO *info;
  2183. seq_printf(m, "synclink driver:%s\n", driver_version);
  2184. info = mgslpc_device_list;
  2185. while (info) {
  2186. line_info(m, info);
  2187. info = info->next_device;
  2188. }
  2189. return 0;
  2190. }
  2191. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2192. {
  2193. return single_open(file, mgslpc_proc_show, NULL);
  2194. }
  2195. static const struct file_operations mgslpc_proc_fops = {
  2196. .owner = THIS_MODULE,
  2197. .open = mgslpc_proc_open,
  2198. .read = seq_read,
  2199. .llseek = seq_lseek,
  2200. .release = single_release,
  2201. };
  2202. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2203. {
  2204. /* each buffer has header and data */
  2205. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2206. /* calculate total allocation size for 8 buffers */
  2207. info->rx_buf_total_size = info->rx_buf_size * 8;
  2208. /* limit total allocated memory */
  2209. if (info->rx_buf_total_size > 0x10000)
  2210. info->rx_buf_total_size = 0x10000;
  2211. /* calculate number of buffers */
  2212. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2213. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2214. if (info->rx_buf == NULL)
  2215. return -ENOMEM;
  2216. /* unused flag buffer to satisfy receive_buf calling interface */
  2217. info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
  2218. if (!info->flag_buf) {
  2219. kfree(info->rx_buf);
  2220. info->rx_buf = NULL;
  2221. return -ENOMEM;
  2222. }
  2223. rx_reset_buffers(info);
  2224. return 0;
  2225. }
  2226. static void rx_free_buffers(MGSLPC_INFO *info)
  2227. {
  2228. kfree(info->rx_buf);
  2229. info->rx_buf = NULL;
  2230. kfree(info->flag_buf);
  2231. info->flag_buf = NULL;
  2232. }
  2233. static int claim_resources(MGSLPC_INFO *info)
  2234. {
  2235. if (rx_alloc_buffers(info) < 0) {
  2236. printk("Can't allocate rx buffer %s\n", info->device_name);
  2237. release_resources(info);
  2238. return -ENODEV;
  2239. }
  2240. return 0;
  2241. }
  2242. static void release_resources(MGSLPC_INFO *info)
  2243. {
  2244. if (debug_level >= DEBUG_LEVEL_INFO)
  2245. printk("release_resources(%s)\n", info->device_name);
  2246. rx_free_buffers(info);
  2247. }
  2248. /* Add the specified device instance data structure to the
  2249. * global linked list of devices and increment the device count.
  2250. *
  2251. * Arguments: info pointer to device instance data
  2252. */
  2253. static int mgslpc_add_device(MGSLPC_INFO *info)
  2254. {
  2255. MGSLPC_INFO *current_dev = NULL;
  2256. struct device *tty_dev;
  2257. int ret;
  2258. info->next_device = NULL;
  2259. info->line = mgslpc_device_count;
  2260. sprintf(info->device_name,"ttySLP%d",info->line);
  2261. if (info->line < MAX_DEVICE_COUNT) {
  2262. if (maxframe[info->line])
  2263. info->max_frame_size = maxframe[info->line];
  2264. }
  2265. mgslpc_device_count++;
  2266. if (!mgslpc_device_list)
  2267. mgslpc_device_list = info;
  2268. else {
  2269. current_dev = mgslpc_device_list;
  2270. while (current_dev->next_device)
  2271. current_dev = current_dev->next_device;
  2272. current_dev->next_device = info;
  2273. }
  2274. if (info->max_frame_size < 4096)
  2275. info->max_frame_size = 4096;
  2276. else if (info->max_frame_size > 65535)
  2277. info->max_frame_size = 65535;
  2278. printk("SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2279. info->device_name, info->io_base, info->irq_level);
  2280. #if SYNCLINK_GENERIC_HDLC
  2281. ret = hdlcdev_init(info);
  2282. if (ret != 0)
  2283. goto failed;
  2284. #endif
  2285. tty_dev = tty_port_register_device(&info->port, serial_driver, info->line,
  2286. &info->p_dev->dev);
  2287. if (IS_ERR(tty_dev)) {
  2288. ret = PTR_ERR(tty_dev);
  2289. #if SYNCLINK_GENERIC_HDLC
  2290. hdlcdev_exit(info);
  2291. #endif
  2292. goto failed;
  2293. }
  2294. return 0;
  2295. failed:
  2296. if (current_dev)
  2297. current_dev->next_device = NULL;
  2298. else
  2299. mgslpc_device_list = NULL;
  2300. mgslpc_device_count--;
  2301. return ret;
  2302. }
  2303. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2304. {
  2305. MGSLPC_INFO *info = mgslpc_device_list;
  2306. MGSLPC_INFO *last = NULL;
  2307. while(info) {
  2308. if (info == remove_info) {
  2309. if (last)
  2310. last->next_device = info->next_device;
  2311. else
  2312. mgslpc_device_list = info->next_device;
  2313. tty_unregister_device(serial_driver, info->line);
  2314. #if SYNCLINK_GENERIC_HDLC
  2315. hdlcdev_exit(info);
  2316. #endif
  2317. release_resources(info);
  2318. tty_port_destroy(&info->port);
  2319. kfree(info);
  2320. mgslpc_device_count--;
  2321. return;
  2322. }
  2323. last = info;
  2324. info = info->next_device;
  2325. }
  2326. }
  2327. static const struct pcmcia_device_id mgslpc_ids[] = {
  2328. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2329. PCMCIA_DEVICE_NULL
  2330. };
  2331. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2332. static struct pcmcia_driver mgslpc_driver = {
  2333. .owner = THIS_MODULE,
  2334. .name = "synclink_cs",
  2335. .probe = mgslpc_probe,
  2336. .remove = mgslpc_detach,
  2337. .id_table = mgslpc_ids,
  2338. .suspend = mgslpc_suspend,
  2339. .resume = mgslpc_resume,
  2340. };
  2341. static const struct tty_operations mgslpc_ops = {
  2342. .open = mgslpc_open,
  2343. .close = mgslpc_close,
  2344. .write = mgslpc_write,
  2345. .put_char = mgslpc_put_char,
  2346. .flush_chars = mgslpc_flush_chars,
  2347. .write_room = mgslpc_write_room,
  2348. .chars_in_buffer = mgslpc_chars_in_buffer,
  2349. .flush_buffer = mgslpc_flush_buffer,
  2350. .ioctl = mgslpc_ioctl,
  2351. .throttle = mgslpc_throttle,
  2352. .unthrottle = mgslpc_unthrottle,
  2353. .send_xchar = mgslpc_send_xchar,
  2354. .break_ctl = mgslpc_break,
  2355. .wait_until_sent = mgslpc_wait_until_sent,
  2356. .set_termios = mgslpc_set_termios,
  2357. .stop = tx_pause,
  2358. .start = tx_release,
  2359. .hangup = mgslpc_hangup,
  2360. .tiocmget = tiocmget,
  2361. .tiocmset = tiocmset,
  2362. .get_icount = mgslpc_get_icount,
  2363. .proc_fops = &mgslpc_proc_fops,
  2364. };
  2365. static int __init synclink_cs_init(void)
  2366. {
  2367. int rc;
  2368. if (break_on_load) {
  2369. mgslpc_get_text_ptr();
  2370. BREAKPOINT();
  2371. }
  2372. serial_driver = tty_alloc_driver(MAX_DEVICE_COUNT,
  2373. TTY_DRIVER_REAL_RAW |
  2374. TTY_DRIVER_DYNAMIC_DEV);
  2375. if (IS_ERR(serial_driver)) {
  2376. rc = PTR_ERR(serial_driver);
  2377. goto err;
  2378. }
  2379. /* Initialize the tty_driver structure */
  2380. serial_driver->driver_name = "synclink_cs";
  2381. serial_driver->name = "ttySLP";
  2382. serial_driver->major = ttymajor;
  2383. serial_driver->minor_start = 64;
  2384. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2385. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2386. serial_driver->init_termios = tty_std_termios;
  2387. serial_driver->init_termios.c_cflag =
  2388. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2389. tty_set_operations(serial_driver, &mgslpc_ops);
  2390. rc = tty_register_driver(serial_driver);
  2391. if (rc < 0) {
  2392. printk(KERN_ERR "%s(%d):Couldn't register serial driver\n",
  2393. __FILE__, __LINE__);
  2394. goto err_put_tty;
  2395. }
  2396. rc = pcmcia_register_driver(&mgslpc_driver);
  2397. if (rc < 0)
  2398. goto err_unreg_tty;
  2399. printk(KERN_INFO "%s %s, tty major#%d\n", driver_name, driver_version,
  2400. serial_driver->major);
  2401. return 0;
  2402. err_unreg_tty:
  2403. tty_unregister_driver(serial_driver);
  2404. err_put_tty:
  2405. put_tty_driver(serial_driver);
  2406. err:
  2407. return rc;
  2408. }
  2409. static void __exit synclink_cs_exit(void)
  2410. {
  2411. pcmcia_unregister_driver(&mgslpc_driver);
  2412. tty_unregister_driver(serial_driver);
  2413. put_tty_driver(serial_driver);
  2414. }
  2415. module_init(synclink_cs_init);
  2416. module_exit(synclink_cs_exit);
  2417. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2418. {
  2419. unsigned int M, N;
  2420. unsigned char val;
  2421. /* note:standard BRG mode is broken in V3.2 chip
  2422. * so enhanced mode is always used
  2423. */
  2424. if (rate) {
  2425. N = 3686400 / rate;
  2426. if (!N)
  2427. N = 1;
  2428. N >>= 1;
  2429. for (M = 1; N > 64 && M < 16; M++)
  2430. N >>= 1;
  2431. N--;
  2432. /* BGR[5..0] = N
  2433. * BGR[9..6] = M
  2434. * BGR[7..0] contained in BGR register
  2435. * BGR[9..8] contained in CCR2[7..6]
  2436. * divisor = (N+1)*2^M
  2437. *
  2438. * Note: M *must* not be zero (causes asymetric duty cycle)
  2439. */
  2440. write_reg(info, (unsigned char) (channel + BGR),
  2441. (unsigned char) ((M << 6) + N));
  2442. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2443. val |= ((M << 4) & 0xc0);
  2444. write_reg(info, (unsigned char) (channel + CCR2), val);
  2445. }
  2446. }
  2447. /* Enabled the AUX clock output at the specified frequency.
  2448. */
  2449. static void enable_auxclk(MGSLPC_INFO *info)
  2450. {
  2451. unsigned char val;
  2452. /* MODE
  2453. *
  2454. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2455. * 05 ADM Address Mode, 0 = no addr recognition
  2456. * 04 TMD Timer Mode, 0 = external
  2457. * 03 RAC Receiver Active, 0 = inactive
  2458. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2459. * 01 TRS Timer Resolution, 1=512
  2460. * 00 TLP Test Loop, 0 = no loop
  2461. *
  2462. * 1000 0010
  2463. */
  2464. val = 0x82;
  2465. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2466. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2467. val |= BIT2;
  2468. write_reg(info, CHB + MODE, val);
  2469. /* CCR0
  2470. *
  2471. * 07 PU Power Up, 1=active, 0=power down
  2472. * 06 MCE Master Clock Enable, 1=enabled
  2473. * 05 Reserved, 0
  2474. * 04..02 SC[2..0] Encoding
  2475. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2476. *
  2477. * 11000000
  2478. */
  2479. write_reg(info, CHB + CCR0, 0xc0);
  2480. /* CCR1
  2481. *
  2482. * 07 SFLG Shared Flag, 0 = disable shared flags
  2483. * 06 GALP Go Active On Loop, 0 = not used
  2484. * 05 GLP Go On Loop, 0 = not used
  2485. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2486. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2487. * 02..00 CM[2..0] Clock Mode
  2488. *
  2489. * 0001 0111
  2490. */
  2491. write_reg(info, CHB + CCR1, 0x17);
  2492. /* CCR2 (Channel B)
  2493. *
  2494. * 07..06 BGR[9..8] Baud rate bits 9..8
  2495. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2496. * 04 SSEL Clock source select, 1=submode b
  2497. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2498. * 02 RWX Read/Write Exchange 0=disabled
  2499. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2500. * 00 DIV, data inversion 0=disabled, 1=enabled
  2501. *
  2502. * 0011 1000
  2503. */
  2504. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2505. write_reg(info, CHB + CCR2, 0x38);
  2506. else
  2507. write_reg(info, CHB + CCR2, 0x30);
  2508. /* CCR4
  2509. *
  2510. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2511. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2512. * 05 TST1 Test Pin, 0=normal operation
  2513. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2514. * 03..02 Reserved, must be 0
  2515. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2516. *
  2517. * 0101 0000
  2518. */
  2519. write_reg(info, CHB + CCR4, 0x50);
  2520. /* if auxclk not enabled, set internal BRG so
  2521. * CTS transitions can be detected (requires TxC)
  2522. */
  2523. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2524. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2525. else
  2526. mgslpc_set_rate(info, CHB, 921600);
  2527. }
  2528. static void loopback_enable(MGSLPC_INFO *info)
  2529. {
  2530. unsigned char val;
  2531. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2532. val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0);
  2533. write_reg(info, CHA + CCR1, val);
  2534. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2535. val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5);
  2536. write_reg(info, CHA + CCR2, val);
  2537. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2538. if (info->params.clock_speed)
  2539. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2540. else
  2541. mgslpc_set_rate(info, CHA, 1843200);
  2542. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2543. val = read_reg(info, CHA + MODE) | BIT0;
  2544. write_reg(info, CHA + MODE, val);
  2545. }
  2546. static void hdlc_mode(MGSLPC_INFO *info)
  2547. {
  2548. unsigned char val;
  2549. unsigned char clkmode, clksubmode;
  2550. /* disable all interrupts */
  2551. irq_disable(info, CHA, 0xffff);
  2552. irq_disable(info, CHB, 0xffff);
  2553. port_irq_disable(info, 0xff);
  2554. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2555. clkmode = clksubmode = 0;
  2556. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2557. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2558. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2559. clkmode = 7;
  2560. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2561. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2562. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2563. clkmode = 7;
  2564. clksubmode = 1;
  2565. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2566. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2567. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2568. clkmode = 6;
  2569. clksubmode = 1;
  2570. } else {
  2571. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2572. clkmode = 6;
  2573. }
  2574. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2575. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2576. clksubmode = 1;
  2577. }
  2578. /* MODE
  2579. *
  2580. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2581. * 05 ADM Address Mode, 0 = no addr recognition
  2582. * 04 TMD Timer Mode, 0 = external
  2583. * 03 RAC Receiver Active, 0 = inactive
  2584. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2585. * 01 TRS Timer Resolution, 1=512
  2586. * 00 TLP Test Loop, 0 = no loop
  2587. *
  2588. * 1000 0010
  2589. */
  2590. val = 0x82;
  2591. if (info->params.loopback)
  2592. val |= BIT0;
  2593. /* preserve RTS state */
  2594. if (info->serial_signals & SerialSignal_RTS)
  2595. val |= BIT2;
  2596. write_reg(info, CHA + MODE, val);
  2597. /* CCR0
  2598. *
  2599. * 07 PU Power Up, 1=active, 0=power down
  2600. * 06 MCE Master Clock Enable, 1=enabled
  2601. * 05 Reserved, 0
  2602. * 04..02 SC[2..0] Encoding
  2603. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2604. *
  2605. * 11000000
  2606. */
  2607. val = 0xc0;
  2608. switch (info->params.encoding)
  2609. {
  2610. case HDLC_ENCODING_NRZI:
  2611. val |= BIT3;
  2612. break;
  2613. case HDLC_ENCODING_BIPHASE_SPACE:
  2614. val |= BIT4;
  2615. break; // FM0
  2616. case HDLC_ENCODING_BIPHASE_MARK:
  2617. val |= BIT4 | BIT2;
  2618. break; // FM1
  2619. case HDLC_ENCODING_BIPHASE_LEVEL:
  2620. val |= BIT4 | BIT3;
  2621. break; // Manchester
  2622. }
  2623. write_reg(info, CHA + CCR0, val);
  2624. /* CCR1
  2625. *
  2626. * 07 SFLG Shared Flag, 0 = disable shared flags
  2627. * 06 GALP Go Active On Loop, 0 = not used
  2628. * 05 GLP Go On Loop, 0 = not used
  2629. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2630. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2631. * 02..00 CM[2..0] Clock Mode
  2632. *
  2633. * 0001 0000
  2634. */
  2635. val = 0x10 + clkmode;
  2636. write_reg(info, CHA + CCR1, val);
  2637. /* CCR2
  2638. *
  2639. * 07..06 BGR[9..8] Baud rate bits 9..8
  2640. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2641. * 04 SSEL Clock source select, 1=submode b
  2642. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2643. * 02 RWX Read/Write Exchange 0=disabled
  2644. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2645. * 00 DIV, data inversion 0=disabled, 1=enabled
  2646. *
  2647. * 0000 0000
  2648. */
  2649. val = 0x00;
  2650. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2651. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2652. val |= BIT5;
  2653. if (clksubmode)
  2654. val |= BIT4;
  2655. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2656. val |= BIT1;
  2657. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2658. val |= BIT0;
  2659. write_reg(info, CHA + CCR2, val);
  2660. /* CCR3
  2661. *
  2662. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2663. * 05 EPT Enable preamble transmission, 1=enabled
  2664. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2665. * 03 CRL CRC Reset Level, 0=FFFF
  2666. * 02 RCRC Rx CRC 0=On 1=Off
  2667. * 01 TCRC Tx CRC 0=On 1=Off
  2668. * 00 PSD DPLL Phase Shift Disable
  2669. *
  2670. * 0000 0000
  2671. */
  2672. val = 0x00;
  2673. if (info->params.crc_type == HDLC_CRC_NONE)
  2674. val |= BIT2 | BIT1;
  2675. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2676. val |= BIT5;
  2677. switch (info->params.preamble_length)
  2678. {
  2679. case HDLC_PREAMBLE_LENGTH_16BITS:
  2680. val |= BIT6;
  2681. break;
  2682. case HDLC_PREAMBLE_LENGTH_32BITS:
  2683. val |= BIT6;
  2684. break;
  2685. case HDLC_PREAMBLE_LENGTH_64BITS:
  2686. val |= BIT7 | BIT6;
  2687. break;
  2688. }
  2689. write_reg(info, CHA + CCR3, val);
  2690. /* PRE - Preamble pattern */
  2691. val = 0;
  2692. switch (info->params.preamble)
  2693. {
  2694. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2695. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2696. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2697. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2698. }
  2699. write_reg(info, CHA + PRE, val);
  2700. /* CCR4
  2701. *
  2702. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2703. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2704. * 05 TST1 Test Pin, 0=normal operation
  2705. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2706. * 03..02 Reserved, must be 0
  2707. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2708. *
  2709. * 0101 0000
  2710. */
  2711. val = 0x50;
  2712. write_reg(info, CHA + CCR4, val);
  2713. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2714. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2715. else
  2716. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2717. /* RLCR Receive length check register
  2718. *
  2719. * 7 1=enable receive length check
  2720. * 6..0 Max frame length = (RL + 1) * 32
  2721. */
  2722. write_reg(info, CHA + RLCR, 0);
  2723. /* XBCH Transmit Byte Count High
  2724. *
  2725. * 07 DMA mode, 0 = interrupt driven
  2726. * 06 NRM, 0=ABM (ignored)
  2727. * 05 CAS Carrier Auto Start
  2728. * 04 XC Transmit Continuously (ignored)
  2729. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2730. *
  2731. * 0000 0000
  2732. */
  2733. val = 0x00;
  2734. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2735. val |= BIT5;
  2736. write_reg(info, CHA + XBCH, val);
  2737. enable_auxclk(info);
  2738. if (info->params.loopback || info->testing_irq)
  2739. loopback_enable(info);
  2740. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2741. {
  2742. irq_enable(info, CHB, IRQ_CTS);
  2743. /* PVR[3] 1=AUTO CTS active */
  2744. set_reg_bits(info, CHA + PVR, BIT3);
  2745. } else
  2746. clear_reg_bits(info, CHA + PVR, BIT3);
  2747. irq_enable(info, CHA,
  2748. IRQ_RXEOM | IRQ_RXFIFO | IRQ_ALLSENT |
  2749. IRQ_UNDERRUN | IRQ_TXFIFO);
  2750. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2751. wait_command_complete(info, CHA);
  2752. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2753. /* Master clock mode enabled above to allow reset commands
  2754. * to complete even if no data clocks are present.
  2755. *
  2756. * Disable master clock mode for normal communications because
  2757. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2758. * IRQ when in master clock mode.
  2759. *
  2760. * Leave master clock mode enabled for IRQ test because the
  2761. * timer IRQ used by the test can only happen in master clock mode.
  2762. */
  2763. if (!info->testing_irq)
  2764. clear_reg_bits(info, CHA + CCR0, BIT6);
  2765. tx_set_idle(info);
  2766. tx_stop(info);
  2767. rx_stop(info);
  2768. }
  2769. static void rx_stop(MGSLPC_INFO *info)
  2770. {
  2771. if (debug_level >= DEBUG_LEVEL_ISR)
  2772. printk("%s(%d):rx_stop(%s)\n",
  2773. __FILE__, __LINE__, info->device_name);
  2774. /* MODE:03 RAC Receiver Active, 0=inactive */
  2775. clear_reg_bits(info, CHA + MODE, BIT3);
  2776. info->rx_enabled = false;
  2777. info->rx_overflow = false;
  2778. }
  2779. static void rx_start(MGSLPC_INFO *info)
  2780. {
  2781. if (debug_level >= DEBUG_LEVEL_ISR)
  2782. printk("%s(%d):rx_start(%s)\n",
  2783. __FILE__, __LINE__, info->device_name);
  2784. rx_reset_buffers(info);
  2785. info->rx_enabled = false;
  2786. info->rx_overflow = false;
  2787. /* MODE:03 RAC Receiver Active, 1=active */
  2788. set_reg_bits(info, CHA + MODE, BIT3);
  2789. info->rx_enabled = true;
  2790. }
  2791. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2792. {
  2793. if (debug_level >= DEBUG_LEVEL_ISR)
  2794. printk("%s(%d):tx_start(%s)\n",
  2795. __FILE__, __LINE__, info->device_name);
  2796. if (info->tx_count) {
  2797. /* If auto RTS enabled and RTS is inactive, then assert */
  2798. /* RTS and set a flag indicating that the driver should */
  2799. /* negate RTS when the transmission completes. */
  2800. info->drop_rts_on_tx_done = false;
  2801. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2802. get_signals(info);
  2803. if (!(info->serial_signals & SerialSignal_RTS)) {
  2804. info->serial_signals |= SerialSignal_RTS;
  2805. set_signals(info);
  2806. info->drop_rts_on_tx_done = true;
  2807. }
  2808. }
  2809. if (info->params.mode == MGSL_MODE_ASYNC) {
  2810. if (!info->tx_active) {
  2811. info->tx_active = true;
  2812. tx_ready(info, tty);
  2813. }
  2814. } else {
  2815. info->tx_active = true;
  2816. tx_ready(info, tty);
  2817. mod_timer(&info->tx_timer, jiffies +
  2818. msecs_to_jiffies(5000));
  2819. }
  2820. }
  2821. if (!info->tx_enabled)
  2822. info->tx_enabled = true;
  2823. }
  2824. static void tx_stop(MGSLPC_INFO *info)
  2825. {
  2826. if (debug_level >= DEBUG_LEVEL_ISR)
  2827. printk("%s(%d):tx_stop(%s)\n",
  2828. __FILE__, __LINE__, info->device_name);
  2829. del_timer(&info->tx_timer);
  2830. info->tx_enabled = false;
  2831. info->tx_active = false;
  2832. }
  2833. /* Reset the adapter to a known state and prepare it for further use.
  2834. */
  2835. static void reset_device(MGSLPC_INFO *info)
  2836. {
  2837. /* power up both channels (set BIT7) */
  2838. write_reg(info, CHA + CCR0, 0x80);
  2839. write_reg(info, CHB + CCR0, 0x80);
  2840. write_reg(info, CHA + MODE, 0);
  2841. write_reg(info, CHB + MODE, 0);
  2842. /* disable all interrupts */
  2843. irq_disable(info, CHA, 0xffff);
  2844. irq_disable(info, CHB, 0xffff);
  2845. port_irq_disable(info, 0xff);
  2846. /* PCR Port Configuration Register
  2847. *
  2848. * 07..04 DEC[3..0] Serial I/F select outputs
  2849. * 03 output, 1=AUTO CTS control enabled
  2850. * 02 RI Ring Indicator input 0=active
  2851. * 01 DSR input 0=active
  2852. * 00 DTR output 0=active
  2853. *
  2854. * 0000 0110
  2855. */
  2856. write_reg(info, PCR, 0x06);
  2857. /* PVR Port Value Register
  2858. *
  2859. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2860. * 03 AUTO CTS output 1=enabled
  2861. * 02 RI Ring Indicator input
  2862. * 01 DSR input
  2863. * 00 DTR output (1=inactive)
  2864. *
  2865. * 0000 0001
  2866. */
  2867. // write_reg(info, PVR, PVR_DTR);
  2868. /* IPC Interrupt Port Configuration
  2869. *
  2870. * 07 VIS 1=Masked interrupts visible
  2871. * 06..05 Reserved, 0
  2872. * 04..03 SLA Slave address, 00 ignored
  2873. * 02 CASM Cascading Mode, 1=daisy chain
  2874. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2875. *
  2876. * 0000 0101
  2877. */
  2878. write_reg(info, IPC, 0x05);
  2879. }
  2880. static void async_mode(MGSLPC_INFO *info)
  2881. {
  2882. unsigned char val;
  2883. /* disable all interrupts */
  2884. irq_disable(info, CHA, 0xffff);
  2885. irq_disable(info, CHB, 0xffff);
  2886. port_irq_disable(info, 0xff);
  2887. /* MODE
  2888. *
  2889. * 07 Reserved, 0
  2890. * 06 FRTS RTS State, 0=active
  2891. * 05 FCTS Flow Control on CTS
  2892. * 04 FLON Flow Control Enable
  2893. * 03 RAC Receiver Active, 0 = inactive
  2894. * 02 RTS 0=Auto RTS, 1=manual RTS
  2895. * 01 TRS Timer Resolution, 1=512
  2896. * 00 TLP Test Loop, 0 = no loop
  2897. *
  2898. * 0000 0110
  2899. */
  2900. val = 0x06;
  2901. if (info->params.loopback)
  2902. val |= BIT0;
  2903. /* preserve RTS state */
  2904. if (!(info->serial_signals & SerialSignal_RTS))
  2905. val |= BIT6;
  2906. write_reg(info, CHA + MODE, val);
  2907. /* CCR0
  2908. *
  2909. * 07 PU Power Up, 1=active, 0=power down
  2910. * 06 MCE Master Clock Enable, 1=enabled
  2911. * 05 Reserved, 0
  2912. * 04..02 SC[2..0] Encoding, 000=NRZ
  2913. * 01..00 SM[1..0] Serial Mode, 11=Async
  2914. *
  2915. * 1000 0011
  2916. */
  2917. write_reg(info, CHA + CCR0, 0x83);
  2918. /* CCR1
  2919. *
  2920. * 07..05 Reserved, 0
  2921. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2922. * 03 BCR Bit Clock Rate, 1=16x
  2923. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2924. *
  2925. * 0001 1111
  2926. */
  2927. write_reg(info, CHA + CCR1, 0x1f);
  2928. /* CCR2 (channel A)
  2929. *
  2930. * 07..06 BGR[9..8] Baud rate bits 9..8
  2931. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2932. * 04 SSEL Clock source select, 1=submode b
  2933. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2934. * 02 RWX Read/Write Exchange 0=disabled
  2935. * 01 Reserved, 0
  2936. * 00 DIV, data inversion 0=disabled, 1=enabled
  2937. *
  2938. * 0001 0000
  2939. */
  2940. write_reg(info, CHA + CCR2, 0x10);
  2941. /* CCR3
  2942. *
  2943. * 07..01 Reserved, 0
  2944. * 00 PSD DPLL Phase Shift Disable
  2945. *
  2946. * 0000 0000
  2947. */
  2948. write_reg(info, CHA + CCR3, 0);
  2949. /* CCR4
  2950. *
  2951. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2952. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2953. * 05 TST1 Test Pin, 0=normal operation
  2954. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2955. * 03..00 Reserved, must be 0
  2956. *
  2957. * 0101 0000
  2958. */
  2959. write_reg(info, CHA + CCR4, 0x50);
  2960. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2961. /* DAFO Data Format
  2962. *
  2963. * 07 Reserved, 0
  2964. * 06 XBRK transmit break, 0=normal operation
  2965. * 05 Stop bits (0=1, 1=2)
  2966. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2967. * 02 PAREN Parity Enable
  2968. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2969. *
  2970. */
  2971. val = 0x00;
  2972. if (info->params.data_bits != 8)
  2973. val |= BIT0; /* 7 bits */
  2974. if (info->params.stop_bits != 1)
  2975. val |= BIT5;
  2976. if (info->params.parity != ASYNC_PARITY_NONE)
  2977. {
  2978. val |= BIT2; /* Parity enable */
  2979. if (info->params.parity == ASYNC_PARITY_ODD)
  2980. val |= BIT3;
  2981. else
  2982. val |= BIT4;
  2983. }
  2984. write_reg(info, CHA + DAFO, val);
  2985. /* RFC Rx FIFO Control
  2986. *
  2987. * 07 Reserved, 0
  2988. * 06 DPS, 1=parity bit not stored in data byte
  2989. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  2990. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  2991. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  2992. * 01 Reserved, 0
  2993. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  2994. *
  2995. * 0101 1100
  2996. */
  2997. write_reg(info, CHA + RFC, 0x5c);
  2998. /* RLCR Receive length check register
  2999. *
  3000. * Max frame length = (RL + 1) * 32
  3001. */
  3002. write_reg(info, CHA + RLCR, 0);
  3003. /* XBCH Transmit Byte Count High
  3004. *
  3005. * 07 DMA mode, 0 = interrupt driven
  3006. * 06 NRM, 0=ABM (ignored)
  3007. * 05 CAS Carrier Auto Start
  3008. * 04 XC Transmit Continuously (ignored)
  3009. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3010. *
  3011. * 0000 0000
  3012. */
  3013. val = 0x00;
  3014. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3015. val |= BIT5;
  3016. write_reg(info, CHA + XBCH, val);
  3017. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3018. irq_enable(info, CHA, IRQ_CTS);
  3019. /* MODE:03 RAC Receiver Active, 1=active */
  3020. set_reg_bits(info, CHA + MODE, BIT3);
  3021. enable_auxclk(info);
  3022. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3023. irq_enable(info, CHB, IRQ_CTS);
  3024. /* PVR[3] 1=AUTO CTS active */
  3025. set_reg_bits(info, CHA + PVR, BIT3);
  3026. } else
  3027. clear_reg_bits(info, CHA + PVR, BIT3);
  3028. irq_enable(info, CHA,
  3029. IRQ_RXEOM | IRQ_RXFIFO | IRQ_BREAK_ON | IRQ_RXTIME |
  3030. IRQ_ALLSENT | IRQ_TXFIFO);
  3031. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3032. wait_command_complete(info, CHA);
  3033. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3034. }
  3035. /* Set the HDLC idle mode for the transmitter.
  3036. */
  3037. static void tx_set_idle(MGSLPC_INFO *info)
  3038. {
  3039. /* Note: ESCC2 only supports flags and one idle modes */
  3040. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3041. set_reg_bits(info, CHA + CCR1, BIT3);
  3042. else
  3043. clear_reg_bits(info, CHA + CCR1, BIT3);
  3044. }
  3045. /* get state of the V24 status (input) signals.
  3046. */
  3047. static void get_signals(MGSLPC_INFO *info)
  3048. {
  3049. unsigned char status = 0;
  3050. /* preserve RTS and DTR */
  3051. info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
  3052. if (read_reg(info, CHB + VSTR) & BIT7)
  3053. info->serial_signals |= SerialSignal_DCD;
  3054. if (read_reg(info, CHB + STAR) & BIT1)
  3055. info->serial_signals |= SerialSignal_CTS;
  3056. status = read_reg(info, CHA + PVR);
  3057. if (!(status & PVR_RI))
  3058. info->serial_signals |= SerialSignal_RI;
  3059. if (!(status & PVR_DSR))
  3060. info->serial_signals |= SerialSignal_DSR;
  3061. }
  3062. /* Set the state of RTS and DTR based on contents of
  3063. * serial_signals member of device extension.
  3064. */
  3065. static void set_signals(MGSLPC_INFO *info)
  3066. {
  3067. unsigned char val;
  3068. val = read_reg(info, CHA + MODE);
  3069. if (info->params.mode == MGSL_MODE_ASYNC) {
  3070. if (info->serial_signals & SerialSignal_RTS)
  3071. val &= ~BIT6;
  3072. else
  3073. val |= BIT6;
  3074. } else {
  3075. if (info->serial_signals & SerialSignal_RTS)
  3076. val |= BIT2;
  3077. else
  3078. val &= ~BIT2;
  3079. }
  3080. write_reg(info, CHA + MODE, val);
  3081. if (info->serial_signals & SerialSignal_DTR)
  3082. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3083. else
  3084. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3085. }
  3086. static void rx_reset_buffers(MGSLPC_INFO *info)
  3087. {
  3088. RXBUF *buf;
  3089. int i;
  3090. info->rx_put = 0;
  3091. info->rx_get = 0;
  3092. info->rx_frame_count = 0;
  3093. for (i=0 ; i < info->rx_buf_count ; i++) {
  3094. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3095. buf->status = buf->count = 0;
  3096. }
  3097. }
  3098. /* Attempt to return a received HDLC frame
  3099. * Only frames received without errors are returned.
  3100. *
  3101. * Returns true if frame returned, otherwise false
  3102. */
  3103. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3104. {
  3105. unsigned short status;
  3106. RXBUF *buf;
  3107. unsigned int framesize = 0;
  3108. unsigned long flags;
  3109. bool return_frame = false;
  3110. if (info->rx_frame_count == 0)
  3111. return false;
  3112. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3113. status = buf->status;
  3114. /* 07 VFR 1=valid frame
  3115. * 06 RDO 1=data overrun
  3116. * 05 CRC 1=OK, 0=error
  3117. * 04 RAB 1=frame aborted
  3118. */
  3119. if ((status & 0xf0) != 0xA0) {
  3120. if (!(status & BIT7) || (status & BIT4))
  3121. info->icount.rxabort++;
  3122. else if (status & BIT6)
  3123. info->icount.rxover++;
  3124. else if (!(status & BIT5)) {
  3125. info->icount.rxcrc++;
  3126. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3127. return_frame = true;
  3128. }
  3129. framesize = 0;
  3130. #if SYNCLINK_GENERIC_HDLC
  3131. {
  3132. info->netdev->stats.rx_errors++;
  3133. info->netdev->stats.rx_frame_errors++;
  3134. }
  3135. #endif
  3136. } else
  3137. return_frame = true;
  3138. if (return_frame)
  3139. framesize = buf->count;
  3140. if (debug_level >= DEBUG_LEVEL_BH)
  3141. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3142. __FILE__, __LINE__, info->device_name, status, framesize);
  3143. if (debug_level >= DEBUG_LEVEL_DATA)
  3144. trace_block(info, buf->data, framesize, 0);
  3145. if (framesize) {
  3146. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3147. framesize+1 > info->max_frame_size) ||
  3148. framesize > info->max_frame_size)
  3149. info->icount.rxlong++;
  3150. else {
  3151. if (status & BIT5)
  3152. info->icount.rxok++;
  3153. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3154. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3155. ++framesize;
  3156. }
  3157. #if SYNCLINK_GENERIC_HDLC
  3158. if (info->netcount)
  3159. hdlcdev_rx(info, buf->data, framesize);
  3160. else
  3161. #endif
  3162. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3163. }
  3164. }
  3165. spin_lock_irqsave(&info->lock, flags);
  3166. buf->status = buf->count = 0;
  3167. info->rx_frame_count--;
  3168. info->rx_get++;
  3169. if (info->rx_get >= info->rx_buf_count)
  3170. info->rx_get = 0;
  3171. spin_unlock_irqrestore(&info->lock, flags);
  3172. return true;
  3173. }
  3174. static bool register_test(MGSLPC_INFO *info)
  3175. {
  3176. static unsigned char patterns[] =
  3177. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3178. static unsigned int count = ARRAY_SIZE(patterns);
  3179. unsigned int i;
  3180. bool rc = true;
  3181. unsigned long flags;
  3182. spin_lock_irqsave(&info->lock, flags);
  3183. reset_device(info);
  3184. for (i = 0; i < count; i++) {
  3185. write_reg(info, XAD1, patterns[i]);
  3186. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3187. if ((read_reg(info, XAD1) != patterns[i]) ||
  3188. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3189. rc = false;
  3190. break;
  3191. }
  3192. }
  3193. spin_unlock_irqrestore(&info->lock, flags);
  3194. return rc;
  3195. }
  3196. static bool irq_test(MGSLPC_INFO *info)
  3197. {
  3198. unsigned long end_time;
  3199. unsigned long flags;
  3200. spin_lock_irqsave(&info->lock, flags);
  3201. reset_device(info);
  3202. info->testing_irq = true;
  3203. hdlc_mode(info);
  3204. info->irq_occurred = false;
  3205. /* init hdlc mode */
  3206. irq_enable(info, CHA, IRQ_TIMER);
  3207. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3208. issue_command(info, CHA, CMD_START_TIMER);
  3209. spin_unlock_irqrestore(&info->lock, flags);
  3210. end_time=100;
  3211. while(end_time-- && !info->irq_occurred) {
  3212. msleep_interruptible(10);
  3213. }
  3214. info->testing_irq = false;
  3215. spin_lock_irqsave(&info->lock, flags);
  3216. reset_device(info);
  3217. spin_unlock_irqrestore(&info->lock, flags);
  3218. return info->irq_occurred;
  3219. }
  3220. static int adapter_test(MGSLPC_INFO *info)
  3221. {
  3222. if (!register_test(info)) {
  3223. info->init_error = DiagStatus_AddressFailure;
  3224. printk("%s(%d):Register test failure for device %s Addr=%04X\n",
  3225. __FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
  3226. return -ENODEV;
  3227. }
  3228. if (!irq_test(info)) {
  3229. info->init_error = DiagStatus_IrqFailure;
  3230. printk("%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3231. __FILE__, __LINE__, info->device_name, (unsigned short)(info->irq_level));
  3232. return -ENODEV;
  3233. }
  3234. if (debug_level >= DEBUG_LEVEL_INFO)
  3235. printk("%s(%d):device %s passed diagnostics\n",
  3236. __FILE__, __LINE__, info->device_name);
  3237. return 0;
  3238. }
  3239. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3240. {
  3241. int i;
  3242. int linecount;
  3243. if (xmit)
  3244. printk("%s tx data:\n", info->device_name);
  3245. else
  3246. printk("%s rx data:\n", info->device_name);
  3247. while(count) {
  3248. if (count > 16)
  3249. linecount = 16;
  3250. else
  3251. linecount = count;
  3252. for(i=0;i<linecount;i++)
  3253. printk("%02X ", (unsigned char)data[i]);
  3254. for(;i<17;i++)
  3255. printk(" ");
  3256. for(i=0;i<linecount;i++) {
  3257. if (data[i]>=040 && data[i]<=0176)
  3258. printk("%c", data[i]);
  3259. else
  3260. printk(".");
  3261. }
  3262. printk("\n");
  3263. data += linecount;
  3264. count -= linecount;
  3265. }
  3266. }
  3267. /* HDLC frame time out
  3268. * update stats and do tx completion processing
  3269. */
  3270. static void tx_timeout(unsigned long context)
  3271. {
  3272. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3273. unsigned long flags;
  3274. if (debug_level >= DEBUG_LEVEL_INFO)
  3275. printk("%s(%d):tx_timeout(%s)\n",
  3276. __FILE__, __LINE__, info->device_name);
  3277. if (info->tx_active &&
  3278. info->params.mode == MGSL_MODE_HDLC) {
  3279. info->icount.txtimeout++;
  3280. }
  3281. spin_lock_irqsave(&info->lock, flags);
  3282. info->tx_active = false;
  3283. info->tx_count = info->tx_put = info->tx_get = 0;
  3284. spin_unlock_irqrestore(&info->lock, flags);
  3285. #if SYNCLINK_GENERIC_HDLC
  3286. if (info->netcount)
  3287. hdlcdev_tx_done(info);
  3288. else
  3289. #endif
  3290. {
  3291. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3292. bh_transmit(info, tty);
  3293. tty_kref_put(tty);
  3294. }
  3295. }
  3296. #if SYNCLINK_GENERIC_HDLC
  3297. /**
  3298. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3299. * set encoding and frame check sequence (FCS) options
  3300. *
  3301. * dev pointer to network device structure
  3302. * encoding serial encoding setting
  3303. * parity FCS setting
  3304. *
  3305. * returns 0 if success, otherwise error code
  3306. */
  3307. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3308. unsigned short parity)
  3309. {
  3310. MGSLPC_INFO *info = dev_to_port(dev);
  3311. struct tty_struct *tty;
  3312. unsigned char new_encoding;
  3313. unsigned short new_crctype;
  3314. /* return error if TTY interface open */
  3315. if (info->port.count)
  3316. return -EBUSY;
  3317. switch (encoding)
  3318. {
  3319. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3320. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3321. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3322. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3323. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3324. default: return -EINVAL;
  3325. }
  3326. switch (parity)
  3327. {
  3328. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3329. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3330. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3331. default: return -EINVAL;
  3332. }
  3333. info->params.encoding = new_encoding;
  3334. info->params.crc_type = new_crctype;
  3335. /* if network interface up, reprogram hardware */
  3336. if (info->netcount) {
  3337. tty = tty_port_tty_get(&info->port);
  3338. mgslpc_program_hw(info, tty);
  3339. tty_kref_put(tty);
  3340. }
  3341. return 0;
  3342. }
  3343. /**
  3344. * called by generic HDLC layer to send frame
  3345. *
  3346. * skb socket buffer containing HDLC frame
  3347. * dev pointer to network device structure
  3348. */
  3349. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3350. struct net_device *dev)
  3351. {
  3352. MGSLPC_INFO *info = dev_to_port(dev);
  3353. unsigned long flags;
  3354. if (debug_level >= DEBUG_LEVEL_INFO)
  3355. printk(KERN_INFO "%s:hdlc_xmit(%s)\n", __FILE__, dev->name);
  3356. /* stop sending until this frame completes */
  3357. netif_stop_queue(dev);
  3358. /* copy data to device buffers */
  3359. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3360. info->tx_get = 0;
  3361. info->tx_put = info->tx_count = skb->len;
  3362. /* update network statistics */
  3363. dev->stats.tx_packets++;
  3364. dev->stats.tx_bytes += skb->len;
  3365. /* done with socket buffer, so free it */
  3366. dev_kfree_skb(skb);
  3367. /* save start time for transmit timeout detection */
  3368. dev->trans_start = jiffies;
  3369. /* start hardware transmitter if necessary */
  3370. spin_lock_irqsave(&info->lock, flags);
  3371. if (!info->tx_active) {
  3372. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3373. tx_start(info, tty);
  3374. tty_kref_put(tty);
  3375. }
  3376. spin_unlock_irqrestore(&info->lock, flags);
  3377. return NETDEV_TX_OK;
  3378. }
  3379. /**
  3380. * called by network layer when interface enabled
  3381. * claim resources and initialize hardware
  3382. *
  3383. * dev pointer to network device structure
  3384. *
  3385. * returns 0 if success, otherwise error code
  3386. */
  3387. static int hdlcdev_open(struct net_device *dev)
  3388. {
  3389. MGSLPC_INFO *info = dev_to_port(dev);
  3390. struct tty_struct *tty;
  3391. int rc;
  3392. unsigned long flags;
  3393. if (debug_level >= DEBUG_LEVEL_INFO)
  3394. printk("%s:hdlcdev_open(%s)\n", __FILE__, dev->name);
  3395. /* generic HDLC layer open processing */
  3396. rc = hdlc_open(dev);
  3397. if (rc != 0)
  3398. return rc;
  3399. /* arbitrate between network and tty opens */
  3400. spin_lock_irqsave(&info->netlock, flags);
  3401. if (info->port.count != 0 || info->netcount != 0) {
  3402. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3403. spin_unlock_irqrestore(&info->netlock, flags);
  3404. return -EBUSY;
  3405. }
  3406. info->netcount=1;
  3407. spin_unlock_irqrestore(&info->netlock, flags);
  3408. tty = tty_port_tty_get(&info->port);
  3409. /* claim resources and init adapter */
  3410. rc = startup(info, tty);
  3411. if (rc != 0) {
  3412. tty_kref_put(tty);
  3413. spin_lock_irqsave(&info->netlock, flags);
  3414. info->netcount=0;
  3415. spin_unlock_irqrestore(&info->netlock, flags);
  3416. return rc;
  3417. }
  3418. /* assert RTS and DTR, apply hardware settings */
  3419. info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
  3420. mgslpc_program_hw(info, tty);
  3421. tty_kref_put(tty);
  3422. /* enable network layer transmit */
  3423. dev->trans_start = jiffies;
  3424. netif_start_queue(dev);
  3425. /* inform generic HDLC layer of current DCD status */
  3426. spin_lock_irqsave(&info->lock, flags);
  3427. get_signals(info);
  3428. spin_unlock_irqrestore(&info->lock, flags);
  3429. if (info->serial_signals & SerialSignal_DCD)
  3430. netif_carrier_on(dev);
  3431. else
  3432. netif_carrier_off(dev);
  3433. return 0;
  3434. }
  3435. /**
  3436. * called by network layer when interface is disabled
  3437. * shutdown hardware and release resources
  3438. *
  3439. * dev pointer to network device structure
  3440. *
  3441. * returns 0 if success, otherwise error code
  3442. */
  3443. static int hdlcdev_close(struct net_device *dev)
  3444. {
  3445. MGSLPC_INFO *info = dev_to_port(dev);
  3446. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3447. unsigned long flags;
  3448. if (debug_level >= DEBUG_LEVEL_INFO)
  3449. printk("%s:hdlcdev_close(%s)\n", __FILE__, dev->name);
  3450. netif_stop_queue(dev);
  3451. /* shutdown adapter and release resources */
  3452. shutdown(info, tty);
  3453. tty_kref_put(tty);
  3454. hdlc_close(dev);
  3455. spin_lock_irqsave(&info->netlock, flags);
  3456. info->netcount=0;
  3457. spin_unlock_irqrestore(&info->netlock, flags);
  3458. return 0;
  3459. }
  3460. /**
  3461. * called by network layer to process IOCTL call to network device
  3462. *
  3463. * dev pointer to network device structure
  3464. * ifr pointer to network interface request structure
  3465. * cmd IOCTL command code
  3466. *
  3467. * returns 0 if success, otherwise error code
  3468. */
  3469. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3470. {
  3471. const size_t size = sizeof(sync_serial_settings);
  3472. sync_serial_settings new_line;
  3473. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3474. MGSLPC_INFO *info = dev_to_port(dev);
  3475. unsigned int flags;
  3476. if (debug_level >= DEBUG_LEVEL_INFO)
  3477. printk("%s:hdlcdev_ioctl(%s)\n", __FILE__, dev->name);
  3478. /* return error if TTY interface open */
  3479. if (info->port.count)
  3480. return -EBUSY;
  3481. if (cmd != SIOCWANDEV)
  3482. return hdlc_ioctl(dev, ifr, cmd);
  3483. memset(&new_line, 0, size);
  3484. switch(ifr->ifr_settings.type) {
  3485. case IF_GET_IFACE: /* return current sync_serial_settings */
  3486. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3487. if (ifr->ifr_settings.size < size) {
  3488. ifr->ifr_settings.size = size; /* data size wanted */
  3489. return -ENOBUFS;
  3490. }
  3491. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3492. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3493. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3494. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3495. switch (flags){
  3496. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3497. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3498. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3499. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3500. default: new_line.clock_type = CLOCK_DEFAULT;
  3501. }
  3502. new_line.clock_rate = info->params.clock_speed;
  3503. new_line.loopback = info->params.loopback ? 1:0;
  3504. if (copy_to_user(line, &new_line, size))
  3505. return -EFAULT;
  3506. return 0;
  3507. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3508. if(!capable(CAP_NET_ADMIN))
  3509. return -EPERM;
  3510. if (copy_from_user(&new_line, line, size))
  3511. return -EFAULT;
  3512. switch (new_line.clock_type)
  3513. {
  3514. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3515. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3516. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3517. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3518. case CLOCK_DEFAULT: flags = info->params.flags &
  3519. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3520. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3521. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3522. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3523. default: return -EINVAL;
  3524. }
  3525. if (new_line.loopback != 0 && new_line.loopback != 1)
  3526. return -EINVAL;
  3527. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3528. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3529. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3530. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3531. info->params.flags |= flags;
  3532. info->params.loopback = new_line.loopback;
  3533. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3534. info->params.clock_speed = new_line.clock_rate;
  3535. else
  3536. info->params.clock_speed = 0;
  3537. /* if network interface up, reprogram hardware */
  3538. if (info->netcount) {
  3539. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3540. mgslpc_program_hw(info, tty);
  3541. tty_kref_put(tty);
  3542. }
  3543. return 0;
  3544. default:
  3545. return hdlc_ioctl(dev, ifr, cmd);
  3546. }
  3547. }
  3548. /**
  3549. * called by network layer when transmit timeout is detected
  3550. *
  3551. * dev pointer to network device structure
  3552. */
  3553. static void hdlcdev_tx_timeout(struct net_device *dev)
  3554. {
  3555. MGSLPC_INFO *info = dev_to_port(dev);
  3556. unsigned long flags;
  3557. if (debug_level >= DEBUG_LEVEL_INFO)
  3558. printk("hdlcdev_tx_timeout(%s)\n", dev->name);
  3559. dev->stats.tx_errors++;
  3560. dev->stats.tx_aborted_errors++;
  3561. spin_lock_irqsave(&info->lock, flags);
  3562. tx_stop(info);
  3563. spin_unlock_irqrestore(&info->lock, flags);
  3564. netif_wake_queue(dev);
  3565. }
  3566. /**
  3567. * called by device driver when transmit completes
  3568. * reenable network layer transmit if stopped
  3569. *
  3570. * info pointer to device instance information
  3571. */
  3572. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3573. {
  3574. if (netif_queue_stopped(info->netdev))
  3575. netif_wake_queue(info->netdev);
  3576. }
  3577. /**
  3578. * called by device driver when frame received
  3579. * pass frame to network layer
  3580. *
  3581. * info pointer to device instance information
  3582. * buf pointer to buffer contianing frame data
  3583. * size count of data bytes in buf
  3584. */
  3585. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3586. {
  3587. struct sk_buff *skb = dev_alloc_skb(size);
  3588. struct net_device *dev = info->netdev;
  3589. if (debug_level >= DEBUG_LEVEL_INFO)
  3590. printk("hdlcdev_rx(%s)\n", dev->name);
  3591. if (skb == NULL) {
  3592. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3593. dev->stats.rx_dropped++;
  3594. return;
  3595. }
  3596. memcpy(skb_put(skb, size), buf, size);
  3597. skb->protocol = hdlc_type_trans(skb, dev);
  3598. dev->stats.rx_packets++;
  3599. dev->stats.rx_bytes += size;
  3600. netif_rx(skb);
  3601. }
  3602. static const struct net_device_ops hdlcdev_ops = {
  3603. .ndo_open = hdlcdev_open,
  3604. .ndo_stop = hdlcdev_close,
  3605. .ndo_change_mtu = hdlc_change_mtu,
  3606. .ndo_start_xmit = hdlc_start_xmit,
  3607. .ndo_do_ioctl = hdlcdev_ioctl,
  3608. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3609. };
  3610. /**
  3611. * called by device driver when adding device instance
  3612. * do generic HDLC initialization
  3613. *
  3614. * info pointer to device instance information
  3615. *
  3616. * returns 0 if success, otherwise error code
  3617. */
  3618. static int hdlcdev_init(MGSLPC_INFO *info)
  3619. {
  3620. int rc;
  3621. struct net_device *dev;
  3622. hdlc_device *hdlc;
  3623. /* allocate and initialize network and HDLC layer objects */
  3624. dev = alloc_hdlcdev(info);
  3625. if (dev == NULL) {
  3626. printk(KERN_ERR "%s:hdlc device allocation failure\n", __FILE__);
  3627. return -ENOMEM;
  3628. }
  3629. /* for network layer reporting purposes only */
  3630. dev->base_addr = info->io_base;
  3631. dev->irq = info->irq_level;
  3632. /* network layer callbacks and settings */
  3633. dev->netdev_ops = &hdlcdev_ops;
  3634. dev->watchdog_timeo = 10 * HZ;
  3635. dev->tx_queue_len = 50;
  3636. /* generic HDLC layer callbacks and settings */
  3637. hdlc = dev_to_hdlc(dev);
  3638. hdlc->attach = hdlcdev_attach;
  3639. hdlc->xmit = hdlcdev_xmit;
  3640. /* register objects with HDLC layer */
  3641. rc = register_hdlc_device(dev);
  3642. if (rc) {
  3643. printk(KERN_WARNING "%s:unable to register hdlc device\n", __FILE__);
  3644. free_netdev(dev);
  3645. return rc;
  3646. }
  3647. info->netdev = dev;
  3648. return 0;
  3649. }
  3650. /**
  3651. * called by device driver when removing device instance
  3652. * do generic HDLC cleanup
  3653. *
  3654. * info pointer to device instance information
  3655. */
  3656. static void hdlcdev_exit(MGSLPC_INFO *info)
  3657. {
  3658. unregister_hdlc_device(info->netdev);
  3659. free_netdev(info->netdev);
  3660. info->netdev = NULL;
  3661. }
  3662. #endif /* CONFIG_HDLC */