tpm_crb.c 8.3 KB

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  1. /*
  2. * Copyright (C) 2014 Intel Corporation
  3. *
  4. * Authors:
  5. * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
  6. *
  7. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  8. *
  9. * This device driver implements the TPM interface as defined in
  10. * the TCG CRB 2.0 TPM specification.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; version 2
  15. * of the License.
  16. */
  17. #include <linux/acpi.h>
  18. #include <linux/highmem.h>
  19. #include <linux/rculist.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include "tpm.h"
  23. #define ACPI_SIG_TPM2 "TPM2"
  24. static const u8 CRB_ACPI_START_UUID[] = {
  25. /* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
  26. /* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
  27. };
  28. enum crb_defaults {
  29. CRB_ACPI_START_REVISION_ID = 1,
  30. CRB_ACPI_START_INDEX = 1,
  31. };
  32. struct acpi_tpm2 {
  33. struct acpi_table_header hdr;
  34. u16 platform_class;
  35. u16 reserved;
  36. u64 control_area_pa;
  37. u32 start_method;
  38. } __packed;
  39. enum crb_ca_request {
  40. CRB_CA_REQ_GO_IDLE = BIT(0),
  41. CRB_CA_REQ_CMD_READY = BIT(1),
  42. };
  43. enum crb_ca_status {
  44. CRB_CA_STS_ERROR = BIT(0),
  45. CRB_CA_STS_TPM_IDLE = BIT(1),
  46. };
  47. enum crb_start {
  48. CRB_START_INVOKE = BIT(0),
  49. };
  50. enum crb_cancel {
  51. CRB_CANCEL_INVOKE = BIT(0),
  52. };
  53. struct crb_control_area {
  54. u32 req;
  55. u32 sts;
  56. u32 cancel;
  57. u32 start;
  58. u32 int_enable;
  59. u32 int_sts;
  60. u32 cmd_size;
  61. u32 cmd_pa_low;
  62. u32 cmd_pa_high;
  63. u32 rsp_size;
  64. u64 rsp_pa;
  65. } __packed;
  66. enum crb_status {
  67. CRB_STS_COMPLETE = BIT(0),
  68. };
  69. enum crb_flags {
  70. CRB_FL_ACPI_START = BIT(0),
  71. CRB_FL_CRB_START = BIT(1),
  72. };
  73. struct crb_priv {
  74. unsigned int flags;
  75. struct crb_control_area __iomem *cca;
  76. u8 __iomem *cmd;
  77. u8 __iomem *rsp;
  78. };
  79. static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
  80. static u8 crb_status(struct tpm_chip *chip)
  81. {
  82. struct crb_priv *priv = chip->vendor.priv;
  83. u8 sts = 0;
  84. if ((le32_to_cpu(ioread32(&priv->cca->start)) & CRB_START_INVOKE) !=
  85. CRB_START_INVOKE)
  86. sts |= CRB_STS_COMPLETE;
  87. return sts;
  88. }
  89. static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  90. {
  91. struct crb_priv *priv = chip->vendor.priv;
  92. unsigned int expected;
  93. /* A sanity check that the upper layer wants to get at least the header
  94. * as that is the minimum size for any TPM response.
  95. */
  96. if (count < TPM_HEADER_SIZE)
  97. return -EIO;
  98. /* If this bit is set, according to the spec, the TPM is in
  99. * unrecoverable condition.
  100. */
  101. if (le32_to_cpu(ioread32(&priv->cca->sts)) & CRB_CA_STS_ERROR)
  102. return -EIO;
  103. /* Read the first 8 bytes in order to get the length of the response.
  104. * We read exactly a quad word in order to make sure that the remaining
  105. * reads will be aligned.
  106. */
  107. memcpy_fromio(buf, priv->rsp, 8);
  108. expected = be32_to_cpup((__be32 *)&buf[2]);
  109. if (expected > count || expected < TPM_HEADER_SIZE)
  110. return -EIO;
  111. memcpy_fromio(&buf[8], &priv->rsp[8], expected - 8);
  112. return expected;
  113. }
  114. static int crb_do_acpi_start(struct tpm_chip *chip)
  115. {
  116. union acpi_object *obj;
  117. int rc;
  118. obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
  119. CRB_ACPI_START_UUID,
  120. CRB_ACPI_START_REVISION_ID,
  121. CRB_ACPI_START_INDEX,
  122. NULL);
  123. if (!obj)
  124. return -ENXIO;
  125. rc = obj->integer.value == 0 ? 0 : -ENXIO;
  126. ACPI_FREE(obj);
  127. return rc;
  128. }
  129. static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
  130. {
  131. struct crb_priv *priv = chip->vendor.priv;
  132. int rc = 0;
  133. /* Zero the cancel register so that the next command will not get
  134. * canceled.
  135. */
  136. iowrite32(0, &priv->cca->cancel);
  137. if (len > le32_to_cpu(ioread32(&priv->cca->cmd_size))) {
  138. dev_err(&chip->dev,
  139. "invalid command count value %x %zx\n",
  140. (unsigned int) len,
  141. (size_t) le32_to_cpu(ioread32(&priv->cca->cmd_size)));
  142. return -E2BIG;
  143. }
  144. memcpy_toio(priv->cmd, buf, len);
  145. /* Make sure that cmd is populated before issuing start. */
  146. wmb();
  147. if (priv->flags & CRB_FL_CRB_START)
  148. iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);
  149. if (priv->flags & CRB_FL_ACPI_START)
  150. rc = crb_do_acpi_start(chip);
  151. return rc;
  152. }
  153. static void crb_cancel(struct tpm_chip *chip)
  154. {
  155. struct crb_priv *priv = chip->vendor.priv;
  156. iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);
  157. /* Make sure that cmd is populated before issuing cancel. */
  158. wmb();
  159. if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
  160. dev_err(&chip->dev, "ACPI Start failed\n");
  161. }
  162. static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
  163. {
  164. struct crb_priv *priv = chip->vendor.priv;
  165. u32 cancel = le32_to_cpu(ioread32(&priv->cca->cancel));
  166. return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
  167. }
  168. static const struct tpm_class_ops tpm_crb = {
  169. .status = crb_status,
  170. .recv = crb_recv,
  171. .send = crb_send,
  172. .cancel = crb_cancel,
  173. .req_canceled = crb_req_canceled,
  174. .req_complete_mask = CRB_STS_COMPLETE,
  175. .req_complete_val = CRB_STS_COMPLETE,
  176. };
  177. static int crb_acpi_add(struct acpi_device *device)
  178. {
  179. struct tpm_chip *chip;
  180. struct acpi_tpm2 *buf;
  181. struct crb_priv *priv;
  182. struct device *dev = &device->dev;
  183. acpi_status status;
  184. u32 sm;
  185. u64 pa;
  186. int rc;
  187. status = acpi_get_table(ACPI_SIG_TPM2, 1,
  188. (struct acpi_table_header **) &buf);
  189. if (ACPI_FAILURE(status)) {
  190. dev_err(dev, "failed to get TPM2 ACPI table\n");
  191. return -ENODEV;
  192. }
  193. /* Should the FIFO driver handle this? */
  194. if (buf->start_method == TPM2_START_FIFO)
  195. return -ENODEV;
  196. chip = tpmm_chip_alloc(dev, &tpm_crb);
  197. if (IS_ERR(chip))
  198. return PTR_ERR(chip);
  199. chip->flags = TPM_CHIP_FLAG_TPM2;
  200. if (buf->hdr.length < sizeof(struct acpi_tpm2)) {
  201. dev_err(dev, "TPM2 ACPI table has wrong size");
  202. return -EINVAL;
  203. }
  204. priv = (struct crb_priv *) devm_kzalloc(dev, sizeof(struct crb_priv),
  205. GFP_KERNEL);
  206. if (!priv) {
  207. dev_err(dev, "failed to devm_kzalloc for private data\n");
  208. return -ENOMEM;
  209. }
  210. sm = le32_to_cpu(buf->start_method);
  211. /* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
  212. * report only ACPI start but in practice seems to require both
  213. * ACPI start and CRB start.
  214. */
  215. if (sm == TPM2_START_CRB || sm == TPM2_START_FIFO ||
  216. !strcmp(acpi_device_hid(device), "MSFT0101"))
  217. priv->flags |= CRB_FL_CRB_START;
  218. if (sm == TPM2_START_ACPI || sm == TPM2_START_CRB_WITH_ACPI)
  219. priv->flags |= CRB_FL_ACPI_START;
  220. priv->cca = (struct crb_control_area __iomem *)
  221. devm_ioremap_nocache(dev, buf->control_area_pa, 0x1000);
  222. if (!priv->cca) {
  223. dev_err(dev, "ioremap of the control area failed\n");
  224. return -ENOMEM;
  225. }
  226. pa = ((u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_high)) << 32) |
  227. (u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_low));
  228. priv->cmd = devm_ioremap_nocache(dev, pa,
  229. ioread32(&priv->cca->cmd_size));
  230. if (!priv->cmd) {
  231. dev_err(dev, "ioremap of the command buffer failed\n");
  232. return -ENOMEM;
  233. }
  234. memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
  235. pa = le64_to_cpu(pa);
  236. priv->rsp = devm_ioremap_nocache(dev, pa,
  237. ioread32(&priv->cca->rsp_size));
  238. if (!priv->rsp) {
  239. dev_err(dev, "ioremap of the response buffer failed\n");
  240. return -ENOMEM;
  241. }
  242. chip->vendor.priv = priv;
  243. /* Default timeouts and durations */
  244. chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
  245. chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
  246. chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
  247. chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
  248. chip->vendor.duration[TPM_SHORT] =
  249. msecs_to_jiffies(TPM2_DURATION_SHORT);
  250. chip->vendor.duration[TPM_MEDIUM] =
  251. msecs_to_jiffies(TPM2_DURATION_MEDIUM);
  252. chip->vendor.duration[TPM_LONG] =
  253. msecs_to_jiffies(TPM2_DURATION_LONG);
  254. chip->acpi_dev_handle = device->handle;
  255. rc = tpm2_do_selftest(chip);
  256. if (rc)
  257. return rc;
  258. return tpm_chip_register(chip);
  259. }
  260. static int crb_acpi_remove(struct acpi_device *device)
  261. {
  262. struct device *dev = &device->dev;
  263. struct tpm_chip *chip = dev_get_drvdata(dev);
  264. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  265. tpm2_shutdown(chip, TPM2_SU_CLEAR);
  266. tpm_chip_unregister(chip);
  267. return 0;
  268. }
  269. static struct acpi_device_id crb_device_ids[] = {
  270. {"MSFT0101", 0},
  271. {"", 0},
  272. };
  273. MODULE_DEVICE_TABLE(acpi, crb_device_ids);
  274. static struct acpi_driver crb_acpi_driver = {
  275. .name = "tpm_crb",
  276. .ids = crb_device_ids,
  277. .ops = {
  278. .add = crb_acpi_add,
  279. .remove = crb_acpi_remove,
  280. },
  281. .drv = {
  282. .pm = &crb_pm,
  283. },
  284. };
  285. module_acpi_driver(crb_acpi_driver);
  286. MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
  287. MODULE_DESCRIPTION("TPM2 Driver");
  288. MODULE_VERSION("0.1");
  289. MODULE_LICENSE("GPL");