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clk-hi6220.c

clk-hi6220.c 18 KB
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  1. /*
    2. 

  2.  * Hisilicon Hi6220 clock driver
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2015 Hisilicon Limited.
    5. 

  5.  *
    6. 

  6.  * Author: Bintian Wang <bintian.wang@huawei.com>
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU General Public License version 2 as
    10. 

  10.  * published by the Free Software Foundation.
    11. 

  11.  */
    12. 

  12. 

  13. #include <linux/kernel.h>
    14. 

  14. #include <linux/clk-provider.h>
    15. 

  15. #include <linux/clkdev.h>
    16. 

  16. #include <linux/io.h>
    17. 

  17. #include <linux/of.h>
    18. 

  18. #include <linux/of_address.h>
    19. 

  19. #include <linux/of_device.h>
    20. 

  20. #include <linux/slab.h>
    21. 

  21. 

  22. #include <dt-bindings/clock/hi6220-clock.h>
    23. 

  23. 

  24. #include "clk.h"
    25. 

  25. 

  26. 

  27. /* clocks in AO (always on) controller */
    28. 

  28. static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
    29. 

  29. 	{ HI6220_REF32K,	"ref32k",	NULL, CLK_IS_ROOT, 32764,     },
    30. 

  30. 	{ HI6220_CLK_TCXO,	"clk_tcxo",	NULL, CLK_IS_ROOT, 19200000,  },
    31. 

  31. 	{ HI6220_MMC1_PAD,	"mmc1_pad",	NULL, CLK_IS_ROOT, 100000000, },
    32. 

  32. 	{ HI6220_MMC2_PAD,	"mmc2_pad",	NULL, CLK_IS_ROOT, 100000000, },
    33. 

  33. 	{ HI6220_MMC0_PAD,	"mmc0_pad",	NULL, CLK_IS_ROOT, 200000000, },
    34. 

  34. 	{ HI6220_PLL_BBP,	"bbppll0",	NULL, CLK_IS_ROOT, 245760000, },
    35. 

  35. 	{ HI6220_PLL_GPU,	"gpupll",	NULL, CLK_IS_ROOT, 1000000000,},
    36. 

  36. 	{ HI6220_PLL1_DDR,	"ddrpll1",	NULL, CLK_IS_ROOT, 1066000000,},
    37. 

  37. 	{ HI6220_PLL_SYS,	"syspll",	NULL, CLK_IS_ROOT, 1200000000,},
    38. 

  38. 	{ HI6220_PLL_SYS_MEDIA,	"media_syspll",	NULL, CLK_IS_ROOT, 1200000000,},
    39. 

  39. 	{ HI6220_DDR_SRC,	"ddr_sel_src",  NULL, CLK_IS_ROOT, 1200000000,},
    40. 

  40. 	{ HI6220_PLL_MEDIA,	"media_pll",    NULL, CLK_IS_ROOT, 1440000000,},
    41. 

  41. 	{ HI6220_PLL_DDR,	"ddrpll0",      NULL, CLK_IS_ROOT, 1600000000,},
    42. 

  42. };
    43. 

  43. 

  44. static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
    45. 

  45. 	{ HI6220_300M,         "clk_300m",    "syspll",          1, 4, 0, },
    46. 

  46. 	{ HI6220_150M,         "clk_150m",    "clk_300m",        1, 2, 0, },
    47. 

  47. 	{ HI6220_PICOPHY_SRC,  "picophy_src", "clk_150m",        1, 4, 0, },
    48. 

  48. 	{ HI6220_MMC0_SRC_SEL, "mmc0srcsel",  "mmc0_sel",        1, 8, 0, },
    49. 

  49. 	{ HI6220_MMC1_SRC_SEL, "mmc1srcsel",  "mmc1_sel",        1, 8, 0, },
    50. 

  50. 	{ HI6220_MMC2_SRC_SEL, "mmc2srcsel",  "mmc2_sel",        1, 8, 0, },
    51. 

  51. 	{ HI6220_VPU_CODEC,    "vpucodec",    "codec_jpeg_aclk", 1, 2, 0, },
    52. 

  52. 	{ HI6220_MMC0_SMP,     "mmc0_sample", "mmc0_sel",        1, 8, 0, },
    53. 

  53. 	{ HI6220_MMC1_SMP,     "mmc1_sample", "mmc1_sel",        1, 8, 0, },
    54. 

  54. 	{ HI6220_MMC2_SMP,     "mmc2_sample", "mmc2_sel",        1, 8, 0, },
    55. 

  55. };
    56. 

  56. 

  57. static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
    58. 

  58. 	{ HI6220_WDT0_PCLK,   "wdt0_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
    59. 

  59. 	{ HI6220_WDT1_PCLK,   "wdt1_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
    60. 

  60. 	{ HI6220_WDT2_PCLK,   "wdt2_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
    61. 

  61. 	{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
    62. 

  62. 	{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
    63. 

  63. 	{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
    64. 

  64. 	{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
    65. 

  65. 	{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
    66. 

  66. 	{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
    67. 

  67. 	{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21, 0, },
    68. 

  68. 	{ HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
    69. 

  69. 	{ HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
    70. 

  70. 	{ HI6220_UART0_PCLK,  "uart0_pclk",  "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
    71. 

  71. };
    72. 

  72. 

  73. static void __init hi6220_clk_ao_init(struct device_node *np)
    74. 

  74. {
    75. 

  75. 	struct hisi_clock_data *clk_data_ao;
    76. 

  76. 

  77. 	clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
    78. 

  78. 	if (!clk_data_ao)
    79. 

  79. 		return;
    80. 

  80. 

  81. 	hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
    82. 

  82. 				ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);
    83. 

  83. 

  84. 	hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
    85. 

  85. 				ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);
    86. 

  86. 

  87. 	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
    88. 

  88. 				ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
    89. 

  89. }
    90. 

  90. CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
    91. 

  91. 

  92. 

  93. /* clocks in sysctrl */
    94. 

  94. static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
    95. 

  95. static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
    96. 

  96. static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
    97. 

  97. static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
    98. 

  98. static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
    99. 

  99. static const char *mmc1_src_p[]  __initdata = { "mmc1srcsel", "mmc1_div", };
    100. 

  100. static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
    101. 

  101. static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
    102. 

  102. static const char *mmc2_src_p[]  __initdata = { "mmc2srcsel", "mmc2_div", };
    103. 

  103. static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
    104. 

  104. static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
    105. 

  105. static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
    106. 

  106. static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
    107. 

  107. static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
    108. 

  108. static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
    109. 

  109. static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
    110. 

  110. static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
    111. 

  111. 

  112. static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
    113. 

  113. 	{ HI6220_MMC0_CLK,      "mmc0_clk",      "mmc0_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0,  0, },
    114. 

  114. 	{ HI6220_MMC0_CIUCLK,   "mmc0_ciuclk",   "mmc0_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0,  0, },
    115. 

  115. 	{ HI6220_MMC1_CLK,      "mmc1_clk",      "mmc1_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1,  0, },
    116. 

  116. 	{ HI6220_MMC1_CIUCLK,   "mmc1_ciuclk",   "mmc1_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1,  0, },
    117. 

  117. 	{ HI6220_MMC2_CLK,      "mmc2_clk",      "mmc2_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2,  0, },
    118. 

  118. 	{ HI6220_MMC2_CIUCLK,   "mmc2_ciuclk",   "mmc2_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2,  0, },
    119. 

  119. 	{ HI6220_USBOTG_HCLK,   "usbotg_hclk",   "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 4,  0, },
    120. 

  120. 	{ HI6220_CLK_PICOPHY,   "clk_picophy",   "cs_dapb",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 5,  0, },
    121. 

  121. 	{ HI6220_HIFI,          "hifi_clk",      "hifi_div",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 0,  0, },
    122. 

  122. 	{ HI6220_DACODEC_PCLK,  "dacodec_pclk",  "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 5,  0, },
    123. 

  123. 	{ HI6220_EDMAC_ACLK,    "edmac_aclk",    "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x220, 2,  0, },
    124. 

  124. 	{ HI6220_CS_ATB,        "cs_atb",        "cs_atb_div",     CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 0,  0, },
    125. 

  125. 	{ HI6220_I2C0_CLK,      "i2c0_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 1,  0, },
    126. 

  126. 	{ HI6220_I2C1_CLK,      "i2c1_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 2,  0, },
    127. 

  127. 	{ HI6220_I2C2_CLK,      "i2c2_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 3,  0, },
    128. 

  128. 	{ HI6220_I2C3_CLK,      "i2c3_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 4,  0, },
    129. 

  129. 	{ HI6220_UART1_PCLK,    "uart1_pclk",    "uart1_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 5,  0, },
    130. 

  130. 	{ HI6220_UART2_PCLK,    "uart2_pclk",    "uart2_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 6,  0, },
    131. 

  131. 	{ HI6220_UART3_PCLK,    "uart3_pclk",    "uart3_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 7,  0, },
    132. 

  132. 	{ HI6220_UART4_PCLK,    "uart4_pclk",    "uart4_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8,  0, },
    133. 

  133. 	{ HI6220_SPI_CLK,       "spi_clk",       "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9,  0, },
    134. 

  134. 	{ HI6220_TSENSOR_CLK,   "tsensor_clk",   "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
    135. 

  135. 	{ HI6220_MMU_CLK,       "mmu_clk",       "ddrc_axi1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
    136. 

  136. 	{ HI6220_HIFI_SEL,      "hifi_sel",      "hifi_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0,  0, },
    137. 

  137. 	{ HI6220_MMC0_SYSPLL,   "mmc0_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1,  0, },
    138. 

  138. 	{ HI6220_MMC1_SYSPLL,   "mmc1_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 2,  0, },
    139. 

  139. 	{ HI6220_MMC2_SYSPLL,   "mmc2_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 3,  0, },
    140. 

  140. 	{ HI6220_MMC0_SEL,      "mmc0_sel",      "mmc0_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 6,  0, },
    141. 

  141. 	{ HI6220_MMC1_SEL,      "mmc1_sel",      "mmc1_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 7,  0, },
    142. 

  142. 	{ HI6220_BBPPLL_SEL,    "bbppll_sel",    "pll0_bbp_gate",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9,  0, },
    143. 

  143. 	{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
    144. 

  144. 	{ HI6220_MMC2_SEL,      "mmc2_sel",      "mmc2_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
    145. 

  145. 	{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
    146. 

  146. };
    147. 

  147. 

  148. static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
    149. 

  149. 	{ HI6220_MMC0_SRC,    "mmc0_src",    mmc0_src_p,     ARRAY_SIZE(mmc0_src_p),     CLK_SET_RATE_PARENT, 0x4,   0,  1, 0, },
    150. 

  150. 	{ HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4,   0,  1, 0, },
    151. 

  151. 	{ HI6220_MMC1_SRC,    "mmc1_src",    mmc1_src_p,     ARRAY_SIZE(mmc1_src_p),     CLK_SET_RATE_PARENT, 0x4,   2,  1, 0, },
    152. 

  152. 	{ HI6220_MMC1_SMP_IN, "mmc1_smp_in", mmc1_sample_in, ARRAY_SIZE(mmc1_sample_in), CLK_SET_RATE_PARENT, 0x4,   2,  1, 0, },
    153. 

  153. 	{ HI6220_MMC2_SRC,    "mmc2_src",    mmc2_src_p,     ARRAY_SIZE(mmc2_src_p),     CLK_SET_RATE_PARENT, 0x4,   4,  1, 0, },
    154. 

  154. 	{ HI6220_MMC2_SMP_IN, "mmc2_smp_in", mmc2_sample_in, ARRAY_SIZE(mmc2_sample_in), CLK_SET_RATE_PARENT, 0x4,   4,  1, 0, },
    155. 

  155. 	{ HI6220_HIFI_SRC,    "hifi_src",    hifi_src,       ARRAY_SIZE(hifi_src),       CLK_SET_RATE_PARENT, 0x400, 0,  1, CLK_MUX_HIWORD_MASK,},
    156. 

  156. 	{ HI6220_UART1_SRC,   "uart1_src",   uart1_src,      ARRAY_SIZE(uart1_src),      CLK_SET_RATE_PARENT, 0x400, 1,  1, CLK_MUX_HIWORD_MASK,},
    157. 

  157. 	{ HI6220_UART2_SRC,   "uart2_src",   uart2_src,      ARRAY_SIZE(uart2_src),      CLK_SET_RATE_PARENT, 0x400, 2,  1, CLK_MUX_HIWORD_MASK,},
    158. 

  158. 	{ HI6220_UART3_SRC,   "uart3_src",   uart3_src,      ARRAY_SIZE(uart3_src),      CLK_SET_RATE_PARENT, 0x400, 3,  1, CLK_MUX_HIWORD_MASK,},
    159. 

  159. 	{ HI6220_UART4_SRC,   "uart4_src",   uart4_src,      ARRAY_SIZE(uart4_src),      CLK_SET_RATE_PARENT, 0x400, 4,  1, CLK_MUX_HIWORD_MASK,},
    160. 

  160. 	{ HI6220_MMC0_MUX0,   "mmc0_mux0",   mmc0_mux0_p,    ARRAY_SIZE(mmc0_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 5,  1, CLK_MUX_HIWORD_MASK,},
    161. 

  161. 	{ HI6220_MMC1_MUX0,   "mmc1_mux0",   mmc1_mux0_p,    ARRAY_SIZE(mmc1_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
    162. 

  162. 	{ HI6220_MMC2_MUX0,   "mmc2_mux0",   mmc2_mux0_p,    ARRAY_SIZE(mmc2_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
    163. 

  163. 	{ HI6220_MMC0_MUX1,   "mmc0_mux1",   mmc0_mux1_p,    ARRAY_SIZE(mmc0_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
    164. 

  164. 	{ HI6220_MMC1_MUX1,   "mmc1_mux1",   mmc1_mux1_p,    ARRAY_SIZE(mmc1_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
    165. 

  165. 	{ HI6220_MMC2_MUX1,   "mmc2_mux1",   mmc2_mux1_p,    ARRAY_SIZE(mmc2_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},
    166. 

  166. };
    167. 

  167. 

  168. static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
    169. 

  169. 	{ HI6220_CLK_BUS,     "clk_bus",     "clk_300m",      CLK_SET_RATE_PARENT, 0x490, 0,  4, 7, },
    170. 

  170. 	{ HI6220_MMC0_DIV,    "mmc0_div",    "mmc0_syspll",   CLK_SET_RATE_PARENT, 0x494, 0,  6, 7, },
    171. 

  171. 	{ HI6220_MMC1_DIV,    "mmc1_div",    "mmc1_syspll",   CLK_SET_RATE_PARENT, 0x498, 0,  6, 7, },
    172. 

  172. 	{ HI6220_MMC2_DIV,    "mmc2_div",    "mmc2_syspll",   CLK_SET_RATE_PARENT, 0x49c, 0,  6, 7, },
    173. 

  173. 	{ HI6220_HIFI_DIV,    "hifi_div",    "hifi_sel",      CLK_SET_RATE_PARENT, 0x4a0, 0,  4, 7, },
    174. 

  174. 	{ HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel",    CLK_SET_RATE_PARENT, 0x4a0, 8,  6, 15,},
    175. 

  175. 	{ HI6220_CS_DAPB,     "cs_dapb",     "picophy_src",   CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
    176. 

  176. 	{ HI6220_CS_ATB_DIV,  "cs_atb_div",  "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0,  4, 7, },
    177. 

  177. };
    178. 

  178. 

  179. static void __init hi6220_clk_sys_init(struct device_node *np)
    180. 

  180. {
    181. 

  181. 	struct hisi_clock_data *clk_data;
    182. 

  182. 

  183. 	clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
    184. 

  184. 	if (!clk_data)
    185. 

  185. 		return;
    186. 

  186. 

  187. 	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
    188. 

  188. 			ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
    189. 

  189. 

  190. 	hisi_clk_register_mux(hi6220_mux_clks_sys,
    191. 

  191. 			ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
    192. 

  192. 

  193. 	hi6220_clk_register_divider(hi6220_div_clks_sys,
    194. 

  194. 			ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
    195. 

  195. }
    196. 

  196. CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
    197. 

  197. 

  198. 

  199. /* clocks in media controller */
    200. 

  200. static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
    201. 

  201. static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
    202. 

  202. static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
    203. 

  203. 

  204. static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
    205. 

  205. 	{ HI6220_DSI_PCLK,       "dsi_pclk",         "vpucodec",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0,  0, },
    206. 

  206. 	{ HI6220_G3D_PCLK,       "g3d_pclk",         "vpucodec",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1,  0, },
    207. 

  207. 	{ HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu",   "ade_core_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3,  0, },
    208. 

  208. 	{ HI6220_ISP_SCLK,       "isp_sclk",         "isp_sclk_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 5,  0, },
    209. 

  209. 	{ HI6220_ADE_CORE,	 "ade_core",	     "ade_core_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 6,  0, },
    210. 

  210. 	{ HI6220_MED_MMU,        "media_mmu",        "mmu_clk",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 8,  0, },
    211. 

  211. 	{ HI6220_CFG_CSI4PHY,    "cfg_csi4phy",      "clk_tcxo",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 9,  0, },
    212. 

  212. 	{ HI6220_CFG_CSI2PHY,    "cfg_csi2phy",      "clk_tcxo",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 10, 0, },
    213. 

  213. 	{ HI6220_ISP_SCLK_GATE,  "isp_sclk_gate",    "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 11, 0, },
    214. 

  214. 	{ HI6220_ISP_SCLK_GATE1, "isp_sclk_gate1",   "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 12, 0, },
    215. 

  215. 	{ HI6220_ADE_CORE_GATE,  "ade_core_gate",    "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 14, 0, },
    216. 

  216. 	{ HI6220_CODEC_VPU_GATE, "codec_vpu_gate",   "clk_1000_1440", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 15, 0, },
    217. 

  217. 	{ HI6220_MED_SYSPLL,     "media_syspll_src", "media_syspll",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, },
    218. 

  218. };
    219. 

  219. 

  220. static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
    221. 

  221. 	{ HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, },
    222. 

  222. 	{ HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, },
    223. 

  223. 	{ HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, },
    224. 

  224. };
    225. 

  225. 

  226. static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
    227. 

  227. 	{ HI6220_CODEC_JPEG,    "codec_jpeg_aclk", "media_pll_src",  CLK_SET_RATE_PARENT, 0xcbc, 0,  4, 23, },
    228. 

  228. 	{ HI6220_ISP_SCLK_SRC,  "isp_sclk_src",    "isp_sclk_gate",  CLK_SET_RATE_PARENT, 0xcbc, 8,  4, 15, },
    229. 

  229. 	{ HI6220_ISP_SCLK1,     "isp_sclk1",       "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, },
    230. 

  230. 	{ HI6220_ADE_CORE_SRC,  "ade_core_src",    "ade_core_gate",  CLK_SET_RATE_PARENT, 0xcc0, 16, 3, 23, },
    231. 

  231. 	{ HI6220_ADE_PIX_SRC,   "ade_pix_src",     "clk_1440_1200",  CLK_SET_RATE_PARENT, 0xcc0, 24, 6, 31, },
    232. 

  232. 	{ HI6220_G3D_CLK,       "g3d_clk",         "clk_1000_1200",  CLK_SET_RATE_PARENT, 0xcc4, 8,  4, 15, },
    233. 

  233. 	{ HI6220_CODEC_VPU_SRC, "codec_vpu_src",   "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, },
    234. 

  234. };
    235. 

  235. 

  236. static void __init hi6220_clk_media_init(struct device_node *np)
    237. 

  237. {
    238. 

  238. 	struct hisi_clock_data *clk_data;
    239. 

  239. 

  240. 	clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
    241. 

  241. 	if (!clk_data)
    242. 

  242. 		return;
    243. 

  243. 

  244. 	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
    245. 

  245. 				ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);
    246. 

  246. 

  247. 	hisi_clk_register_mux(hi6220_mux_clks_media,
    248. 

  248. 				ARRAY_SIZE(hi6220_mux_clks_media), clk_data);
    249. 

  249. 

  250. 	hi6220_clk_register_divider(hi6220_div_clks_media,
    251. 

  251. 				ARRAY_SIZE(hi6220_div_clks_media), clk_data);
    252. 

  252. }
    253. 

  253. CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
    254. 

  254. 

  255. 

  256. /* clocks in pmctrl */
    257. 

  257. static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
    258. 

  258. 	{ HI6220_PLL_GPU_GATE,   "pll_gpu_gate",   "gpupll",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8,  0,  0, },
    259. 

  259. 	{ HI6220_PLL1_DDR_GATE,  "pll1_ddr_gate",  "ddrpll1",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0,  0, },
    260. 

  260. 	{ HI6220_PLL_DDR_GATE,   "pll_ddr_gate",   "ddrpll0",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0,  0, },
    261. 

  261. 	{ HI6220_PLL_MEDIA_GATE, "pll_media_gate", "media_pll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x38, 0,  0, },
    262. 

  262. 	{ HI6220_PLL0_BBP_GATE,  "pll0_bbp_gate",  "bbppll0",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0,  0, },
    263. 

  263. };
    264. 

  264. 

  265. static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {
    266. 

  266. 	{ HI6220_DDRC_SRC,  "ddrc_src",  "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
    267. 

  267. 	{ HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src",    CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
    268. 

  268. };
    269. 

  269. 

  270. static void __init hi6220_clk_power_init(struct device_node *np)
    271. 

  271. {
    272. 

  272. 	struct hisi_clock_data *clk_data;
    273. 

  273. 

  274. 	clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
    275. 

  275. 	if (!clk_data)
    276. 

  276. 		return;
    277. 

  277. 

  278. 	hisi_clk_register_gate(hi6220_gate_clks_power,
    279. 

  279. 				ARRAY_SIZE(hi6220_gate_clks_power), clk_data);
    280. 

  280. 

  281. 	hi6220_clk_register_divider(hi6220_div_clks_power,
    282. 

  282. 				ARRAY_SIZE(hi6220_div_clks_power), clk_data);
    283. 

  283. }
    284. 

  284. CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
    285.