clk-cpu.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108
  1. /*
  2. * Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/slab.h>
  14. #include "clk.h"
  15. struct clk_cpu {
  16. struct clk_hw hw;
  17. struct clk *div;
  18. struct clk *mux;
  19. struct clk *pll;
  20. struct clk *step;
  21. };
  22. static inline struct clk_cpu *to_clk_cpu(struct clk_hw *hw)
  23. {
  24. return container_of(hw, struct clk_cpu, hw);
  25. }
  26. static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
  27. unsigned long parent_rate)
  28. {
  29. struct clk_cpu *cpu = to_clk_cpu(hw);
  30. return clk_get_rate(cpu->div);
  31. }
  32. static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
  33. unsigned long *prate)
  34. {
  35. struct clk_cpu *cpu = to_clk_cpu(hw);
  36. return clk_round_rate(cpu->pll, rate);
  37. }
  38. static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
  39. unsigned long parent_rate)
  40. {
  41. struct clk_cpu *cpu = to_clk_cpu(hw);
  42. int ret;
  43. /* switch to PLL bypass clock */
  44. ret = clk_set_parent(cpu->mux, cpu->step);
  45. if (ret)
  46. return ret;
  47. /* reprogram PLL */
  48. ret = clk_set_rate(cpu->pll, rate);
  49. if (ret) {
  50. clk_set_parent(cpu->mux, cpu->pll);
  51. return ret;
  52. }
  53. /* switch back to PLL clock */
  54. clk_set_parent(cpu->mux, cpu->pll);
  55. /* Ensure the divider is what we expect */
  56. clk_set_rate(cpu->div, rate);
  57. return 0;
  58. }
  59. static const struct clk_ops clk_cpu_ops = {
  60. .recalc_rate = clk_cpu_recalc_rate,
  61. .round_rate = clk_cpu_round_rate,
  62. .set_rate = clk_cpu_set_rate,
  63. };
  64. struct clk *imx_clk_cpu(const char *name, const char *parent_name,
  65. struct clk *div, struct clk *mux, struct clk *pll,
  66. struct clk *step)
  67. {
  68. struct clk_cpu *cpu;
  69. struct clk *clk;
  70. struct clk_init_data init;
  71. cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
  72. if (!cpu)
  73. return ERR_PTR(-ENOMEM);
  74. cpu->div = div;
  75. cpu->mux = mux;
  76. cpu->pll = pll;
  77. cpu->step = step;
  78. init.name = name;
  79. init.ops = &clk_cpu_ops;
  80. init.flags = 0;
  81. init.parent_names = &parent_name;
  82. init.num_parents = 1;
  83. cpu->hw.init = &init;
  84. clk = clk_register(NULL, &cpu->hw);
  85. if (IS_ERR(clk))
  86. kfree(cpu);
  87. return clk;
  88. }