clk-div.c 2.6 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/clk-provider.h>
  12. #include <linux/err.h>
  13. #include <linux/slab.h>
  14. #include "clk.h"
  15. /**
  16. * struct clk_div - mxs integer divider clock
  17. * @divider: the parent class
  18. * @ops: pointer to clk_ops of parent class
  19. * @reg: register address
  20. * @busy: busy bit shift
  21. *
  22. * The mxs divider clock is a subclass of basic clk_divider with an
  23. * addtional busy bit.
  24. */
  25. struct clk_div {
  26. struct clk_divider divider;
  27. const struct clk_ops *ops;
  28. void __iomem *reg;
  29. u8 busy;
  30. };
  31. static inline struct clk_div *to_clk_div(struct clk_hw *hw)
  32. {
  33. struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
  34. return container_of(divider, struct clk_div, divider);
  35. }
  36. static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
  37. unsigned long parent_rate)
  38. {
  39. struct clk_div *div = to_clk_div(hw);
  40. return div->ops->recalc_rate(&div->divider.hw, parent_rate);
  41. }
  42. static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
  43. unsigned long *prate)
  44. {
  45. struct clk_div *div = to_clk_div(hw);
  46. return div->ops->round_rate(&div->divider.hw, rate, prate);
  47. }
  48. static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
  49. unsigned long parent_rate)
  50. {
  51. struct clk_div *div = to_clk_div(hw);
  52. int ret;
  53. ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
  54. if (!ret)
  55. ret = mxs_clk_wait(div->reg, div->busy);
  56. return ret;
  57. }
  58. static struct clk_ops clk_div_ops = {
  59. .recalc_rate = clk_div_recalc_rate,
  60. .round_rate = clk_div_round_rate,
  61. .set_rate = clk_div_set_rate,
  62. };
  63. struct clk *mxs_clk_div(const char *name, const char *parent_name,
  64. void __iomem *reg, u8 shift, u8 width, u8 busy)
  65. {
  66. struct clk_div *div;
  67. struct clk *clk;
  68. struct clk_init_data init;
  69. div = kzalloc(sizeof(*div), GFP_KERNEL);
  70. if (!div)
  71. return ERR_PTR(-ENOMEM);
  72. init.name = name;
  73. init.ops = &clk_div_ops;
  74. init.flags = CLK_SET_RATE_PARENT;
  75. init.parent_names = (parent_name ? &parent_name: NULL);
  76. init.num_parents = (parent_name ? 1 : 0);
  77. div->reg = reg;
  78. div->busy = busy;
  79. div->divider.reg = reg;
  80. div->divider.shift = shift;
  81. div->divider.width = width;
  82. div->divider.flags = CLK_DIVIDER_ONE_BASED;
  83. div->divider.lock = &mxs_lock;
  84. div->divider.hw.init = &init;
  85. div->ops = &clk_divider_ops;
  86. clk = clk_register(NULL, &div->divider.hw);
  87. if (IS_ERR(clk))
  88. kfree(div);
  89. return clk;
  90. }