clk.h 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #ifndef __MXS_CLK_H
  12. #define __MXS_CLK_H
  13. struct clk;
  14. #include <linux/clk-provider.h>
  15. #include <linux/spinlock.h>
  16. #define SET 0x4
  17. #define CLR 0x8
  18. extern spinlock_t mxs_lock;
  19. int mxs_clk_wait(void __iomem *reg, u8 shift);
  20. struct clk *mxs_clk_pll(const char *name, const char *parent_name,
  21. void __iomem *base, u8 power, unsigned long rate);
  22. struct clk *mxs_clk_ref(const char *name, const char *parent_name,
  23. void __iomem *reg, u8 idx);
  24. struct clk *mxs_clk_div(const char *name, const char *parent_name,
  25. void __iomem *reg, u8 shift, u8 width, u8 busy);
  26. struct clk *mxs_clk_frac(const char *name, const char *parent_name,
  27. void __iomem *reg, u8 shift, u8 width, u8 busy);
  28. static inline struct clk *mxs_clk_fixed(const char *name, int rate)
  29. {
  30. return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
  31. }
  32. static inline struct clk *mxs_clk_gate(const char *name,
  33. const char *parent_name, void __iomem *reg, u8 shift)
  34. {
  35. return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
  36. reg, shift, CLK_GATE_SET_TO_DISABLE,
  37. &mxs_lock);
  38. }
  39. static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
  40. u8 shift, u8 width, const char *const *parent_names, int num_parents)
  41. {
  42. return clk_register_mux(NULL, name, parent_names, num_parents,
  43. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  44. reg, shift, width, 0, &mxs_lock);
  45. }
  46. static inline struct clk *mxs_clk_fixed_factor(const char *name,
  47. const char *parent_name, unsigned int mult, unsigned int div)
  48. {
  49. return clk_register_fixed_factor(NULL, name, parent_name,
  50. CLK_SET_RATE_PARENT, mult, div);
  51. }
  52. #endif /* __MXS_CLK_H */