clk-pll.h 2.1 KB

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  1. /*
  2. * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef __QCOM_CLK_PLL_H__
  14. #define __QCOM_CLK_PLL_H__
  15. #include <linux/clk-provider.h>
  16. #include "clk-regmap.h"
  17. /**
  18. * struct pll_freq_tbl - PLL frequency table
  19. * @l: L value
  20. * @m: M value
  21. * @n: N value
  22. * @ibits: internal values
  23. */
  24. struct pll_freq_tbl {
  25. unsigned long freq;
  26. u16 l;
  27. u16 m;
  28. u16 n;
  29. u32 ibits;
  30. };
  31. /**
  32. * struct clk_pll - phase locked loop (PLL)
  33. * @l_reg: L register
  34. * @m_reg: M register
  35. * @n_reg: N register
  36. * @config_reg: config register
  37. * @mode_reg: mode register
  38. * @status_reg: status register
  39. * @status_bit: ANDed with @status_reg to determine if PLL is enabled
  40. * @freq_tbl: PLL frequency table
  41. * @hw: handle between common and hardware-specific interfaces
  42. */
  43. struct clk_pll {
  44. u32 l_reg;
  45. u32 m_reg;
  46. u32 n_reg;
  47. u32 config_reg;
  48. u32 mode_reg;
  49. u32 status_reg;
  50. u8 status_bit;
  51. u8 post_div_width;
  52. u8 post_div_shift;
  53. const struct pll_freq_tbl *freq_tbl;
  54. struct clk_regmap clkr;
  55. };
  56. extern const struct clk_ops clk_pll_ops;
  57. extern const struct clk_ops clk_pll_vote_ops;
  58. extern const struct clk_ops clk_pll_sr2_ops;
  59. #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
  60. struct pll_config {
  61. u16 l;
  62. u32 m;
  63. u32 n;
  64. u32 vco_val;
  65. u32 vco_mask;
  66. u32 pre_div_val;
  67. u32 pre_div_mask;
  68. u32 post_div_val;
  69. u32 post_div_mask;
  70. u32 mn_ena_mask;
  71. u32 main_output_mask;
  72. u32 aux_output_mask;
  73. };
  74. void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
  75. const struct pll_config *config, bool fsm_mode);
  76. void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
  77. const struct pll_config *config, bool fsm_mode);
  78. #endif