adf_sriov.c 9.5 KB

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  1. /*
  2. This file is provided under a dual BSD/GPLv2 license. When using or
  3. redistributing this file, you may do so under either license.
  4. GPL LICENSE SUMMARY
  5. Copyright(c) 2015 Intel Corporation.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of version 2 of the GNU General Public License as
  8. published by the Free Software Foundation.
  9. This program is distributed in the hope that it will be useful, but
  10. WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. General Public License for more details.
  13. Contact Information:
  14. qat-linux@intel.com
  15. BSD LICENSE
  16. Copyright(c) 2015 Intel Corporation.
  17. Redistribution and use in source and binary forms, with or without
  18. modification, are permitted provided that the following conditions
  19. are met:
  20. * Redistributions of source code must retain the above copyright
  21. notice, this list of conditions and the following disclaimer.
  22. * Redistributions in binary form must reproduce the above copyright
  23. notice, this list of conditions and the following disclaimer in
  24. the documentation and/or other materials provided with the
  25. distribution.
  26. * Neither the name of Intel Corporation nor the names of its
  27. contributors may be used to endorse or promote products derived
  28. from this software without specific prior written permission.
  29. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32. A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33. OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34. SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35. LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36. DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37. THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38. (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39. OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. */
  41. #include <linux/workqueue.h>
  42. #include <linux/pci.h>
  43. #include <linux/device.h>
  44. #include <linux/iommu.h>
  45. #include "adf_common_drv.h"
  46. #include "adf_cfg.h"
  47. #include "adf_pf2vf_msg.h"
  48. static struct workqueue_struct *pf2vf_resp_wq;
  49. #define ME2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
  50. #define ME2FUNCTION_MAP_A_NUM_REGS 96
  51. #define ME2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
  52. #define ME2FUNCTION_MAP_B_NUM_REGS 12
  53. #define ME2FUNCTION_MAP_REG_SIZE 4
  54. #define ME2FUNCTION_MAP_VALID BIT(7)
  55. #define READ_CSR_ME2FUNCTION_MAP_A(pmisc_bar_addr, index) \
  56. ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
  57. ME2FUNCTION_MAP_REG_SIZE * index)
  58. #define WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
  59. ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
  60. ME2FUNCTION_MAP_REG_SIZE * index, value)
  61. #define READ_CSR_ME2FUNCTION_MAP_B(pmisc_bar_addr, index) \
  62. ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
  63. ME2FUNCTION_MAP_REG_SIZE * index)
  64. #define WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
  65. ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
  66. ME2FUNCTION_MAP_REG_SIZE * index, value)
  67. struct adf_pf2vf_resp {
  68. struct work_struct pf2vf_resp_work;
  69. struct adf_accel_vf_info *vf_info;
  70. };
  71. static void adf_iov_send_resp(struct work_struct *work)
  72. {
  73. struct adf_pf2vf_resp *pf2vf_resp =
  74. container_of(work, struct adf_pf2vf_resp, pf2vf_resp_work);
  75. adf_vf2pf_req_hndl(pf2vf_resp->vf_info);
  76. kfree(pf2vf_resp);
  77. }
  78. static void adf_vf2pf_bh_handler(void *data)
  79. {
  80. struct adf_accel_vf_info *vf_info = (struct adf_accel_vf_info *)data;
  81. struct adf_pf2vf_resp *pf2vf_resp;
  82. pf2vf_resp = kzalloc(sizeof(*pf2vf_resp), GFP_ATOMIC);
  83. if (!pf2vf_resp)
  84. return;
  85. pf2vf_resp->vf_info = vf_info;
  86. INIT_WORK(&pf2vf_resp->pf2vf_resp_work, adf_iov_send_resp);
  87. queue_work(pf2vf_resp_wq, &pf2vf_resp->pf2vf_resp_work);
  88. }
  89. static int adf_enable_sriov(struct adf_accel_dev *accel_dev)
  90. {
  91. struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
  92. int totalvfs = pci_sriov_get_totalvfs(pdev);
  93. struct adf_hw_device_data *hw_data = accel_dev->hw_device;
  94. struct adf_bar *pmisc =
  95. &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
  96. void __iomem *pmisc_addr = pmisc->virt_addr;
  97. struct adf_accel_vf_info *vf_info;
  98. int i;
  99. u32 reg;
  100. for (i = 0, vf_info = accel_dev->pf.vf_info; i < totalvfs;
  101. i++, vf_info++) {
  102. /* This ptr will be populated when VFs will be created */
  103. vf_info->accel_dev = accel_dev;
  104. vf_info->vf_nr = i;
  105. tasklet_init(&vf_info->vf2pf_bh_tasklet,
  106. (void *)adf_vf2pf_bh_handler,
  107. (unsigned long)vf_info);
  108. mutex_init(&vf_info->pf2vf_lock);
  109. ratelimit_state_init(&vf_info->vf2pf_ratelimit,
  110. DEFAULT_RATELIMIT_INTERVAL,
  111. DEFAULT_RATELIMIT_BURST);
  112. }
  113. /* Set Valid bits in ME Thread to PCIe Function Mapping Group A */
  114. for (i = 0; i < ME2FUNCTION_MAP_A_NUM_REGS; i++) {
  115. reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i);
  116. reg |= ME2FUNCTION_MAP_VALID;
  117. WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg);
  118. }
  119. /* Set Valid bits in ME Thread to PCIe Function Mapping Group B */
  120. for (i = 0; i < ME2FUNCTION_MAP_B_NUM_REGS; i++) {
  121. reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i);
  122. reg |= ME2FUNCTION_MAP_VALID;
  123. WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg);
  124. }
  125. /* Enable VF to PF interrupts for all VFs */
  126. adf_enable_vf2pf_interrupts(accel_dev, GENMASK_ULL(totalvfs - 1, 0));
  127. /*
  128. * Due to the hardware design, when SR-IOV and the ring arbiter
  129. * are enabled all the VFs supported in hardware must be enabled in
  130. * order for all the hardware resources (i.e. bundles) to be usable.
  131. * When SR-IOV is enabled, each of the VFs will own one bundle.
  132. */
  133. return pci_enable_sriov(pdev, totalvfs);
  134. }
  135. /**
  136. * adf_disable_sriov() - Disable SRIOV for the device
  137. * @pdev: Pointer to pci device.
  138. *
  139. * Function disables SRIOV for the pci device.
  140. *
  141. * Return: 0 on success, error code otherwise.
  142. */
  143. void adf_disable_sriov(struct adf_accel_dev *accel_dev)
  144. {
  145. struct adf_hw_device_data *hw_data = accel_dev->hw_device;
  146. struct adf_bar *pmisc =
  147. &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)];
  148. void __iomem *pmisc_addr = pmisc->virt_addr;
  149. int totalvfs = pci_sriov_get_totalvfs(accel_to_pci_dev(accel_dev));
  150. struct adf_accel_vf_info *vf;
  151. u32 reg;
  152. int i;
  153. if (!accel_dev->pf.vf_info)
  154. return;
  155. adf_pf2vf_notify_restarting(accel_dev);
  156. pci_disable_sriov(accel_to_pci_dev(accel_dev));
  157. /* Disable VF to PF interrupts */
  158. adf_disable_vf2pf_interrupts(accel_dev, 0xFFFFFFFF);
  159. /* Clear Valid bits in ME Thread to PCIe Function Mapping Group A */
  160. for (i = 0; i < ME2FUNCTION_MAP_A_NUM_REGS; i++) {
  161. reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i);
  162. reg &= ~ME2FUNCTION_MAP_VALID;
  163. WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg);
  164. }
  165. /* Clear Valid bits in ME Thread to PCIe Function Mapping Group B */
  166. for (i = 0; i < ME2FUNCTION_MAP_B_NUM_REGS; i++) {
  167. reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i);
  168. reg &= ~ME2FUNCTION_MAP_VALID;
  169. WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg);
  170. }
  171. for (i = 0, vf = accel_dev->pf.vf_info; i < totalvfs; i++, vf++) {
  172. tasklet_disable(&vf->vf2pf_bh_tasklet);
  173. tasklet_kill(&vf->vf2pf_bh_tasklet);
  174. mutex_destroy(&vf->pf2vf_lock);
  175. }
  176. kfree(accel_dev->pf.vf_info);
  177. accel_dev->pf.vf_info = NULL;
  178. }
  179. EXPORT_SYMBOL_GPL(adf_disable_sriov);
  180. /**
  181. * adf_sriov_configure() - Enable SRIOV for the device
  182. * @pdev: Pointer to pci device.
  183. *
  184. * Function enables SRIOV for the pci device.
  185. *
  186. * Return: 0 on success, error code otherwise.
  187. */
  188. int adf_sriov_configure(struct pci_dev *pdev, int numvfs)
  189. {
  190. struct adf_accel_dev *accel_dev = adf_devmgr_pci_to_accel_dev(pdev);
  191. int totalvfs = pci_sriov_get_totalvfs(pdev);
  192. unsigned long val;
  193. int ret;
  194. if (!accel_dev) {
  195. dev_err(&pdev->dev, "Failed to find accel_dev\n");
  196. return -EFAULT;
  197. }
  198. if (!iommu_present(&pci_bus_type))
  199. dev_warn(&pdev->dev, "IOMMU should be enabled for SR-IOV to work correctly\n");
  200. if (accel_dev->pf.vf_info) {
  201. dev_info(&pdev->dev, "Already enabled for this device\n");
  202. return -EINVAL;
  203. }
  204. if (adf_dev_started(accel_dev)) {
  205. if (adf_devmgr_in_reset(accel_dev) ||
  206. adf_dev_in_use(accel_dev)) {
  207. dev_err(&GET_DEV(accel_dev), "Device busy\n");
  208. return -EBUSY;
  209. }
  210. if (adf_dev_stop(accel_dev)) {
  211. dev_err(&GET_DEV(accel_dev),
  212. "Failed to stop qat_dev%d\n",
  213. accel_dev->accel_id);
  214. return -EFAULT;
  215. }
  216. adf_dev_shutdown(accel_dev);
  217. }
  218. if (adf_cfg_section_add(accel_dev, ADF_KERNEL_SEC))
  219. return -EFAULT;
  220. val = 0;
  221. if (adf_cfg_add_key_value_param(accel_dev, ADF_KERNEL_SEC,
  222. ADF_NUM_CY, (void *)&val, ADF_DEC))
  223. return -EFAULT;
  224. set_bit(ADF_STATUS_CONFIGURED, &accel_dev->status);
  225. /* Allocate memory for VF info structs */
  226. accel_dev->pf.vf_info = kcalloc(totalvfs,
  227. sizeof(struct adf_accel_vf_info),
  228. GFP_KERNEL);
  229. if (!accel_dev->pf.vf_info)
  230. return -ENOMEM;
  231. if (adf_dev_init(accel_dev)) {
  232. dev_err(&GET_DEV(accel_dev), "Failed to init qat_dev%d\n",
  233. accel_dev->accel_id);
  234. return -EFAULT;
  235. }
  236. if (adf_dev_start(accel_dev)) {
  237. dev_err(&GET_DEV(accel_dev), "Failed to start qat_dev%d\n",
  238. accel_dev->accel_id);
  239. return -EFAULT;
  240. }
  241. ret = adf_enable_sriov(accel_dev);
  242. if (ret)
  243. return ret;
  244. return numvfs;
  245. }
  246. EXPORT_SYMBOL_GPL(adf_sriov_configure);
  247. int __init adf_init_pf_wq(void)
  248. {
  249. /* Workqueue for PF2VF responses */
  250. pf2vf_resp_wq = create_workqueue("qat_pf2vf_resp_wq");
  251. return !pf2vf_resp_wq ? -ENOMEM : 0;
  252. }
  253. void adf_exit_pf_wq(void)
  254. {
  255. if (pf2vf_resp_wq) {
  256. destroy_workqueue(pf2vf_resp_wq);
  257. pf2vf_resp_wq = NULL;
  258. }
  259. }