edac_mc_sysfs.c 27 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012-2013 - Mauro Carvalho Chehab
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. unsigned long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = kstrtoul(val, 0, &l);
  52. if (ret)
  53. return ret;
  54. if (l < 1000)
  55. return -EINVAL;
  56. *((unsigned long *)kp->arg) = l;
  57. /* notify edac_mc engine to reset the poll period */
  58. edac_mc_reset_delay_period(l);
  59. return 0;
  60. }
  61. /* Parameter declarations for above */
  62. module_param(edac_mc_panic_on_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  64. module_param(edac_mc_log_ue, int, 0644);
  65. MODULE_PARM_DESC(edac_mc_log_ue,
  66. "Log uncorrectable error to console: 0=off 1=on");
  67. module_param(edac_mc_log_ce, int, 0644);
  68. MODULE_PARM_DESC(edac_mc_log_ce,
  69. "Log correctable error to console: 0=off 1=on");
  70. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  71. &edac_mc_poll_msec, 0644);
  72. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  73. static struct device *mci_pdev;
  74. /*
  75. * various constants for Memory Controllers
  76. */
  77. static const char * const mem_types[] = {
  78. [MEM_EMPTY] = "Empty",
  79. [MEM_RESERVED] = "Reserved",
  80. [MEM_UNKNOWN] = "Unknown",
  81. [MEM_FPM] = "FPM",
  82. [MEM_EDO] = "EDO",
  83. [MEM_BEDO] = "BEDO",
  84. [MEM_SDR] = "Unbuffered-SDR",
  85. [MEM_RDR] = "Registered-SDR",
  86. [MEM_DDR] = "Unbuffered-DDR",
  87. [MEM_RDDR] = "Registered-DDR",
  88. [MEM_RMBS] = "RMBS",
  89. [MEM_DDR2] = "Unbuffered-DDR2",
  90. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  91. [MEM_RDDR2] = "Registered-DDR2",
  92. [MEM_XDR] = "XDR",
  93. [MEM_DDR3] = "Unbuffered-DDR3",
  94. [MEM_RDDR3] = "Registered-DDR3",
  95. [MEM_DDR4] = "Unbuffered-DDR4",
  96. [MEM_RDDR4] = "Registered-DDR4"
  97. };
  98. static const char * const dev_types[] = {
  99. [DEV_UNKNOWN] = "Unknown",
  100. [DEV_X1] = "x1",
  101. [DEV_X2] = "x2",
  102. [DEV_X4] = "x4",
  103. [DEV_X8] = "x8",
  104. [DEV_X16] = "x16",
  105. [DEV_X32] = "x32",
  106. [DEV_X64] = "x64"
  107. };
  108. static const char * const edac_caps[] = {
  109. [EDAC_UNKNOWN] = "Unknown",
  110. [EDAC_NONE] = "None",
  111. [EDAC_RESERVED] = "Reserved",
  112. [EDAC_PARITY] = "PARITY",
  113. [EDAC_EC] = "EC",
  114. [EDAC_SECDED] = "SECDED",
  115. [EDAC_S2ECD2ED] = "S2ECD2ED",
  116. [EDAC_S4ECD4ED] = "S4ECD4ED",
  117. [EDAC_S8ECD8ED] = "S8ECD8ED",
  118. [EDAC_S16ECD16ED] = "S16ECD16ED"
  119. };
  120. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  121. /*
  122. * EDAC sysfs CSROW data structures and methods
  123. */
  124. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  125. /*
  126. * We need it to avoid namespace conflicts between the legacy API
  127. * and the per-dimm/per-rank one
  128. */
  129. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  130. static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  131. struct dev_ch_attribute {
  132. struct device_attribute attr;
  133. int channel;
  134. };
  135. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  136. static struct dev_ch_attribute dev_attr_legacy_##_name = \
  137. { __ATTR(_name, _mode, _show, _store), (_var) }
  138. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  139. /* Set of more default csrow<id> attribute show/store functions */
  140. static ssize_t csrow_ue_count_show(struct device *dev,
  141. struct device_attribute *mattr, char *data)
  142. {
  143. struct csrow_info *csrow = to_csrow(dev);
  144. return sprintf(data, "%u\n", csrow->ue_count);
  145. }
  146. static ssize_t csrow_ce_count_show(struct device *dev,
  147. struct device_attribute *mattr, char *data)
  148. {
  149. struct csrow_info *csrow = to_csrow(dev);
  150. return sprintf(data, "%u\n", csrow->ce_count);
  151. }
  152. static ssize_t csrow_size_show(struct device *dev,
  153. struct device_attribute *mattr, char *data)
  154. {
  155. struct csrow_info *csrow = to_csrow(dev);
  156. int i;
  157. u32 nr_pages = 0;
  158. for (i = 0; i < csrow->nr_channels; i++)
  159. nr_pages += csrow->channels[i]->dimm->nr_pages;
  160. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  161. }
  162. static ssize_t csrow_mem_type_show(struct device *dev,
  163. struct device_attribute *mattr, char *data)
  164. {
  165. struct csrow_info *csrow = to_csrow(dev);
  166. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  167. }
  168. static ssize_t csrow_dev_type_show(struct device *dev,
  169. struct device_attribute *mattr, char *data)
  170. {
  171. struct csrow_info *csrow = to_csrow(dev);
  172. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  173. }
  174. static ssize_t csrow_edac_mode_show(struct device *dev,
  175. struct device_attribute *mattr,
  176. char *data)
  177. {
  178. struct csrow_info *csrow = to_csrow(dev);
  179. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  180. }
  181. /* show/store functions for DIMM Label attributes */
  182. static ssize_t channel_dimm_label_show(struct device *dev,
  183. struct device_attribute *mattr,
  184. char *data)
  185. {
  186. struct csrow_info *csrow = to_csrow(dev);
  187. unsigned chan = to_channel(mattr);
  188. struct rank_info *rank = csrow->channels[chan];
  189. /* if field has not been initialized, there is nothing to send */
  190. if (!rank->dimm->label[0])
  191. return 0;
  192. return snprintf(data, sizeof(rank->dimm->label) + 1, "%s\n",
  193. rank->dimm->label);
  194. }
  195. static ssize_t channel_dimm_label_store(struct device *dev,
  196. struct device_attribute *mattr,
  197. const char *data, size_t count)
  198. {
  199. struct csrow_info *csrow = to_csrow(dev);
  200. unsigned chan = to_channel(mattr);
  201. struct rank_info *rank = csrow->channels[chan];
  202. size_t copy_count = count;
  203. if (count == 0)
  204. return -EINVAL;
  205. if (data[count - 1] == '\0' || data[count - 1] == '\n')
  206. copy_count -= 1;
  207. if (copy_count == 0 || copy_count >= sizeof(rank->dimm->label))
  208. return -EINVAL;
  209. strncpy(rank->dimm->label, data, copy_count);
  210. rank->dimm->label[copy_count] = '\0';
  211. return count;
  212. }
  213. /* show function for dynamic chX_ce_count attribute */
  214. static ssize_t channel_ce_count_show(struct device *dev,
  215. struct device_attribute *mattr, char *data)
  216. {
  217. struct csrow_info *csrow = to_csrow(dev);
  218. unsigned chan = to_channel(mattr);
  219. struct rank_info *rank = csrow->channels[chan];
  220. return sprintf(data, "%u\n", rank->ce_count);
  221. }
  222. /* cwrow<id>/attribute files */
  223. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  224. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  225. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  226. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  227. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  228. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  229. /* default attributes of the CSROW<id> object */
  230. static struct attribute *csrow_attrs[] = {
  231. &dev_attr_legacy_dev_type.attr,
  232. &dev_attr_legacy_mem_type.attr,
  233. &dev_attr_legacy_edac_mode.attr,
  234. &dev_attr_legacy_size_mb.attr,
  235. &dev_attr_legacy_ue_count.attr,
  236. &dev_attr_legacy_ce_count.attr,
  237. NULL,
  238. };
  239. static struct attribute_group csrow_attr_grp = {
  240. .attrs = csrow_attrs,
  241. };
  242. static const struct attribute_group *csrow_attr_groups[] = {
  243. &csrow_attr_grp,
  244. NULL
  245. };
  246. static void csrow_attr_release(struct device *dev)
  247. {
  248. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  249. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  250. kfree(csrow);
  251. }
  252. static struct device_type csrow_attr_type = {
  253. .groups = csrow_attr_groups,
  254. .release = csrow_attr_release,
  255. };
  256. /*
  257. * possible dynamic channel DIMM Label attribute files
  258. *
  259. */
  260. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 0);
  262. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 1);
  264. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 2);
  266. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  267. channel_dimm_label_show, channel_dimm_label_store, 3);
  268. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  269. channel_dimm_label_show, channel_dimm_label_store, 4);
  270. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  271. channel_dimm_label_show, channel_dimm_label_store, 5);
  272. DEVICE_CHANNEL(ch6_dimm_label, S_IRUGO | S_IWUSR,
  273. channel_dimm_label_show, channel_dimm_label_store, 6);
  274. DEVICE_CHANNEL(ch7_dimm_label, S_IRUGO | S_IWUSR,
  275. channel_dimm_label_show, channel_dimm_label_store, 7);
  276. /* Total possible dynamic DIMM Label attribute file table */
  277. static struct attribute *dynamic_csrow_dimm_attr[] = {
  278. &dev_attr_legacy_ch0_dimm_label.attr.attr,
  279. &dev_attr_legacy_ch1_dimm_label.attr.attr,
  280. &dev_attr_legacy_ch2_dimm_label.attr.attr,
  281. &dev_attr_legacy_ch3_dimm_label.attr.attr,
  282. &dev_attr_legacy_ch4_dimm_label.attr.attr,
  283. &dev_attr_legacy_ch5_dimm_label.attr.attr,
  284. &dev_attr_legacy_ch6_dimm_label.attr.attr,
  285. &dev_attr_legacy_ch7_dimm_label.attr.attr,
  286. NULL
  287. };
  288. /* possible dynamic channel ce_count attribute files */
  289. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
  290. channel_ce_count_show, NULL, 0);
  291. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
  292. channel_ce_count_show, NULL, 1);
  293. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
  294. channel_ce_count_show, NULL, 2);
  295. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
  296. channel_ce_count_show, NULL, 3);
  297. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
  298. channel_ce_count_show, NULL, 4);
  299. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
  300. channel_ce_count_show, NULL, 5);
  301. DEVICE_CHANNEL(ch6_ce_count, S_IRUGO,
  302. channel_ce_count_show, NULL, 6);
  303. DEVICE_CHANNEL(ch7_ce_count, S_IRUGO,
  304. channel_ce_count_show, NULL, 7);
  305. /* Total possible dynamic ce_count attribute file table */
  306. static struct attribute *dynamic_csrow_ce_count_attr[] = {
  307. &dev_attr_legacy_ch0_ce_count.attr.attr,
  308. &dev_attr_legacy_ch1_ce_count.attr.attr,
  309. &dev_attr_legacy_ch2_ce_count.attr.attr,
  310. &dev_attr_legacy_ch3_ce_count.attr.attr,
  311. &dev_attr_legacy_ch4_ce_count.attr.attr,
  312. &dev_attr_legacy_ch5_ce_count.attr.attr,
  313. &dev_attr_legacy_ch6_ce_count.attr.attr,
  314. &dev_attr_legacy_ch7_ce_count.attr.attr,
  315. NULL
  316. };
  317. static umode_t csrow_dev_is_visible(struct kobject *kobj,
  318. struct attribute *attr, int idx)
  319. {
  320. struct device *dev = kobj_to_dev(kobj);
  321. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  322. if (idx >= csrow->nr_channels)
  323. return 0;
  324. if (idx >= ARRAY_SIZE(dynamic_csrow_ce_count_attr) - 1) {
  325. WARN_ONCE(1, "idx: %d\n", idx);
  326. return 0;
  327. }
  328. /* Only expose populated DIMMs */
  329. if (!csrow->channels[idx]->dimm->nr_pages)
  330. return 0;
  331. return attr->mode;
  332. }
  333. static const struct attribute_group csrow_dev_dimm_group = {
  334. .attrs = dynamic_csrow_dimm_attr,
  335. .is_visible = csrow_dev_is_visible,
  336. };
  337. static const struct attribute_group csrow_dev_ce_count_group = {
  338. .attrs = dynamic_csrow_ce_count_attr,
  339. .is_visible = csrow_dev_is_visible,
  340. };
  341. static const struct attribute_group *csrow_dev_groups[] = {
  342. &csrow_dev_dimm_group,
  343. &csrow_dev_ce_count_group,
  344. NULL
  345. };
  346. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  347. {
  348. int chan, nr_pages = 0;
  349. for (chan = 0; chan < csrow->nr_channels; chan++)
  350. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  351. return nr_pages;
  352. }
  353. /* Create a CSROW object under specifed edac_mc_device */
  354. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  355. struct csrow_info *csrow, int index)
  356. {
  357. csrow->dev.type = &csrow_attr_type;
  358. csrow->dev.bus = mci->bus;
  359. csrow->dev.groups = csrow_dev_groups;
  360. device_initialize(&csrow->dev);
  361. csrow->dev.parent = &mci->dev;
  362. csrow->mci = mci;
  363. dev_set_name(&csrow->dev, "csrow%d", index);
  364. dev_set_drvdata(&csrow->dev, csrow);
  365. edac_dbg(0, "creating (virtual) csrow node %s\n",
  366. dev_name(&csrow->dev));
  367. return device_add(&csrow->dev);
  368. }
  369. /* Create a CSROW object under specifed edac_mc_device */
  370. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  371. {
  372. int err, i;
  373. struct csrow_info *csrow;
  374. for (i = 0; i < mci->nr_csrows; i++) {
  375. csrow = mci->csrows[i];
  376. if (!nr_pages_per_csrow(csrow))
  377. continue;
  378. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  379. if (err < 0) {
  380. edac_dbg(1,
  381. "failure: create csrow objects for csrow %d\n",
  382. i);
  383. goto error;
  384. }
  385. }
  386. return 0;
  387. error:
  388. for (--i; i >= 0; i--) {
  389. csrow = mci->csrows[i];
  390. if (!nr_pages_per_csrow(csrow))
  391. continue;
  392. put_device(&mci->csrows[i]->dev);
  393. }
  394. return err;
  395. }
  396. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  397. {
  398. int i;
  399. struct csrow_info *csrow;
  400. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  401. csrow = mci->csrows[i];
  402. if (!nr_pages_per_csrow(csrow))
  403. continue;
  404. device_unregister(&mci->csrows[i]->dev);
  405. }
  406. }
  407. #endif
  408. /*
  409. * Per-dimm (or per-rank) devices
  410. */
  411. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  412. /* show/store functions for DIMM Label attributes */
  413. static ssize_t dimmdev_location_show(struct device *dev,
  414. struct device_attribute *mattr, char *data)
  415. {
  416. struct dimm_info *dimm = to_dimm(dev);
  417. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  418. }
  419. static ssize_t dimmdev_label_show(struct device *dev,
  420. struct device_attribute *mattr, char *data)
  421. {
  422. struct dimm_info *dimm = to_dimm(dev);
  423. /* if field has not been initialized, there is nothing to send */
  424. if (!dimm->label[0])
  425. return 0;
  426. return snprintf(data, sizeof(dimm->label) + 1, "%s\n", dimm->label);
  427. }
  428. static ssize_t dimmdev_label_store(struct device *dev,
  429. struct device_attribute *mattr,
  430. const char *data,
  431. size_t count)
  432. {
  433. struct dimm_info *dimm = to_dimm(dev);
  434. size_t copy_count = count;
  435. if (count == 0)
  436. return -EINVAL;
  437. if (data[count - 1] == '\0' || data[count - 1] == '\n')
  438. copy_count -= 1;
  439. if (copy_count == 0 || copy_count >= sizeof(dimm->label))
  440. return -EINVAL;
  441. strncpy(dimm->label, data, copy_count);
  442. dimm->label[copy_count] = '\0';
  443. return count;
  444. }
  445. static ssize_t dimmdev_size_show(struct device *dev,
  446. struct device_attribute *mattr, char *data)
  447. {
  448. struct dimm_info *dimm = to_dimm(dev);
  449. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  450. }
  451. static ssize_t dimmdev_mem_type_show(struct device *dev,
  452. struct device_attribute *mattr, char *data)
  453. {
  454. struct dimm_info *dimm = to_dimm(dev);
  455. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  456. }
  457. static ssize_t dimmdev_dev_type_show(struct device *dev,
  458. struct device_attribute *mattr, char *data)
  459. {
  460. struct dimm_info *dimm = to_dimm(dev);
  461. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  462. }
  463. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  464. struct device_attribute *mattr,
  465. char *data)
  466. {
  467. struct dimm_info *dimm = to_dimm(dev);
  468. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  469. }
  470. /* dimm/rank attribute files */
  471. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  472. dimmdev_label_show, dimmdev_label_store);
  473. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  474. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  475. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  476. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  477. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  478. /* attributes of the dimm<id>/rank<id> object */
  479. static struct attribute *dimm_attrs[] = {
  480. &dev_attr_dimm_label.attr,
  481. &dev_attr_dimm_location.attr,
  482. &dev_attr_size.attr,
  483. &dev_attr_dimm_mem_type.attr,
  484. &dev_attr_dimm_dev_type.attr,
  485. &dev_attr_dimm_edac_mode.attr,
  486. NULL,
  487. };
  488. static struct attribute_group dimm_attr_grp = {
  489. .attrs = dimm_attrs,
  490. };
  491. static const struct attribute_group *dimm_attr_groups[] = {
  492. &dimm_attr_grp,
  493. NULL
  494. };
  495. static void dimm_attr_release(struct device *dev)
  496. {
  497. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  498. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  499. kfree(dimm);
  500. }
  501. static struct device_type dimm_attr_type = {
  502. .groups = dimm_attr_groups,
  503. .release = dimm_attr_release,
  504. };
  505. /* Create a DIMM object under specifed memory controller device */
  506. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  507. struct dimm_info *dimm,
  508. int index)
  509. {
  510. int err;
  511. dimm->mci = mci;
  512. dimm->dev.type = &dimm_attr_type;
  513. dimm->dev.bus = mci->bus;
  514. device_initialize(&dimm->dev);
  515. dimm->dev.parent = &mci->dev;
  516. if (mci->csbased)
  517. dev_set_name(&dimm->dev, "rank%d", index);
  518. else
  519. dev_set_name(&dimm->dev, "dimm%d", index);
  520. dev_set_drvdata(&dimm->dev, dimm);
  521. pm_runtime_forbid(&mci->dev);
  522. err = device_add(&dimm->dev);
  523. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  524. return err;
  525. }
  526. /*
  527. * Memory controller device
  528. */
  529. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  530. static ssize_t mci_reset_counters_store(struct device *dev,
  531. struct device_attribute *mattr,
  532. const char *data, size_t count)
  533. {
  534. struct mem_ctl_info *mci = to_mci(dev);
  535. int cnt, row, chan, i;
  536. mci->ue_mc = 0;
  537. mci->ce_mc = 0;
  538. mci->ue_noinfo_count = 0;
  539. mci->ce_noinfo_count = 0;
  540. for (row = 0; row < mci->nr_csrows; row++) {
  541. struct csrow_info *ri = mci->csrows[row];
  542. ri->ue_count = 0;
  543. ri->ce_count = 0;
  544. for (chan = 0; chan < ri->nr_channels; chan++)
  545. ri->channels[chan]->ce_count = 0;
  546. }
  547. cnt = 1;
  548. for (i = 0; i < mci->n_layers; i++) {
  549. cnt *= mci->layers[i].size;
  550. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  551. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  552. }
  553. mci->start_time = jiffies;
  554. return count;
  555. }
  556. /* Memory scrubbing interface:
  557. *
  558. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  559. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  560. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  561. *
  562. * Negative value still means that an error has occurred while setting
  563. * the scrub rate.
  564. */
  565. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  566. struct device_attribute *mattr,
  567. const char *data, size_t count)
  568. {
  569. struct mem_ctl_info *mci = to_mci(dev);
  570. unsigned long bandwidth = 0;
  571. int new_bw = 0;
  572. if (kstrtoul(data, 10, &bandwidth) < 0)
  573. return -EINVAL;
  574. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  575. if (new_bw < 0) {
  576. edac_printk(KERN_WARNING, EDAC_MC,
  577. "Error setting scrub rate to: %lu\n", bandwidth);
  578. return -EINVAL;
  579. }
  580. return count;
  581. }
  582. /*
  583. * ->get_sdram_scrub_rate() return value semantics same as above.
  584. */
  585. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  586. struct device_attribute *mattr,
  587. char *data)
  588. {
  589. struct mem_ctl_info *mci = to_mci(dev);
  590. int bandwidth = 0;
  591. bandwidth = mci->get_sdram_scrub_rate(mci);
  592. if (bandwidth < 0) {
  593. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  594. return bandwidth;
  595. }
  596. return sprintf(data, "%d\n", bandwidth);
  597. }
  598. /* default attribute files for the MCI object */
  599. static ssize_t mci_ue_count_show(struct device *dev,
  600. struct device_attribute *mattr,
  601. char *data)
  602. {
  603. struct mem_ctl_info *mci = to_mci(dev);
  604. return sprintf(data, "%d\n", mci->ue_mc);
  605. }
  606. static ssize_t mci_ce_count_show(struct device *dev,
  607. struct device_attribute *mattr,
  608. char *data)
  609. {
  610. struct mem_ctl_info *mci = to_mci(dev);
  611. return sprintf(data, "%d\n", mci->ce_mc);
  612. }
  613. static ssize_t mci_ce_noinfo_show(struct device *dev,
  614. struct device_attribute *mattr,
  615. char *data)
  616. {
  617. struct mem_ctl_info *mci = to_mci(dev);
  618. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  619. }
  620. static ssize_t mci_ue_noinfo_show(struct device *dev,
  621. struct device_attribute *mattr,
  622. char *data)
  623. {
  624. struct mem_ctl_info *mci = to_mci(dev);
  625. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  626. }
  627. static ssize_t mci_seconds_show(struct device *dev,
  628. struct device_attribute *mattr,
  629. char *data)
  630. {
  631. struct mem_ctl_info *mci = to_mci(dev);
  632. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  633. }
  634. static ssize_t mci_ctl_name_show(struct device *dev,
  635. struct device_attribute *mattr,
  636. char *data)
  637. {
  638. struct mem_ctl_info *mci = to_mci(dev);
  639. return sprintf(data, "%s\n", mci->ctl_name);
  640. }
  641. static ssize_t mci_size_mb_show(struct device *dev,
  642. struct device_attribute *mattr,
  643. char *data)
  644. {
  645. struct mem_ctl_info *mci = to_mci(dev);
  646. int total_pages = 0, csrow_idx, j;
  647. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  648. struct csrow_info *csrow = mci->csrows[csrow_idx];
  649. for (j = 0; j < csrow->nr_channels; j++) {
  650. struct dimm_info *dimm = csrow->channels[j]->dimm;
  651. total_pages += dimm->nr_pages;
  652. }
  653. }
  654. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  655. }
  656. static ssize_t mci_max_location_show(struct device *dev,
  657. struct device_attribute *mattr,
  658. char *data)
  659. {
  660. struct mem_ctl_info *mci = to_mci(dev);
  661. int i;
  662. char *p = data;
  663. for (i = 0; i < mci->n_layers; i++) {
  664. p += sprintf(p, "%s %d ",
  665. edac_layer_name[mci->layers[i].type],
  666. mci->layers[i].size - 1);
  667. }
  668. return p - data;
  669. }
  670. /* default Control file */
  671. static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  672. /* default Attribute files */
  673. static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  674. static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  675. static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  676. static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  677. static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  678. static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  679. static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  680. static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  681. /* memory scrubber attribute file */
  682. DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show,
  683. mci_sdram_scrub_rate_store); /* umode set later in is_visible */
  684. static struct attribute *mci_attrs[] = {
  685. &dev_attr_reset_counters.attr,
  686. &dev_attr_mc_name.attr,
  687. &dev_attr_size_mb.attr,
  688. &dev_attr_seconds_since_reset.attr,
  689. &dev_attr_ue_noinfo_count.attr,
  690. &dev_attr_ce_noinfo_count.attr,
  691. &dev_attr_ue_count.attr,
  692. &dev_attr_ce_count.attr,
  693. &dev_attr_max_location.attr,
  694. &dev_attr_sdram_scrub_rate.attr,
  695. NULL
  696. };
  697. static umode_t mci_attr_is_visible(struct kobject *kobj,
  698. struct attribute *attr, int idx)
  699. {
  700. struct device *dev = kobj_to_dev(kobj);
  701. struct mem_ctl_info *mci = to_mci(dev);
  702. umode_t mode = 0;
  703. if (attr != &dev_attr_sdram_scrub_rate.attr)
  704. return attr->mode;
  705. if (mci->get_sdram_scrub_rate)
  706. mode |= S_IRUGO;
  707. if (mci->set_sdram_scrub_rate)
  708. mode |= S_IWUSR;
  709. return mode;
  710. }
  711. static struct attribute_group mci_attr_grp = {
  712. .attrs = mci_attrs,
  713. .is_visible = mci_attr_is_visible,
  714. };
  715. static const struct attribute_group *mci_attr_groups[] = {
  716. &mci_attr_grp,
  717. NULL
  718. };
  719. static void mci_attr_release(struct device *dev)
  720. {
  721. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  722. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  723. kfree(mci);
  724. }
  725. static struct device_type mci_attr_type = {
  726. .groups = mci_attr_groups,
  727. .release = mci_attr_release,
  728. };
  729. /*
  730. * Create a new Memory Controller kobject instance,
  731. * mc<id> under the 'mc' directory
  732. *
  733. * Return:
  734. * 0 Success
  735. * !0 Failure
  736. */
  737. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci,
  738. const struct attribute_group **groups)
  739. {
  740. char *name;
  741. int i, err;
  742. /*
  743. * The memory controller needs its own bus, in order to avoid
  744. * namespace conflicts at /sys/bus/edac.
  745. */
  746. name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  747. if (!name)
  748. return -ENOMEM;
  749. mci->bus->name = name;
  750. edac_dbg(0, "creating bus %s\n", mci->bus->name);
  751. err = bus_register(mci->bus);
  752. if (err < 0) {
  753. kfree(name);
  754. return err;
  755. }
  756. /* get the /sys/devices/system/edac subsys reference */
  757. mci->dev.type = &mci_attr_type;
  758. device_initialize(&mci->dev);
  759. mci->dev.parent = mci_pdev;
  760. mci->dev.bus = mci->bus;
  761. mci->dev.groups = groups;
  762. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  763. dev_set_drvdata(&mci->dev, mci);
  764. pm_runtime_forbid(&mci->dev);
  765. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  766. err = device_add(&mci->dev);
  767. if (err < 0) {
  768. edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
  769. goto fail_unregister_bus;
  770. }
  771. /*
  772. * Create the dimm/rank devices
  773. */
  774. for (i = 0; i < mci->tot_dimms; i++) {
  775. struct dimm_info *dimm = mci->dimms[i];
  776. /* Only expose populated DIMMs */
  777. if (!dimm->nr_pages)
  778. continue;
  779. #ifdef CONFIG_EDAC_DEBUG
  780. edac_dbg(1, "creating dimm%d, located at ", i);
  781. if (edac_debug_level >= 1) {
  782. int lay;
  783. for (lay = 0; lay < mci->n_layers; lay++)
  784. printk(KERN_CONT "%s %d ",
  785. edac_layer_name[mci->layers[lay].type],
  786. dimm->location[lay]);
  787. printk(KERN_CONT "\n");
  788. }
  789. #endif
  790. err = edac_create_dimm_object(mci, dimm, i);
  791. if (err) {
  792. edac_dbg(1, "failure: create dimm %d obj\n", i);
  793. goto fail_unregister_dimm;
  794. }
  795. }
  796. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  797. err = edac_create_csrow_objects(mci);
  798. if (err < 0)
  799. goto fail_unregister_dimm;
  800. #endif
  801. edac_create_debugfs_nodes(mci);
  802. return 0;
  803. fail_unregister_dimm:
  804. for (i--; i >= 0; i--) {
  805. struct dimm_info *dimm = mci->dimms[i];
  806. if (!dimm->nr_pages)
  807. continue;
  808. device_unregister(&dimm->dev);
  809. }
  810. device_unregister(&mci->dev);
  811. fail_unregister_bus:
  812. bus_unregister(mci->bus);
  813. kfree(name);
  814. return err;
  815. }
  816. /*
  817. * remove a Memory Controller instance
  818. */
  819. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  820. {
  821. int i;
  822. edac_dbg(0, "\n");
  823. #ifdef CONFIG_EDAC_DEBUG
  824. edac_debugfs_remove_recursive(mci->debugfs);
  825. #endif
  826. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  827. edac_delete_csrow_objects(mci);
  828. #endif
  829. for (i = 0; i < mci->tot_dimms; i++) {
  830. struct dimm_info *dimm = mci->dimms[i];
  831. if (dimm->nr_pages == 0)
  832. continue;
  833. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  834. device_unregister(&dimm->dev);
  835. }
  836. }
  837. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  838. {
  839. const char *name = mci->bus->name;
  840. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  841. device_unregister(&mci->dev);
  842. bus_unregister(mci->bus);
  843. kfree(name);
  844. }
  845. static void mc_attr_release(struct device *dev)
  846. {
  847. /*
  848. * There's no container structure here, as this is just the mci
  849. * parent device, used to create the /sys/devices/mc sysfs node.
  850. * So, there are no attributes on it.
  851. */
  852. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  853. kfree(dev);
  854. }
  855. static struct device_type mc_attr_type = {
  856. .release = mc_attr_release,
  857. };
  858. /*
  859. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  860. */
  861. int __init edac_mc_sysfs_init(void)
  862. {
  863. struct bus_type *edac_subsys;
  864. int err;
  865. /* get the /sys/devices/system/edac subsys reference */
  866. edac_subsys = edac_get_sysfs_subsys();
  867. if (edac_subsys == NULL) {
  868. edac_dbg(1, "no edac_subsys\n");
  869. err = -EINVAL;
  870. goto out;
  871. }
  872. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  873. if (!mci_pdev) {
  874. err = -ENOMEM;
  875. goto out_put_sysfs;
  876. }
  877. mci_pdev->bus = edac_subsys;
  878. mci_pdev->type = &mc_attr_type;
  879. device_initialize(mci_pdev);
  880. dev_set_name(mci_pdev, "mc");
  881. err = device_add(mci_pdev);
  882. if (err < 0)
  883. goto out_dev_free;
  884. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  885. return 0;
  886. out_dev_free:
  887. kfree(mci_pdev);
  888. out_put_sysfs:
  889. edac_put_sysfs_subsys();
  890. out:
  891. return err;
  892. }
  893. void edac_mc_sysfs_exit(void)
  894. {
  895. device_unregister(mci_pdev);
  896. edac_put_sysfs_subsys();
  897. }