gpio-amdpt.c 6.5 KB

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  1. /*
  2. * AMD Promontory GPIO driver
  3. *
  4. * Copyright (C) 2015 ASMedia Technology Inc.
  5. * Author: YD Tseng <yd_tseng@asmedia.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/gpio/driver.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/acpi.h>
  16. #include <linux/platform_device.h>
  17. #define PT_TOTAL_GPIO 8
  18. /* PCI-E MMIO register offsets */
  19. #define PT_DIRECTION_REG 0x00
  20. #define PT_INPUTDATA_REG 0x04
  21. #define PT_OUTPUTDATA_REG 0x08
  22. #define PT_CLOCKRATE_REG 0x0C
  23. #define PT_SYNC_REG 0x28
  24. struct pt_gpio_chip {
  25. struct gpio_chip gc;
  26. void __iomem *reg_base;
  27. spinlock_t lock;
  28. };
  29. #define to_pt_gpio(c) container_of(c, struct pt_gpio_chip, gc)
  30. static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
  31. {
  32. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  33. unsigned long flags;
  34. u32 using_pins;
  35. dev_dbg(gc->dev, "pt_gpio_request offset=%x\n", offset);
  36. spin_lock_irqsave(&pt_gpio->lock, flags);
  37. using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
  38. if (using_pins & BIT(offset)) {
  39. dev_warn(gc->dev, "PT GPIO pin %x reconfigured\n",
  40. offset);
  41. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  42. return -EINVAL;
  43. }
  44. writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
  45. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  46. return 0;
  47. }
  48. static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
  49. {
  50. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  51. unsigned long flags;
  52. u32 using_pins;
  53. spin_lock_irqsave(&pt_gpio->lock, flags);
  54. using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
  55. using_pins &= ~BIT(offset);
  56. writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
  57. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  58. dev_dbg(gc->dev, "pt_gpio_free offset=%x\n", offset);
  59. }
  60. static void pt_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
  61. {
  62. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  63. unsigned long flags;
  64. u32 data;
  65. dev_dbg(gc->dev, "pt_gpio_set_value offset=%x, value=%x\n",
  66. offset, value);
  67. spin_lock_irqsave(&pt_gpio->lock, flags);
  68. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  69. data &= ~BIT(offset);
  70. if (value)
  71. data |= BIT(offset);
  72. writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  73. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  74. }
  75. static int pt_gpio_get_value(struct gpio_chip *gc, unsigned offset)
  76. {
  77. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  78. unsigned long flags;
  79. u32 data;
  80. spin_lock_irqsave(&pt_gpio->lock, flags);
  81. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  82. /* configure as output */
  83. if (data & BIT(offset))
  84. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  85. else /* configure as input */
  86. data = readl(pt_gpio->reg_base + PT_INPUTDATA_REG);
  87. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  88. data >>= offset;
  89. data &= 1;
  90. dev_dbg(gc->dev, "pt_gpio_get_value offset=%x, value=%x\n",
  91. offset, data);
  92. return data;
  93. }
  94. static int pt_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
  95. {
  96. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  97. unsigned long flags;
  98. u32 data;
  99. dev_dbg(gc->dev, "pt_gpio_dirction_input offset=%x\n", offset);
  100. spin_lock_irqsave(&pt_gpio->lock, flags);
  101. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  102. data &= ~BIT(offset);
  103. writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
  104. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  105. return 0;
  106. }
  107. static int pt_gpio_direction_output(struct gpio_chip *gc,
  108. unsigned offset, int value)
  109. {
  110. struct pt_gpio_chip *pt_gpio = to_pt_gpio(gc);
  111. unsigned long flags;
  112. u32 data;
  113. dev_dbg(gc->dev, "pt_gpio_direction_output offset=%x, value=%x\n",
  114. offset, value);
  115. spin_lock_irqsave(&pt_gpio->lock, flags);
  116. data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  117. if (value)
  118. data |= BIT(offset);
  119. else
  120. data &= ~BIT(offset);
  121. writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
  122. data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
  123. data |= BIT(offset);
  124. writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
  125. spin_unlock_irqrestore(&pt_gpio->lock, flags);
  126. return 0;
  127. }
  128. static int pt_gpio_probe(struct platform_device *pdev)
  129. {
  130. struct device *dev = &pdev->dev;
  131. struct acpi_device *acpi_dev;
  132. acpi_handle handle = ACPI_HANDLE(dev);
  133. struct pt_gpio_chip *pt_gpio;
  134. struct resource *res_mem;
  135. int ret = 0;
  136. if (acpi_bus_get_device(handle, &acpi_dev)) {
  137. dev_err(dev, "PT GPIO device node not found\n");
  138. return -ENODEV;
  139. }
  140. pt_gpio = devm_kzalloc(dev, sizeof(struct pt_gpio_chip), GFP_KERNEL);
  141. if (!pt_gpio)
  142. return -ENOMEM;
  143. res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  144. if (!res_mem) {
  145. dev_err(&pdev->dev, "Failed to get MMIO resource for PT GPIO.\n");
  146. return -EINVAL;
  147. }
  148. pt_gpio->reg_base = devm_ioremap_resource(dev, res_mem);
  149. if (IS_ERR(pt_gpio->reg_base)) {
  150. dev_err(&pdev->dev, "Failed to map MMIO resource for PT GPIO.\n");
  151. return PTR_ERR(pt_gpio->reg_base);
  152. }
  153. spin_lock_init(&pt_gpio->lock);
  154. pt_gpio->gc.label = pdev->name;
  155. pt_gpio->gc.owner = THIS_MODULE;
  156. pt_gpio->gc.dev = dev;
  157. pt_gpio->gc.request = pt_gpio_request;
  158. pt_gpio->gc.free = pt_gpio_free;
  159. pt_gpio->gc.direction_input = pt_gpio_direction_input;
  160. pt_gpio->gc.direction_output = pt_gpio_direction_output;
  161. pt_gpio->gc.get = pt_gpio_get_value;
  162. pt_gpio->gc.set = pt_gpio_set_value;
  163. pt_gpio->gc.base = -1;
  164. pt_gpio->gc.ngpio = PT_TOTAL_GPIO;
  165. #if defined(CONFIG_OF_GPIO)
  166. pt_gpio->gc.of_node = pdev->dev.of_node;
  167. #endif
  168. ret = gpiochip_add(&pt_gpio->gc);
  169. if (ret) {
  170. dev_err(&pdev->dev, "Failed to register GPIO lib\n");
  171. return ret;
  172. }
  173. platform_set_drvdata(pdev, pt_gpio);
  174. /* initialize register setting */
  175. writel(0, pt_gpio->reg_base + PT_SYNC_REG);
  176. writel(0, pt_gpio->reg_base + PT_CLOCKRATE_REG);
  177. dev_dbg(&pdev->dev, "PT GPIO driver loaded\n");
  178. return ret;
  179. }
  180. static int pt_gpio_remove(struct platform_device *pdev)
  181. {
  182. struct pt_gpio_chip *pt_gpio = platform_get_drvdata(pdev);
  183. gpiochip_remove(&pt_gpio->gc);
  184. return 0;
  185. }
  186. static const struct acpi_device_id pt_gpio_acpi_match[] = {
  187. { "AMDF030", 0 },
  188. { },
  189. };
  190. MODULE_DEVICE_TABLE(acpi, pt_gpio_acpi_match);
  191. static struct platform_driver pt_gpio_driver = {
  192. .driver = {
  193. .name = "pt-gpio",
  194. .acpi_match_table = ACPI_PTR(pt_gpio_acpi_match),
  195. },
  196. .probe = pt_gpio_probe,
  197. .remove = pt_gpio_remove,
  198. };
  199. module_platform_driver(pt_gpio_driver);
  200. MODULE_LICENSE("GPL");
  201. MODULE_AUTHOR("YD Tseng <yd_tseng@asmedia.com.tw>");
  202. MODULE_DESCRIPTION("AMD Promontory GPIO Driver");