gpio-mcp23s08.c 25 KB

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  1. /*
  2. * MCP23S08 SPI/I2C GPIO gpio expander driver
  3. *
  4. * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
  5. * supported.
  6. * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
  7. * interrupts is also supported.
  8. * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
  9. * also capable of generating interrupts, but the linux driver does not
  10. * support that yet.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/device.h>
  14. #include <linux/mutex.h>
  15. #include <linux/module.h>
  16. #include <linux/gpio.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/spi/mcp23s08.h>
  20. #include <linux/slab.h>
  21. #include <asm/byteorder.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/of_device.h>
  25. /**
  26. * MCP types supported by driver
  27. */
  28. #define MCP_TYPE_S08 0
  29. #define MCP_TYPE_S17 1
  30. #define MCP_TYPE_008 2
  31. #define MCP_TYPE_017 3
  32. /* Registers are all 8 bits wide.
  33. *
  34. * The mcp23s17 has twice as many bits, and can be configured to work
  35. * with either 16 bit registers or with two adjacent 8 bit banks.
  36. */
  37. #define MCP_IODIR 0x00 /* init/reset: all ones */
  38. #define MCP_IPOL 0x01
  39. #define MCP_GPINTEN 0x02
  40. #define MCP_DEFVAL 0x03
  41. #define MCP_INTCON 0x04
  42. #define MCP_IOCON 0x05
  43. # define IOCON_MIRROR (1 << 6)
  44. # define IOCON_SEQOP (1 << 5)
  45. # define IOCON_HAEN (1 << 3)
  46. # define IOCON_ODR (1 << 2)
  47. # define IOCON_INTPOL (1 << 1)
  48. #define MCP_GPPU 0x06
  49. #define MCP_INTF 0x07
  50. #define MCP_INTCAP 0x08
  51. #define MCP_GPIO 0x09
  52. #define MCP_OLAT 0x0a
  53. struct mcp23s08;
  54. struct mcp23s08_ops {
  55. int (*read)(struct mcp23s08 *mcp, unsigned reg);
  56. int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
  57. int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
  58. u16 *vals, unsigned n);
  59. };
  60. struct mcp23s08 {
  61. u8 addr;
  62. bool irq_active_high;
  63. u16 cache[11];
  64. u16 irq_rise;
  65. u16 irq_fall;
  66. int irq;
  67. bool irq_controller;
  68. /* lock protects the cached values */
  69. struct mutex lock;
  70. struct mutex irq_lock;
  71. struct irq_domain *irq_domain;
  72. struct gpio_chip chip;
  73. const struct mcp23s08_ops *ops;
  74. void *data; /* ops specific data */
  75. };
  76. /* A given spi_device can represent up to eight mcp23sxx chips
  77. * sharing the same chipselect but using different addresses
  78. * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
  79. * Driver data holds all the per-chip data.
  80. */
  81. struct mcp23s08_driver_data {
  82. unsigned ngpio;
  83. struct mcp23s08 *mcp[8];
  84. struct mcp23s08 chip[];
  85. };
  86. /* This lock class tells lockdep that GPIO irqs are in a different
  87. * category than their parents, so it won't report false recursion.
  88. */
  89. static struct lock_class_key gpio_lock_class;
  90. /*----------------------------------------------------------------------*/
  91. #if IS_ENABLED(CONFIG_I2C)
  92. static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
  93. {
  94. return i2c_smbus_read_byte_data(mcp->data, reg);
  95. }
  96. static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  97. {
  98. return i2c_smbus_write_byte_data(mcp->data, reg, val);
  99. }
  100. static int
  101. mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  102. {
  103. while (n--) {
  104. int ret = mcp23008_read(mcp, reg++);
  105. if (ret < 0)
  106. return ret;
  107. *vals++ = ret;
  108. }
  109. return 0;
  110. }
  111. static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
  112. {
  113. return i2c_smbus_read_word_data(mcp->data, reg << 1);
  114. }
  115. static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  116. {
  117. return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
  118. }
  119. static int
  120. mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  121. {
  122. while (n--) {
  123. int ret = mcp23017_read(mcp, reg++);
  124. if (ret < 0)
  125. return ret;
  126. *vals++ = ret;
  127. }
  128. return 0;
  129. }
  130. static const struct mcp23s08_ops mcp23008_ops = {
  131. .read = mcp23008_read,
  132. .write = mcp23008_write,
  133. .read_regs = mcp23008_read_regs,
  134. };
  135. static const struct mcp23s08_ops mcp23017_ops = {
  136. .read = mcp23017_read,
  137. .write = mcp23017_write,
  138. .read_regs = mcp23017_read_regs,
  139. };
  140. #endif /* CONFIG_I2C */
  141. /*----------------------------------------------------------------------*/
  142. #ifdef CONFIG_SPI_MASTER
  143. static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
  144. {
  145. u8 tx[2], rx[1];
  146. int status;
  147. tx[0] = mcp->addr | 0x01;
  148. tx[1] = reg;
  149. status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
  150. return (status < 0) ? status : rx[0];
  151. }
  152. static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  153. {
  154. u8 tx[3];
  155. tx[0] = mcp->addr;
  156. tx[1] = reg;
  157. tx[2] = val;
  158. return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
  159. }
  160. static int
  161. mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  162. {
  163. u8 tx[2], *tmp;
  164. int status;
  165. if ((n + reg) > sizeof(mcp->cache))
  166. return -EINVAL;
  167. tx[0] = mcp->addr | 0x01;
  168. tx[1] = reg;
  169. tmp = (u8 *)vals;
  170. status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
  171. if (status >= 0) {
  172. while (n--)
  173. vals[n] = tmp[n]; /* expand to 16bit */
  174. }
  175. return status;
  176. }
  177. static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
  178. {
  179. u8 tx[2], rx[2];
  180. int status;
  181. tx[0] = mcp->addr | 0x01;
  182. tx[1] = reg << 1;
  183. status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
  184. return (status < 0) ? status : (rx[0] | (rx[1] << 8));
  185. }
  186. static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
  187. {
  188. u8 tx[4];
  189. tx[0] = mcp->addr;
  190. tx[1] = reg << 1;
  191. tx[2] = val;
  192. tx[3] = val >> 8;
  193. return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
  194. }
  195. static int
  196. mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
  197. {
  198. u8 tx[2];
  199. int status;
  200. if ((n + reg) > sizeof(mcp->cache))
  201. return -EINVAL;
  202. tx[0] = mcp->addr | 0x01;
  203. tx[1] = reg << 1;
  204. status = spi_write_then_read(mcp->data, tx, sizeof(tx),
  205. (u8 *)vals, n * 2);
  206. if (status >= 0) {
  207. while (n--)
  208. vals[n] = __le16_to_cpu((__le16)vals[n]);
  209. }
  210. return status;
  211. }
  212. static const struct mcp23s08_ops mcp23s08_ops = {
  213. .read = mcp23s08_read,
  214. .write = mcp23s08_write,
  215. .read_regs = mcp23s08_read_regs,
  216. };
  217. static const struct mcp23s08_ops mcp23s17_ops = {
  218. .read = mcp23s17_read,
  219. .write = mcp23s17_write,
  220. .read_regs = mcp23s17_read_regs,
  221. };
  222. #endif /* CONFIG_SPI_MASTER */
  223. /*----------------------------------------------------------------------*/
  224. static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
  225. {
  226. struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
  227. int status;
  228. mutex_lock(&mcp->lock);
  229. mcp->cache[MCP_IODIR] |= (1 << offset);
  230. status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
  231. mutex_unlock(&mcp->lock);
  232. return status;
  233. }
  234. static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
  235. {
  236. struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
  237. int status;
  238. mutex_lock(&mcp->lock);
  239. /* REVISIT reading this clears any IRQ ... */
  240. status = mcp->ops->read(mcp, MCP_GPIO);
  241. if (status < 0)
  242. status = 0;
  243. else {
  244. mcp->cache[MCP_GPIO] = status;
  245. status = !!(status & (1 << offset));
  246. }
  247. mutex_unlock(&mcp->lock);
  248. return status;
  249. }
  250. static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
  251. {
  252. unsigned olat = mcp->cache[MCP_OLAT];
  253. if (value)
  254. olat |= mask;
  255. else
  256. olat &= ~mask;
  257. mcp->cache[MCP_OLAT] = olat;
  258. return mcp->ops->write(mcp, MCP_OLAT, olat);
  259. }
  260. static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
  261. {
  262. struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
  263. unsigned mask = 1 << offset;
  264. mutex_lock(&mcp->lock);
  265. __mcp23s08_set(mcp, mask, value);
  266. mutex_unlock(&mcp->lock);
  267. }
  268. static int
  269. mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  270. {
  271. struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
  272. unsigned mask = 1 << offset;
  273. int status;
  274. mutex_lock(&mcp->lock);
  275. status = __mcp23s08_set(mcp, mask, value);
  276. if (status == 0) {
  277. mcp->cache[MCP_IODIR] &= ~mask;
  278. status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
  279. }
  280. mutex_unlock(&mcp->lock);
  281. return status;
  282. }
  283. /*----------------------------------------------------------------------*/
  284. static irqreturn_t mcp23s08_irq(int irq, void *data)
  285. {
  286. struct mcp23s08 *mcp = data;
  287. int intcap, intf, i;
  288. unsigned int child_irq;
  289. mutex_lock(&mcp->lock);
  290. intf = mcp->ops->read(mcp, MCP_INTF);
  291. if (intf < 0) {
  292. mutex_unlock(&mcp->lock);
  293. return IRQ_HANDLED;
  294. }
  295. mcp->cache[MCP_INTF] = intf;
  296. intcap = mcp->ops->read(mcp, MCP_INTCAP);
  297. if (intcap < 0) {
  298. mutex_unlock(&mcp->lock);
  299. return IRQ_HANDLED;
  300. }
  301. mcp->cache[MCP_INTCAP] = intcap;
  302. mutex_unlock(&mcp->lock);
  303. for (i = 0; i < mcp->chip.ngpio; i++) {
  304. if ((BIT(i) & mcp->cache[MCP_INTF]) &&
  305. ((BIT(i) & intcap & mcp->irq_rise) ||
  306. (mcp->irq_fall & ~intcap & BIT(i)))) {
  307. child_irq = irq_find_mapping(mcp->irq_domain, i);
  308. handle_nested_irq(child_irq);
  309. }
  310. }
  311. return IRQ_HANDLED;
  312. }
  313. static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  314. {
  315. struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip);
  316. return irq_find_mapping(mcp->irq_domain, offset);
  317. }
  318. static void mcp23s08_irq_mask(struct irq_data *data)
  319. {
  320. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  321. unsigned int pos = data->hwirq;
  322. mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
  323. }
  324. static void mcp23s08_irq_unmask(struct irq_data *data)
  325. {
  326. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  327. unsigned int pos = data->hwirq;
  328. mcp->cache[MCP_GPINTEN] |= BIT(pos);
  329. }
  330. static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
  331. {
  332. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  333. unsigned int pos = data->hwirq;
  334. int status = 0;
  335. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  336. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  337. mcp->irq_rise |= BIT(pos);
  338. mcp->irq_fall |= BIT(pos);
  339. } else if (type & IRQ_TYPE_EDGE_RISING) {
  340. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  341. mcp->irq_rise |= BIT(pos);
  342. mcp->irq_fall &= ~BIT(pos);
  343. } else if (type & IRQ_TYPE_EDGE_FALLING) {
  344. mcp->cache[MCP_INTCON] &= ~BIT(pos);
  345. mcp->irq_rise &= ~BIT(pos);
  346. mcp->irq_fall |= BIT(pos);
  347. } else
  348. return -EINVAL;
  349. return status;
  350. }
  351. static void mcp23s08_irq_bus_lock(struct irq_data *data)
  352. {
  353. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  354. mutex_lock(&mcp->irq_lock);
  355. }
  356. static void mcp23s08_irq_bus_unlock(struct irq_data *data)
  357. {
  358. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  359. mutex_lock(&mcp->lock);
  360. mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
  361. mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
  362. mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
  363. mutex_unlock(&mcp->lock);
  364. mutex_unlock(&mcp->irq_lock);
  365. }
  366. static int mcp23s08_irq_reqres(struct irq_data *data)
  367. {
  368. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  369. if (gpiochip_lock_as_irq(&mcp->chip, data->hwirq)) {
  370. dev_err(mcp->chip.dev,
  371. "unable to lock HW IRQ %lu for IRQ usage\n",
  372. data->hwirq);
  373. return -EINVAL;
  374. }
  375. return 0;
  376. }
  377. static void mcp23s08_irq_relres(struct irq_data *data)
  378. {
  379. struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data);
  380. gpiochip_unlock_as_irq(&mcp->chip, data->hwirq);
  381. }
  382. static struct irq_chip mcp23s08_irq_chip = {
  383. .name = "gpio-mcp23xxx",
  384. .irq_mask = mcp23s08_irq_mask,
  385. .irq_unmask = mcp23s08_irq_unmask,
  386. .irq_set_type = mcp23s08_irq_set_type,
  387. .irq_bus_lock = mcp23s08_irq_bus_lock,
  388. .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
  389. .irq_request_resources = mcp23s08_irq_reqres,
  390. .irq_release_resources = mcp23s08_irq_relres,
  391. };
  392. static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
  393. {
  394. struct gpio_chip *chip = &mcp->chip;
  395. int err, irq, j;
  396. unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
  397. mutex_init(&mcp->irq_lock);
  398. mcp->irq_domain = irq_domain_add_linear(chip->dev->of_node, chip->ngpio,
  399. &irq_domain_simple_ops, mcp);
  400. if (!mcp->irq_domain)
  401. return -ENODEV;
  402. if (mcp->irq_active_high)
  403. irqflags |= IRQF_TRIGGER_HIGH;
  404. else
  405. irqflags |= IRQF_TRIGGER_LOW;
  406. err = devm_request_threaded_irq(chip->dev, mcp->irq, NULL, mcp23s08_irq,
  407. irqflags, dev_name(chip->dev), mcp);
  408. if (err != 0) {
  409. dev_err(chip->dev, "unable to request IRQ#%d: %d\n",
  410. mcp->irq, err);
  411. return err;
  412. }
  413. chip->to_irq = mcp23s08_gpio_to_irq;
  414. for (j = 0; j < mcp->chip.ngpio; j++) {
  415. irq = irq_create_mapping(mcp->irq_domain, j);
  416. irq_set_lockdep_class(irq, &gpio_lock_class);
  417. irq_set_chip_data(irq, mcp);
  418. irq_set_chip(irq, &mcp23s08_irq_chip);
  419. irq_set_nested_thread(irq, true);
  420. irq_set_noprobe(irq);
  421. }
  422. return 0;
  423. }
  424. static void mcp23s08_irq_teardown(struct mcp23s08 *mcp)
  425. {
  426. unsigned int irq, i;
  427. for (i = 0; i < mcp->chip.ngpio; i++) {
  428. irq = irq_find_mapping(mcp->irq_domain, i);
  429. if (irq > 0)
  430. irq_dispose_mapping(irq);
  431. }
  432. irq_domain_remove(mcp->irq_domain);
  433. }
  434. /*----------------------------------------------------------------------*/
  435. #ifdef CONFIG_DEBUG_FS
  436. #include <linux/seq_file.h>
  437. /*
  438. * This shows more info than the generic gpio dump code:
  439. * pullups, deglitching, open drain drive.
  440. */
  441. static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  442. {
  443. struct mcp23s08 *mcp;
  444. char bank;
  445. int t;
  446. unsigned mask;
  447. mcp = container_of(chip, struct mcp23s08, chip);
  448. /* NOTE: we only handle one bank for now ... */
  449. bank = '0' + ((mcp->addr >> 1) & 0x7);
  450. mutex_lock(&mcp->lock);
  451. t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
  452. if (t < 0) {
  453. seq_printf(s, " I/O ERROR %d\n", t);
  454. goto done;
  455. }
  456. for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
  457. const char *label;
  458. label = gpiochip_is_requested(chip, t);
  459. if (!label)
  460. continue;
  461. seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
  462. chip->base + t, bank, t, label,
  463. (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
  464. (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
  465. (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
  466. /* NOTE: ignoring the irq-related registers */
  467. seq_puts(s, "\n");
  468. }
  469. done:
  470. mutex_unlock(&mcp->lock);
  471. }
  472. #else
  473. #define mcp23s08_dbg_show NULL
  474. #endif
  475. /*----------------------------------------------------------------------*/
  476. static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
  477. void *data, unsigned addr, unsigned type,
  478. struct mcp23s08_platform_data *pdata, int cs)
  479. {
  480. int status;
  481. bool mirror = false;
  482. mutex_init(&mcp->lock);
  483. mcp->data = data;
  484. mcp->addr = addr;
  485. mcp->irq_active_high = false;
  486. mcp->chip.direction_input = mcp23s08_direction_input;
  487. mcp->chip.get = mcp23s08_get;
  488. mcp->chip.direction_output = mcp23s08_direction_output;
  489. mcp->chip.set = mcp23s08_set;
  490. mcp->chip.dbg_show = mcp23s08_dbg_show;
  491. #ifdef CONFIG_OF
  492. mcp->chip.of_gpio_n_cells = 2;
  493. mcp->chip.of_node = dev->of_node;
  494. #endif
  495. switch (type) {
  496. #ifdef CONFIG_SPI_MASTER
  497. case MCP_TYPE_S08:
  498. mcp->ops = &mcp23s08_ops;
  499. mcp->chip.ngpio = 8;
  500. mcp->chip.label = "mcp23s08";
  501. break;
  502. case MCP_TYPE_S17:
  503. mcp->ops = &mcp23s17_ops;
  504. mcp->chip.ngpio = 16;
  505. mcp->chip.label = "mcp23s17";
  506. break;
  507. #endif /* CONFIG_SPI_MASTER */
  508. #if IS_ENABLED(CONFIG_I2C)
  509. case MCP_TYPE_008:
  510. mcp->ops = &mcp23008_ops;
  511. mcp->chip.ngpio = 8;
  512. mcp->chip.label = "mcp23008";
  513. break;
  514. case MCP_TYPE_017:
  515. mcp->ops = &mcp23017_ops;
  516. mcp->chip.ngpio = 16;
  517. mcp->chip.label = "mcp23017";
  518. break;
  519. #endif /* CONFIG_I2C */
  520. default:
  521. dev_err(dev, "invalid device type (%d)\n", type);
  522. return -EINVAL;
  523. }
  524. mcp->chip.base = pdata->base;
  525. mcp->chip.can_sleep = true;
  526. mcp->chip.dev = dev;
  527. mcp->chip.owner = THIS_MODULE;
  528. /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
  529. * and MCP_IOCON.HAEN = 1, so we work with all chips.
  530. */
  531. status = mcp->ops->read(mcp, MCP_IOCON);
  532. if (status < 0)
  533. goto fail;
  534. mcp->irq_controller = pdata->irq_controller;
  535. if (mcp->irq && mcp->irq_controller) {
  536. mcp->irq_active_high =
  537. of_property_read_bool(mcp->chip.dev->of_node,
  538. "microchip,irq-active-high");
  539. if (type == MCP_TYPE_017)
  540. mirror = pdata->mirror;
  541. }
  542. if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
  543. mcp->irq_active_high) {
  544. /* mcp23s17 has IOCON twice, make sure they are in sync */
  545. status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
  546. status |= IOCON_HAEN | (IOCON_HAEN << 8);
  547. if (mcp->irq_active_high)
  548. status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
  549. else
  550. status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
  551. if (mirror)
  552. status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
  553. status = mcp->ops->write(mcp, MCP_IOCON, status);
  554. if (status < 0)
  555. goto fail;
  556. }
  557. /* configure ~100K pullups */
  558. status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
  559. if (status < 0)
  560. goto fail;
  561. status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
  562. if (status < 0)
  563. goto fail;
  564. /* disable inverter on input */
  565. if (mcp->cache[MCP_IPOL] != 0) {
  566. mcp->cache[MCP_IPOL] = 0;
  567. status = mcp->ops->write(mcp, MCP_IPOL, 0);
  568. if (status < 0)
  569. goto fail;
  570. }
  571. /* disable irqs */
  572. if (mcp->cache[MCP_GPINTEN] != 0) {
  573. mcp->cache[MCP_GPINTEN] = 0;
  574. status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
  575. if (status < 0)
  576. goto fail;
  577. }
  578. status = gpiochip_add(&mcp->chip);
  579. if (status < 0)
  580. goto fail;
  581. if (mcp->irq && mcp->irq_controller) {
  582. status = mcp23s08_irq_setup(mcp);
  583. if (status) {
  584. mcp23s08_irq_teardown(mcp);
  585. goto fail;
  586. }
  587. }
  588. fail:
  589. if (status < 0)
  590. dev_dbg(dev, "can't setup chip %d, --> %d\n",
  591. addr, status);
  592. return status;
  593. }
  594. /*----------------------------------------------------------------------*/
  595. #ifdef CONFIG_OF
  596. #ifdef CONFIG_SPI_MASTER
  597. static const struct of_device_id mcp23s08_spi_of_match[] = {
  598. {
  599. .compatible = "microchip,mcp23s08",
  600. .data = (void *) MCP_TYPE_S08,
  601. },
  602. {
  603. .compatible = "microchip,mcp23s17",
  604. .data = (void *) MCP_TYPE_S17,
  605. },
  606. /* NOTE: The use of the mcp prefix is deprecated and will be removed. */
  607. {
  608. .compatible = "mcp,mcp23s08",
  609. .data = (void *) MCP_TYPE_S08,
  610. },
  611. {
  612. .compatible = "mcp,mcp23s17",
  613. .data = (void *) MCP_TYPE_S17,
  614. },
  615. { },
  616. };
  617. MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
  618. #endif
  619. #if IS_ENABLED(CONFIG_I2C)
  620. static const struct of_device_id mcp23s08_i2c_of_match[] = {
  621. {
  622. .compatible = "microchip,mcp23008",
  623. .data = (void *) MCP_TYPE_008,
  624. },
  625. {
  626. .compatible = "microchip,mcp23017",
  627. .data = (void *) MCP_TYPE_017,
  628. },
  629. /* NOTE: The use of the mcp prefix is deprecated and will be removed. */
  630. {
  631. .compatible = "mcp,mcp23008",
  632. .data = (void *) MCP_TYPE_008,
  633. },
  634. {
  635. .compatible = "mcp,mcp23017",
  636. .data = (void *) MCP_TYPE_017,
  637. },
  638. { },
  639. };
  640. MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
  641. #endif
  642. #endif /* CONFIG_OF */
  643. #if IS_ENABLED(CONFIG_I2C)
  644. static int mcp230xx_probe(struct i2c_client *client,
  645. const struct i2c_device_id *id)
  646. {
  647. struct mcp23s08_platform_data *pdata, local_pdata;
  648. struct mcp23s08 *mcp;
  649. int status;
  650. const struct of_device_id *match;
  651. match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
  652. &client->dev);
  653. if (match) {
  654. pdata = &local_pdata;
  655. pdata->base = -1;
  656. pdata->chip[0].pullups = 0;
  657. pdata->irq_controller = of_property_read_bool(
  658. client->dev.of_node,
  659. "interrupt-controller");
  660. pdata->mirror = of_property_read_bool(client->dev.of_node,
  661. "microchip,irq-mirror");
  662. client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
  663. } else {
  664. pdata = dev_get_platdata(&client->dev);
  665. if (!pdata) {
  666. pdata = devm_kzalloc(&client->dev,
  667. sizeof(struct mcp23s08_platform_data),
  668. GFP_KERNEL);
  669. pdata->base = -1;
  670. }
  671. }
  672. mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
  673. if (!mcp)
  674. return -ENOMEM;
  675. mcp->irq = client->irq;
  676. status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
  677. id->driver_data, pdata, 0);
  678. if (status)
  679. goto fail;
  680. i2c_set_clientdata(client, mcp);
  681. return 0;
  682. fail:
  683. kfree(mcp);
  684. return status;
  685. }
  686. static int mcp230xx_remove(struct i2c_client *client)
  687. {
  688. struct mcp23s08 *mcp = i2c_get_clientdata(client);
  689. if (client->irq && mcp->irq_controller)
  690. mcp23s08_irq_teardown(mcp);
  691. gpiochip_remove(&mcp->chip);
  692. kfree(mcp);
  693. return 0;
  694. }
  695. static const struct i2c_device_id mcp230xx_id[] = {
  696. { "mcp23008", MCP_TYPE_008 },
  697. { "mcp23017", MCP_TYPE_017 },
  698. { },
  699. };
  700. MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
  701. static struct i2c_driver mcp230xx_driver = {
  702. .driver = {
  703. .name = "mcp230xx",
  704. .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
  705. },
  706. .probe = mcp230xx_probe,
  707. .remove = mcp230xx_remove,
  708. .id_table = mcp230xx_id,
  709. };
  710. static int __init mcp23s08_i2c_init(void)
  711. {
  712. return i2c_add_driver(&mcp230xx_driver);
  713. }
  714. static void mcp23s08_i2c_exit(void)
  715. {
  716. i2c_del_driver(&mcp230xx_driver);
  717. }
  718. #else
  719. static int __init mcp23s08_i2c_init(void) { return 0; }
  720. static void mcp23s08_i2c_exit(void) { }
  721. #endif /* CONFIG_I2C */
  722. /*----------------------------------------------------------------------*/
  723. #ifdef CONFIG_SPI_MASTER
  724. static int mcp23s08_probe(struct spi_device *spi)
  725. {
  726. struct mcp23s08_platform_data *pdata, local_pdata;
  727. unsigned addr;
  728. int chips = 0;
  729. struct mcp23s08_driver_data *data;
  730. int status, type;
  731. unsigned ngpio = 0;
  732. const struct of_device_id *match;
  733. u32 spi_present_mask = 0;
  734. match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
  735. if (match) {
  736. type = (int)(uintptr_t)match->data;
  737. status = of_property_read_u32(spi->dev.of_node,
  738. "microchip,spi-present-mask", &spi_present_mask);
  739. if (status) {
  740. status = of_property_read_u32(spi->dev.of_node,
  741. "mcp,spi-present-mask", &spi_present_mask);
  742. if (status) {
  743. dev_err(&spi->dev,
  744. "DT has no spi-present-mask\n");
  745. return -ENODEV;
  746. }
  747. }
  748. if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
  749. dev_err(&spi->dev, "invalid spi-present-mask\n");
  750. return -ENODEV;
  751. }
  752. pdata = &local_pdata;
  753. pdata->base = -1;
  754. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  755. pdata->chip[addr].pullups = 0;
  756. if (spi_present_mask & (1 << addr))
  757. chips++;
  758. }
  759. pdata->irq_controller = of_property_read_bool(
  760. spi->dev.of_node,
  761. "interrupt-controller");
  762. pdata->mirror = of_property_read_bool(spi->dev.of_node,
  763. "microchip,irq-mirror");
  764. } else {
  765. type = spi_get_device_id(spi)->driver_data;
  766. pdata = dev_get_platdata(&spi->dev);
  767. if (!pdata) {
  768. pdata = devm_kzalloc(&spi->dev,
  769. sizeof(struct mcp23s08_platform_data),
  770. GFP_KERNEL);
  771. pdata->base = -1;
  772. }
  773. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  774. if (!pdata->chip[addr].is_present)
  775. continue;
  776. chips++;
  777. if ((type == MCP_TYPE_S08) && (addr > 3)) {
  778. dev_err(&spi->dev,
  779. "mcp23s08 only supports address 0..3\n");
  780. return -EINVAL;
  781. }
  782. spi_present_mask |= 1 << addr;
  783. }
  784. }
  785. if (!chips)
  786. return -ENODEV;
  787. data = devm_kzalloc(&spi->dev,
  788. sizeof(*data) + chips * sizeof(struct mcp23s08),
  789. GFP_KERNEL);
  790. if (!data)
  791. return -ENOMEM;
  792. spi_set_drvdata(spi, data);
  793. spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
  794. for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
  795. if (!(spi_present_mask & (1 << addr)))
  796. continue;
  797. chips--;
  798. data->mcp[addr] = &data->chip[chips];
  799. data->mcp[addr]->irq = spi->irq;
  800. status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
  801. 0x40 | (addr << 1), type, pdata,
  802. addr);
  803. if (status < 0)
  804. goto fail;
  805. if (pdata->base != -1)
  806. pdata->base += (type == MCP_TYPE_S17) ? 16 : 8;
  807. ngpio += (type == MCP_TYPE_S17) ? 16 : 8;
  808. }
  809. data->ngpio = ngpio;
  810. /* NOTE: these chips have a relatively sane IRQ framework, with
  811. * per-signal masking and level/edge triggering. It's not yet
  812. * handled here...
  813. */
  814. return 0;
  815. fail:
  816. for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
  817. if (!data->mcp[addr])
  818. continue;
  819. gpiochip_remove(&data->mcp[addr]->chip);
  820. }
  821. return status;
  822. }
  823. static int mcp23s08_remove(struct spi_device *spi)
  824. {
  825. struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
  826. unsigned addr;
  827. for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
  828. if (!data->mcp[addr])
  829. continue;
  830. if (spi->irq && data->mcp[addr]->irq_controller)
  831. mcp23s08_irq_teardown(data->mcp[addr]);
  832. gpiochip_remove(&data->mcp[addr]->chip);
  833. }
  834. return 0;
  835. }
  836. static const struct spi_device_id mcp23s08_ids[] = {
  837. { "mcp23s08", MCP_TYPE_S08 },
  838. { "mcp23s17", MCP_TYPE_S17 },
  839. { },
  840. };
  841. MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
  842. static struct spi_driver mcp23s08_driver = {
  843. .probe = mcp23s08_probe,
  844. .remove = mcp23s08_remove,
  845. .id_table = mcp23s08_ids,
  846. .driver = {
  847. .name = "mcp23s08",
  848. .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
  849. },
  850. };
  851. static int __init mcp23s08_spi_init(void)
  852. {
  853. return spi_register_driver(&mcp23s08_driver);
  854. }
  855. static void mcp23s08_spi_exit(void)
  856. {
  857. spi_unregister_driver(&mcp23s08_driver);
  858. }
  859. #else
  860. static int __init mcp23s08_spi_init(void) { return 0; }
  861. static void mcp23s08_spi_exit(void) { }
  862. #endif /* CONFIG_SPI_MASTER */
  863. /*----------------------------------------------------------------------*/
  864. static int __init mcp23s08_init(void)
  865. {
  866. int ret;
  867. ret = mcp23s08_spi_init();
  868. if (ret)
  869. goto spi_fail;
  870. ret = mcp23s08_i2c_init();
  871. if (ret)
  872. goto i2c_fail;
  873. return 0;
  874. i2c_fail:
  875. mcp23s08_spi_exit();
  876. spi_fail:
  877. return ret;
  878. }
  879. /* register after spi/i2c postcore initcall and before
  880. * subsys initcalls that may rely on these GPIOs
  881. */
  882. subsys_initcall(mcp23s08_init);
  883. static void __exit mcp23s08_exit(void)
  884. {
  885. mcp23s08_spi_exit();
  886. mcp23s08_i2c_exit();
  887. }
  888. module_exit(mcp23s08_exit);
  889. MODULE_LICENSE("GPL");