gpio-pca953x.c 19 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #ifdef CONFIG_OF_GPIO
  21. #include <linux/of_platform.h>
  22. #endif
  23. #include <linux/acpi.h>
  24. #define PCA953X_INPUT 0
  25. #define PCA953X_OUTPUT 1
  26. #define PCA953X_INVERT 2
  27. #define PCA953X_DIRECTION 3
  28. #define REG_ADDR_AI 0x80
  29. #define PCA957X_IN 0
  30. #define PCA957X_INVRT 1
  31. #define PCA957X_BKEN 2
  32. #define PCA957X_PUPD 3
  33. #define PCA957X_CFG 4
  34. #define PCA957X_OUT 5
  35. #define PCA957X_MSK 6
  36. #define PCA957X_INTS 7
  37. #define PCA_GPIO_MASK 0x00FF
  38. #define PCA_INT 0x0100
  39. #define PCA953X_TYPE 0x1000
  40. #define PCA957X_TYPE 0x2000
  41. #define PCA_TYPE_MASK 0xF000
  42. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  43. static const struct i2c_device_id pca953x_id[] = {
  44. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  45. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  46. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  47. { "pca9536", 4 | PCA953X_TYPE, },
  48. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  53. { "pca9556", 8 | PCA953X_TYPE, },
  54. { "pca9557", 8 | PCA953X_TYPE, },
  55. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  56. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  57. { "pca9698", 40 | PCA953X_TYPE, },
  58. { "max7310", 8 | PCA953X_TYPE, },
  59. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  60. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  61. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  62. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  63. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  64. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  65. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  66. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  67. { "xra1202", 8 | PCA953X_TYPE },
  68. { }
  69. };
  70. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  71. static const struct acpi_device_id pca953x_acpi_ids[] = {
  72. { "INT3491", 16 | PCA953X_TYPE | PCA_INT, },
  73. { }
  74. };
  75. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  76. #define MAX_BANK 5
  77. #define BANK_SZ 8
  78. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  79. struct pca953x_chip {
  80. unsigned gpio_start;
  81. u8 reg_output[MAX_BANK];
  82. u8 reg_direction[MAX_BANK];
  83. struct mutex i2c_lock;
  84. #ifdef CONFIG_GPIO_PCA953X_IRQ
  85. struct mutex irq_lock;
  86. u8 irq_mask[MAX_BANK];
  87. u8 irq_stat[MAX_BANK];
  88. u8 irq_trig_raise[MAX_BANK];
  89. u8 irq_trig_fall[MAX_BANK];
  90. #endif
  91. struct i2c_client *client;
  92. struct gpio_chip gpio_chip;
  93. const char *const *names;
  94. int chip_type;
  95. unsigned long driver_data;
  96. };
  97. static inline struct pca953x_chip *to_pca(struct gpio_chip *gc)
  98. {
  99. return container_of(gc, struct pca953x_chip, gpio_chip);
  100. }
  101. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  102. int off)
  103. {
  104. int ret;
  105. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  106. int offset = off / BANK_SZ;
  107. ret = i2c_smbus_read_byte_data(chip->client,
  108. (reg << bank_shift) + offset);
  109. *val = ret;
  110. if (ret < 0) {
  111. dev_err(&chip->client->dev, "failed reading register\n");
  112. return ret;
  113. }
  114. return 0;
  115. }
  116. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  117. int off)
  118. {
  119. int ret = 0;
  120. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  121. int offset = off / BANK_SZ;
  122. ret = i2c_smbus_write_byte_data(chip->client,
  123. (reg << bank_shift) + offset, val);
  124. if (ret < 0) {
  125. dev_err(&chip->client->dev, "failed writing register\n");
  126. return ret;
  127. }
  128. return 0;
  129. }
  130. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  131. {
  132. int ret = 0;
  133. if (chip->gpio_chip.ngpio <= 8)
  134. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  135. else if (chip->gpio_chip.ngpio >= 24) {
  136. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  137. ret = i2c_smbus_write_i2c_block_data(chip->client,
  138. (reg << bank_shift) | REG_ADDR_AI,
  139. NBANK(chip), val);
  140. } else {
  141. switch (chip->chip_type) {
  142. case PCA953X_TYPE:
  143. ret = i2c_smbus_write_word_data(chip->client,
  144. reg << 1, (u16) *val);
  145. break;
  146. case PCA957X_TYPE:
  147. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  148. val[0]);
  149. if (ret < 0)
  150. break;
  151. ret = i2c_smbus_write_byte_data(chip->client,
  152. (reg << 1) + 1,
  153. val[1]);
  154. break;
  155. }
  156. }
  157. if (ret < 0) {
  158. dev_err(&chip->client->dev, "failed writing register\n");
  159. return ret;
  160. }
  161. return 0;
  162. }
  163. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  164. {
  165. int ret;
  166. if (chip->gpio_chip.ngpio <= 8) {
  167. ret = i2c_smbus_read_byte_data(chip->client, reg);
  168. *val = ret;
  169. } else if (chip->gpio_chip.ngpio >= 24) {
  170. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  171. ret = i2c_smbus_read_i2c_block_data(chip->client,
  172. (reg << bank_shift) | REG_ADDR_AI,
  173. NBANK(chip), val);
  174. } else {
  175. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  176. val[0] = (u16)ret & 0xFF;
  177. val[1] = (u16)ret >> 8;
  178. }
  179. if (ret < 0) {
  180. dev_err(&chip->client->dev, "failed reading register\n");
  181. return ret;
  182. }
  183. return 0;
  184. }
  185. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  186. {
  187. struct pca953x_chip *chip = to_pca(gc);
  188. u8 reg_val;
  189. int ret, offset = 0;
  190. mutex_lock(&chip->i2c_lock);
  191. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  192. switch (chip->chip_type) {
  193. case PCA953X_TYPE:
  194. offset = PCA953X_DIRECTION;
  195. break;
  196. case PCA957X_TYPE:
  197. offset = PCA957X_CFG;
  198. break;
  199. }
  200. ret = pca953x_write_single(chip, offset, reg_val, off);
  201. if (ret)
  202. goto exit;
  203. chip->reg_direction[off / BANK_SZ] = reg_val;
  204. ret = 0;
  205. exit:
  206. mutex_unlock(&chip->i2c_lock);
  207. return ret;
  208. }
  209. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  210. unsigned off, int val)
  211. {
  212. struct pca953x_chip *chip = to_pca(gc);
  213. u8 reg_val;
  214. int ret, offset = 0;
  215. mutex_lock(&chip->i2c_lock);
  216. /* set output level */
  217. if (val)
  218. reg_val = chip->reg_output[off / BANK_SZ]
  219. | (1u << (off % BANK_SZ));
  220. else
  221. reg_val = chip->reg_output[off / BANK_SZ]
  222. & ~(1u << (off % BANK_SZ));
  223. switch (chip->chip_type) {
  224. case PCA953X_TYPE:
  225. offset = PCA953X_OUTPUT;
  226. break;
  227. case PCA957X_TYPE:
  228. offset = PCA957X_OUT;
  229. break;
  230. }
  231. ret = pca953x_write_single(chip, offset, reg_val, off);
  232. if (ret)
  233. goto exit;
  234. chip->reg_output[off / BANK_SZ] = reg_val;
  235. /* then direction */
  236. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  237. switch (chip->chip_type) {
  238. case PCA953X_TYPE:
  239. offset = PCA953X_DIRECTION;
  240. break;
  241. case PCA957X_TYPE:
  242. offset = PCA957X_CFG;
  243. break;
  244. }
  245. ret = pca953x_write_single(chip, offset, reg_val, off);
  246. if (ret)
  247. goto exit;
  248. chip->reg_direction[off / BANK_SZ] = reg_val;
  249. ret = 0;
  250. exit:
  251. mutex_unlock(&chip->i2c_lock);
  252. return ret;
  253. }
  254. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  255. {
  256. struct pca953x_chip *chip = to_pca(gc);
  257. u32 reg_val;
  258. int ret, offset = 0;
  259. mutex_lock(&chip->i2c_lock);
  260. switch (chip->chip_type) {
  261. case PCA953X_TYPE:
  262. offset = PCA953X_INPUT;
  263. break;
  264. case PCA957X_TYPE:
  265. offset = PCA957X_IN;
  266. break;
  267. }
  268. ret = pca953x_read_single(chip, offset, &reg_val, off);
  269. mutex_unlock(&chip->i2c_lock);
  270. if (ret < 0) {
  271. /* NOTE: diagnostic already emitted; that's all we should
  272. * do unless gpio_*_value_cansleep() calls become different
  273. * from their nonsleeping siblings (and report faults).
  274. */
  275. return 0;
  276. }
  277. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  278. }
  279. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  280. {
  281. struct pca953x_chip *chip = to_pca(gc);
  282. u8 reg_val;
  283. int ret, offset = 0;
  284. mutex_lock(&chip->i2c_lock);
  285. if (val)
  286. reg_val = chip->reg_output[off / BANK_SZ]
  287. | (1u << (off % BANK_SZ));
  288. else
  289. reg_val = chip->reg_output[off / BANK_SZ]
  290. & ~(1u << (off % BANK_SZ));
  291. switch (chip->chip_type) {
  292. case PCA953X_TYPE:
  293. offset = PCA953X_OUTPUT;
  294. break;
  295. case PCA957X_TYPE:
  296. offset = PCA957X_OUT;
  297. break;
  298. }
  299. ret = pca953x_write_single(chip, offset, reg_val, off);
  300. if (ret)
  301. goto exit;
  302. chip->reg_output[off / BANK_SZ] = reg_val;
  303. exit:
  304. mutex_unlock(&chip->i2c_lock);
  305. }
  306. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  307. {
  308. struct gpio_chip *gc;
  309. gc = &chip->gpio_chip;
  310. gc->direction_input = pca953x_gpio_direction_input;
  311. gc->direction_output = pca953x_gpio_direction_output;
  312. gc->get = pca953x_gpio_get_value;
  313. gc->set = pca953x_gpio_set_value;
  314. gc->can_sleep = true;
  315. gc->base = chip->gpio_start;
  316. gc->ngpio = gpios;
  317. gc->label = chip->client->name;
  318. gc->dev = &chip->client->dev;
  319. gc->owner = THIS_MODULE;
  320. gc->names = chip->names;
  321. }
  322. #ifdef CONFIG_GPIO_PCA953X_IRQ
  323. static void pca953x_irq_mask(struct irq_data *d)
  324. {
  325. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  326. struct pca953x_chip *chip = to_pca(gc);
  327. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  328. }
  329. static void pca953x_irq_unmask(struct irq_data *d)
  330. {
  331. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  332. struct pca953x_chip *chip = to_pca(gc);
  333. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  334. }
  335. static void pca953x_irq_bus_lock(struct irq_data *d)
  336. {
  337. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  338. struct pca953x_chip *chip = to_pca(gc);
  339. mutex_lock(&chip->irq_lock);
  340. }
  341. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  342. {
  343. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  344. struct pca953x_chip *chip = to_pca(gc);
  345. u8 new_irqs;
  346. int level, i;
  347. /* Look for any newly setup interrupt */
  348. for (i = 0; i < NBANK(chip); i++) {
  349. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  350. new_irqs &= ~chip->reg_direction[i];
  351. while (new_irqs) {
  352. level = __ffs(new_irqs);
  353. pca953x_gpio_direction_input(&chip->gpio_chip,
  354. level + (BANK_SZ * i));
  355. new_irqs &= ~(1 << level);
  356. }
  357. }
  358. mutex_unlock(&chip->irq_lock);
  359. }
  360. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  361. {
  362. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  363. struct pca953x_chip *chip = to_pca(gc);
  364. int bank_nb = d->hwirq / BANK_SZ;
  365. u8 mask = 1 << (d->hwirq % BANK_SZ);
  366. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  367. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  368. d->irq, type);
  369. return -EINVAL;
  370. }
  371. if (type & IRQ_TYPE_EDGE_FALLING)
  372. chip->irq_trig_fall[bank_nb] |= mask;
  373. else
  374. chip->irq_trig_fall[bank_nb] &= ~mask;
  375. if (type & IRQ_TYPE_EDGE_RISING)
  376. chip->irq_trig_raise[bank_nb] |= mask;
  377. else
  378. chip->irq_trig_raise[bank_nb] &= ~mask;
  379. return 0;
  380. }
  381. static struct irq_chip pca953x_irq_chip = {
  382. .name = "pca953x",
  383. .irq_mask = pca953x_irq_mask,
  384. .irq_unmask = pca953x_irq_unmask,
  385. .irq_bus_lock = pca953x_irq_bus_lock,
  386. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  387. .irq_set_type = pca953x_irq_set_type,
  388. };
  389. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  390. {
  391. u8 cur_stat[MAX_BANK];
  392. u8 old_stat[MAX_BANK];
  393. bool pending_seen = false;
  394. bool trigger_seen = false;
  395. u8 trigger[MAX_BANK];
  396. int ret, i, offset = 0;
  397. switch (chip->chip_type) {
  398. case PCA953X_TYPE:
  399. offset = PCA953X_INPUT;
  400. break;
  401. case PCA957X_TYPE:
  402. offset = PCA957X_IN;
  403. break;
  404. }
  405. ret = pca953x_read_regs(chip, offset, cur_stat);
  406. if (ret)
  407. return false;
  408. /* Remove output pins from the equation */
  409. for (i = 0; i < NBANK(chip); i++)
  410. cur_stat[i] &= chip->reg_direction[i];
  411. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  412. for (i = 0; i < NBANK(chip); i++) {
  413. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  414. if (trigger[i])
  415. trigger_seen = true;
  416. }
  417. if (!trigger_seen)
  418. return false;
  419. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  420. for (i = 0; i < NBANK(chip); i++) {
  421. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  422. (cur_stat[i] & chip->irq_trig_raise[i]);
  423. pending[i] &= trigger[i];
  424. if (pending[i])
  425. pending_seen = true;
  426. }
  427. return pending_seen;
  428. }
  429. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  430. {
  431. struct pca953x_chip *chip = devid;
  432. u8 pending[MAX_BANK];
  433. u8 level;
  434. unsigned nhandled = 0;
  435. int i;
  436. if (!pca953x_irq_pending(chip, pending))
  437. return IRQ_NONE;
  438. for (i = 0; i < NBANK(chip); i++) {
  439. while (pending[i]) {
  440. level = __ffs(pending[i]);
  441. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  442. level + (BANK_SZ * i)));
  443. pending[i] &= ~(1 << level);
  444. nhandled++;
  445. }
  446. }
  447. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  448. }
  449. static int pca953x_irq_setup(struct pca953x_chip *chip,
  450. int irq_base)
  451. {
  452. struct i2c_client *client = chip->client;
  453. int ret, i, offset = 0;
  454. if (client->irq && irq_base != -1
  455. && (chip->driver_data & PCA_INT)) {
  456. switch (chip->chip_type) {
  457. case PCA953X_TYPE:
  458. offset = PCA953X_INPUT;
  459. break;
  460. case PCA957X_TYPE:
  461. offset = PCA957X_IN;
  462. break;
  463. }
  464. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  465. if (ret)
  466. return ret;
  467. /*
  468. * There is no way to know which GPIO line generated the
  469. * interrupt. We have to rely on the previous read for
  470. * this purpose.
  471. */
  472. for (i = 0; i < NBANK(chip); i++)
  473. chip->irq_stat[i] &= chip->reg_direction[i];
  474. mutex_init(&chip->irq_lock);
  475. ret = devm_request_threaded_irq(&client->dev,
  476. client->irq,
  477. NULL,
  478. pca953x_irq_handler,
  479. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  480. IRQF_SHARED,
  481. dev_name(&client->dev), chip);
  482. if (ret) {
  483. dev_err(&client->dev, "failed to request irq %d\n",
  484. client->irq);
  485. return ret;
  486. }
  487. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  488. &pca953x_irq_chip,
  489. irq_base,
  490. handle_simple_irq,
  491. IRQ_TYPE_NONE);
  492. if (ret) {
  493. dev_err(&client->dev,
  494. "could not connect irqchip to gpiochip\n");
  495. return ret;
  496. }
  497. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  498. &pca953x_irq_chip,
  499. client->irq, NULL);
  500. }
  501. return 0;
  502. }
  503. #else /* CONFIG_GPIO_PCA953X_IRQ */
  504. static int pca953x_irq_setup(struct pca953x_chip *chip,
  505. int irq_base)
  506. {
  507. struct i2c_client *client = chip->client;
  508. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  509. dev_warn(&client->dev, "interrupt support not compiled in\n");
  510. return 0;
  511. }
  512. #endif
  513. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  514. {
  515. int ret;
  516. u8 val[MAX_BANK];
  517. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  518. if (ret)
  519. goto out;
  520. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  521. chip->reg_direction);
  522. if (ret)
  523. goto out;
  524. /* set platform specific polarity inversion */
  525. if (invert)
  526. memset(val, 0xFF, NBANK(chip));
  527. else
  528. memset(val, 0, NBANK(chip));
  529. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  530. out:
  531. return ret;
  532. }
  533. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  534. {
  535. int ret;
  536. u8 val[MAX_BANK];
  537. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  538. if (ret)
  539. goto out;
  540. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  541. if (ret)
  542. goto out;
  543. /* set platform specific polarity inversion */
  544. if (invert)
  545. memset(val, 0xFF, NBANK(chip));
  546. else
  547. memset(val, 0, NBANK(chip));
  548. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  549. if (ret)
  550. goto out;
  551. /* To enable register 6, 7 to control pull up and pull down */
  552. memset(val, 0x02, NBANK(chip));
  553. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  554. if (ret)
  555. goto out;
  556. return 0;
  557. out:
  558. return ret;
  559. }
  560. static int pca953x_probe(struct i2c_client *client,
  561. const struct i2c_device_id *id)
  562. {
  563. struct pca953x_platform_data *pdata;
  564. struct pca953x_chip *chip;
  565. int irq_base = 0;
  566. int ret;
  567. u32 invert = 0;
  568. chip = devm_kzalloc(&client->dev,
  569. sizeof(struct pca953x_chip), GFP_KERNEL);
  570. if (chip == NULL)
  571. return -ENOMEM;
  572. pdata = dev_get_platdata(&client->dev);
  573. if (pdata) {
  574. irq_base = pdata->irq_base;
  575. chip->gpio_start = pdata->gpio_base;
  576. invert = pdata->invert;
  577. chip->names = pdata->names;
  578. } else {
  579. chip->gpio_start = -1;
  580. irq_base = 0;
  581. }
  582. chip->client = client;
  583. if (id) {
  584. chip->driver_data = id->driver_data;
  585. } else {
  586. const struct acpi_device_id *id;
  587. id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  588. if (!id)
  589. return -ENODEV;
  590. chip->driver_data = id->driver_data;
  591. }
  592. chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
  593. mutex_init(&chip->i2c_lock);
  594. /* initialize cached registers from their original values.
  595. * we can't share this chip with another i2c master.
  596. */
  597. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  598. if (chip->chip_type == PCA953X_TYPE)
  599. ret = device_pca953x_init(chip, invert);
  600. else
  601. ret = device_pca957x_init(chip, invert);
  602. if (ret)
  603. return ret;
  604. ret = gpiochip_add(&chip->gpio_chip);
  605. if (ret)
  606. return ret;
  607. ret = pca953x_irq_setup(chip, irq_base);
  608. if (ret)
  609. return ret;
  610. if (pdata && pdata->setup) {
  611. ret = pdata->setup(client, chip->gpio_chip.base,
  612. chip->gpio_chip.ngpio, pdata->context);
  613. if (ret < 0)
  614. dev_warn(&client->dev, "setup failed, %d\n", ret);
  615. }
  616. i2c_set_clientdata(client, chip);
  617. return 0;
  618. }
  619. static int pca953x_remove(struct i2c_client *client)
  620. {
  621. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  622. struct pca953x_chip *chip = i2c_get_clientdata(client);
  623. int ret = 0;
  624. if (pdata && pdata->teardown) {
  625. ret = pdata->teardown(client, chip->gpio_chip.base,
  626. chip->gpio_chip.ngpio, pdata->context);
  627. if (ret < 0) {
  628. dev_err(&client->dev, "%s failed, %d\n",
  629. "teardown", ret);
  630. return ret;
  631. }
  632. }
  633. gpiochip_remove(&chip->gpio_chip);
  634. return 0;
  635. }
  636. static const struct of_device_id pca953x_dt_ids[] = {
  637. { .compatible = "nxp,pca9505", },
  638. { .compatible = "nxp,pca9534", },
  639. { .compatible = "nxp,pca9535", },
  640. { .compatible = "nxp,pca9536", },
  641. { .compatible = "nxp,pca9537", },
  642. { .compatible = "nxp,pca9538", },
  643. { .compatible = "nxp,pca9539", },
  644. { .compatible = "nxp,pca9554", },
  645. { .compatible = "nxp,pca9555", },
  646. { .compatible = "nxp,pca9556", },
  647. { .compatible = "nxp,pca9557", },
  648. { .compatible = "nxp,pca9574", },
  649. { .compatible = "nxp,pca9575", },
  650. { .compatible = "nxp,pca9698", },
  651. { .compatible = "maxim,max7310", },
  652. { .compatible = "maxim,max7312", },
  653. { .compatible = "maxim,max7313", },
  654. { .compatible = "maxim,max7315", },
  655. { .compatible = "ti,pca6107", },
  656. { .compatible = "ti,tca6408", },
  657. { .compatible = "ti,tca6416", },
  658. { .compatible = "ti,tca6424", },
  659. { .compatible = "exar,xra1202", },
  660. { }
  661. };
  662. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  663. static struct i2c_driver pca953x_driver = {
  664. .driver = {
  665. .name = "pca953x",
  666. .of_match_table = pca953x_dt_ids,
  667. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  668. },
  669. .probe = pca953x_probe,
  670. .remove = pca953x_remove,
  671. .id_table = pca953x_id,
  672. };
  673. static int __init pca953x_init(void)
  674. {
  675. return i2c_add_driver(&pca953x_driver);
  676. }
  677. /* register after i2c postcore initcall and before
  678. * subsys initcalls that may rely on these GPIOs
  679. */
  680. subsys_initcall(pca953x_init);
  681. static void __exit pca953x_exit(void)
  682. {
  683. i2c_del_driver(&pca953x_driver);
  684. }
  685. module_exit(pca953x_exit);
  686. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  687. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  688. MODULE_LICENSE("GPL");