tonga_smc.c 22 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/firmware.h>
  24. #include "drmP.h"
  25. #include "amdgpu.h"
  26. #include "tonga_ppsmc.h"
  27. #include "tonga_smumgr.h"
  28. #include "smu_ucode_xfer_vi.h"
  29. #include "amdgpu_ucode.h"
  30. #include "smu/smu_7_1_2_d.h"
  31. #include "smu/smu_7_1_2_sh_mask.h"
  32. #define TONGA_SMC_SIZE 0x20000
  33. static int tonga_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t limit)
  34. {
  35. uint32_t val;
  36. if (smc_address & 3)
  37. return -EINVAL;
  38. if ((smc_address + 3) > limit)
  39. return -EINVAL;
  40. WREG32(mmSMC_IND_INDEX_0, smc_address);
  41. val = RREG32(mmSMC_IND_ACCESS_CNTL);
  42. val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
  43. WREG32(mmSMC_IND_ACCESS_CNTL, val);
  44. return 0;
  45. }
  46. static int tonga_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit)
  47. {
  48. uint32_t addr;
  49. uint32_t data, orig_data;
  50. int result = 0;
  51. uint32_t extra_shift;
  52. unsigned long flags;
  53. if (smc_start_address & 3)
  54. return -EINVAL;
  55. if ((smc_start_address + byte_count) > limit)
  56. return -EINVAL;
  57. addr = smc_start_address;
  58. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  59. while (byte_count >= 4) {
  60. /* Bytes are written into the SMC addres space with the MSB first */
  61. data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
  62. result = tonga_set_smc_sram_address(adev, addr, limit);
  63. if (result)
  64. goto out;
  65. WREG32(mmSMC_IND_DATA_0, data);
  66. src += 4;
  67. byte_count -= 4;
  68. addr += 4;
  69. }
  70. if (0 != byte_count) {
  71. /* Now write odd bytes left, do a read modify write cycle */
  72. data = 0;
  73. result = tonga_set_smc_sram_address(adev, addr, limit);
  74. if (result)
  75. goto out;
  76. orig_data = RREG32(mmSMC_IND_DATA_0);
  77. extra_shift = 8 * (4 - byte_count);
  78. while (byte_count > 0) {
  79. data = (data << 8) + *src++;
  80. byte_count--;
  81. }
  82. data <<= extra_shift;
  83. data |= (orig_data & ~((~0UL) << extra_shift));
  84. result = tonga_set_smc_sram_address(adev, addr, limit);
  85. if (result)
  86. goto out;
  87. WREG32(mmSMC_IND_DATA_0, data);
  88. }
  89. out:
  90. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  91. return result;
  92. }
  93. static int tonga_program_jump_on_start(struct amdgpu_device *adev)
  94. {
  95. static unsigned char data[] = {0xE0, 0x00, 0x80, 0x40};
  96. tonga_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
  97. return 0;
  98. }
  99. static bool tonga_is_smc_ram_running(struct amdgpu_device *adev)
  100. {
  101. uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
  102. val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);
  103. return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));
  104. }
  105. static int wait_smu_response(struct amdgpu_device *adev)
  106. {
  107. int i;
  108. uint32_t val;
  109. for (i = 0; i < adev->usec_timeout; i++) {
  110. val = RREG32(mmSMC_RESP_0);
  111. if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))
  112. break;
  113. udelay(1);
  114. }
  115. if (i == adev->usec_timeout)
  116. return -EINVAL;
  117. return 0;
  118. }
  119. static int tonga_send_msg_to_smc_offset(struct amdgpu_device *adev)
  120. {
  121. if (wait_smu_response(adev)) {
  122. DRM_ERROR("Failed to send previous message\n");
  123. return -EINVAL;
  124. }
  125. WREG32(mmSMC_MSG_ARG_0, 0x20000);
  126. WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_Test);
  127. if (wait_smu_response(adev)) {
  128. DRM_ERROR("Failed to send message\n");
  129. return -EINVAL;
  130. }
  131. return 0;
  132. }
  133. static int tonga_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
  134. {
  135. if (!tonga_is_smc_ram_running(adev))
  136. {
  137. return -EINVAL;;
  138. }
  139. if (wait_smu_response(adev)) {
  140. DRM_ERROR("Failed to send previous message\n");
  141. return -EINVAL;
  142. }
  143. WREG32(mmSMC_MESSAGE_0, msg);
  144. if (wait_smu_response(adev)) {
  145. DRM_ERROR("Failed to send message\n");
  146. return -EINVAL;
  147. }
  148. return 0;
  149. }
  150. static int tonga_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,
  151. PPSMC_Msg msg)
  152. {
  153. if (wait_smu_response(adev)) {
  154. DRM_ERROR("Failed to send previous message\n");
  155. return -EINVAL;
  156. }
  157. WREG32(mmSMC_MESSAGE_0, msg);
  158. return 0;
  159. }
  160. static int tonga_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
  161. PPSMC_Msg msg,
  162. uint32_t parameter)
  163. {
  164. if (!tonga_is_smc_ram_running(adev))
  165. return -EINVAL;
  166. if (wait_smu_response(adev)) {
  167. DRM_ERROR("Failed to send previous message\n");
  168. return -EINVAL;
  169. }
  170. WREG32(mmSMC_MSG_ARG_0, parameter);
  171. return tonga_send_msg_to_smc(adev, msg);
  172. }
  173. static int tonga_send_msg_to_smc_with_parameter_without_waiting(
  174. struct amdgpu_device *adev,
  175. PPSMC_Msg msg, uint32_t parameter)
  176. {
  177. if (wait_smu_response(adev)) {
  178. DRM_ERROR("Failed to send previous message\n");
  179. return -EINVAL;
  180. }
  181. WREG32(mmSMC_MSG_ARG_0, parameter);
  182. return tonga_send_msg_to_smc_without_waiting(adev, msg);
  183. }
  184. #if 0 /* not used yet */
  185. static int tonga_wait_for_smc_inactive(struct amdgpu_device *adev)
  186. {
  187. int i;
  188. uint32_t val;
  189. if (!tonga_is_smc_ram_running(adev))
  190. return -EINVAL;
  191. for (i = 0; i < adev->usec_timeout; i++) {
  192. val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
  193. if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
  194. break;
  195. udelay(1);
  196. }
  197. if (i == adev->usec_timeout)
  198. return -EINVAL;
  199. return 0;
  200. }
  201. #endif
  202. static int tonga_smu_upload_firmware_image(struct amdgpu_device *adev)
  203. {
  204. const struct smc_firmware_header_v1_0 *hdr;
  205. uint32_t ucode_size;
  206. uint32_t ucode_start_address;
  207. const uint8_t *src;
  208. uint32_t val;
  209. uint32_t byte_count;
  210. uint32_t *data;
  211. unsigned long flags;
  212. if (!adev->pm.fw)
  213. return -EINVAL;
  214. hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
  215. amdgpu_ucode_print_smc_hdr(&hdr->header);
  216. adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
  217. ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
  218. ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
  219. src = (const uint8_t *)
  220. (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  221. if (ucode_size & 3) {
  222. DRM_ERROR("SMC ucode is not 4 bytes aligned\n");
  223. return -EINVAL;
  224. }
  225. if (ucode_size > TONGA_SMC_SIZE) {
  226. DRM_ERROR("SMC address is beyond the SMC RAM area\n");
  227. return -EINVAL;
  228. }
  229. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  230. WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
  231. val = RREG32(mmSMC_IND_ACCESS_CNTL);
  232. val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
  233. WREG32(mmSMC_IND_ACCESS_CNTL, val);
  234. byte_count = ucode_size;
  235. data = (uint32_t *)src;
  236. for (; byte_count >= 4; data++, byte_count -= 4)
  237. WREG32(mmSMC_IND_DATA_0, data[0]);
  238. val = RREG32(mmSMC_IND_ACCESS_CNTL);
  239. val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
  240. WREG32(mmSMC_IND_ACCESS_CNTL, val);
  241. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  242. return 0;
  243. }
  244. #if 0 /* not used yet */
  245. static int tonga_read_smc_sram_dword(struct amdgpu_device *adev,
  246. uint32_t smc_address,
  247. uint32_t *value,
  248. uint32_t limit)
  249. {
  250. int result;
  251. unsigned long flags;
  252. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  253. result = tonga_set_smc_sram_address(adev, smc_address, limit);
  254. if (result == 0)
  255. *value = RREG32(mmSMC_IND_DATA_0);
  256. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  257. return result;
  258. }
  259. static int tonga_write_smc_sram_dword(struct amdgpu_device *adev,
  260. uint32_t smc_address,
  261. uint32_t value,
  262. uint32_t limit)
  263. {
  264. int result;
  265. unsigned long flags;
  266. spin_lock_irqsave(&adev->smc_idx_lock, flags);
  267. result = tonga_set_smc_sram_address(adev, smc_address, limit);
  268. if (result == 0)
  269. WREG32(mmSMC_IND_DATA_0, value);
  270. spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
  271. return result;
  272. }
  273. static int tonga_smu_stop_smc(struct amdgpu_device *adev)
  274. {
  275. uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
  276. val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
  277. WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
  278. val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
  279. val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
  280. WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
  281. return 0;
  282. }
  283. #endif
  284. static enum AMDGPU_UCODE_ID tonga_convert_fw_type(uint32_t fw_type)
  285. {
  286. switch (fw_type) {
  287. case UCODE_ID_SDMA0:
  288. return AMDGPU_UCODE_ID_SDMA0;
  289. case UCODE_ID_SDMA1:
  290. return AMDGPU_UCODE_ID_SDMA1;
  291. case UCODE_ID_CP_CE:
  292. return AMDGPU_UCODE_ID_CP_CE;
  293. case UCODE_ID_CP_PFP:
  294. return AMDGPU_UCODE_ID_CP_PFP;
  295. case UCODE_ID_CP_ME:
  296. return AMDGPU_UCODE_ID_CP_ME;
  297. case UCODE_ID_CP_MEC:
  298. case UCODE_ID_CP_MEC_JT1:
  299. return AMDGPU_UCODE_ID_CP_MEC1;
  300. case UCODE_ID_CP_MEC_JT2:
  301. return AMDGPU_UCODE_ID_CP_MEC2;
  302. case UCODE_ID_RLC_G:
  303. return AMDGPU_UCODE_ID_RLC_G;
  304. default:
  305. DRM_ERROR("ucode type is out of range!\n");
  306. return AMDGPU_UCODE_ID_MAXIMUM;
  307. }
  308. }
  309. static int tonga_smu_populate_single_firmware_entry(struct amdgpu_device *adev,
  310. uint32_t fw_type,
  311. struct SMU_Entry *entry)
  312. {
  313. enum AMDGPU_UCODE_ID id = tonga_convert_fw_type(fw_type);
  314. struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];
  315. const struct gfx_firmware_header_v1_0 *header = NULL;
  316. uint64_t gpu_addr;
  317. uint32_t data_size;
  318. if (ucode->fw == NULL)
  319. return -EINVAL;
  320. gpu_addr = ucode->mc_addr;
  321. header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
  322. data_size = le32_to_cpu(header->header.ucode_size_bytes);
  323. if ((fw_type == UCODE_ID_CP_MEC_JT1) ||
  324. (fw_type == UCODE_ID_CP_MEC_JT2)) {
  325. gpu_addr += le32_to_cpu(header->jt_offset) << 2;
  326. data_size = le32_to_cpu(header->jt_size) << 2;
  327. }
  328. entry->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
  329. entry->id = (uint16_t)fw_type;
  330. entry->image_addr_high = upper_32_bits(gpu_addr);
  331. entry->image_addr_low = lower_32_bits(gpu_addr);
  332. entry->meta_data_addr_high = 0;
  333. entry->meta_data_addr_low = 0;
  334. entry->data_size_byte = data_size;
  335. entry->num_register_entries = 0;
  336. if (fw_type == UCODE_ID_RLC_G)
  337. entry->flags = 1;
  338. else
  339. entry->flags = 0;
  340. return 0;
  341. }
  342. static int tonga_smu_request_load_fw(struct amdgpu_device *adev)
  343. {
  344. struct tonga_smu_private_data *private = (struct tonga_smu_private_data *)adev->smu.priv;
  345. struct SMU_DRAMData_TOC *toc;
  346. uint32_t fw_to_load;
  347. WREG32_SMC(ixSOFT_REGISTERS_TABLE_28, 0);
  348. tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_high);
  349. tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low);
  350. toc = (struct SMU_DRAMData_TOC *)private->header;
  351. toc->num_entries = 0;
  352. toc->structure_version = 1;
  353. if (!adev->firmware.smu_load)
  354. return 0;
  355. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,
  356. &toc->entry[toc->num_entries++])) {
  357. DRM_ERROR("Failed to get firmware entry for RLC\n");
  358. return -EINVAL;
  359. }
  360. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,
  361. &toc->entry[toc->num_entries++])) {
  362. DRM_ERROR("Failed to get firmware entry for CE\n");
  363. return -EINVAL;
  364. }
  365. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,
  366. &toc->entry[toc->num_entries++])) {
  367. DRM_ERROR("Failed to get firmware entry for PFP\n");
  368. return -EINVAL;
  369. }
  370. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,
  371. &toc->entry[toc->num_entries++])) {
  372. DRM_ERROR("Failed to get firmware entry for ME\n");
  373. return -EINVAL;
  374. }
  375. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,
  376. &toc->entry[toc->num_entries++])) {
  377. DRM_ERROR("Failed to get firmware entry for MEC\n");
  378. return -EINVAL;
  379. }
  380. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,
  381. &toc->entry[toc->num_entries++])) {
  382. DRM_ERROR("Failed to get firmware entry for MEC_JT1\n");
  383. return -EINVAL;
  384. }
  385. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
  386. &toc->entry[toc->num_entries++])) {
  387. DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
  388. return -EINVAL;
  389. }
  390. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
  391. &toc->entry[toc->num_entries++])) {
  392. DRM_ERROR("Failed to get firmware entry for SDMA0\n");
  393. return -EINVAL;
  394. }
  395. if (tonga_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,
  396. &toc->entry[toc->num_entries++])) {
  397. DRM_ERROR("Failed to get firmware entry for SDMA1\n");
  398. return -EINVAL;
  399. }
  400. tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);
  401. tonga_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);
  402. fw_to_load = UCODE_ID_RLC_G_MASK |
  403. UCODE_ID_SDMA0_MASK |
  404. UCODE_ID_SDMA1_MASK |
  405. UCODE_ID_CP_CE_MASK |
  406. UCODE_ID_CP_ME_MASK |
  407. UCODE_ID_CP_PFP_MASK |
  408. UCODE_ID_CP_MEC_MASK;
  409. if (tonga_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
  410. DRM_ERROR("Fail to request SMU load ucode\n");
  411. return -EINVAL;
  412. }
  413. return 0;
  414. }
  415. static uint32_t tonga_smu_get_mask_for_fw_type(uint32_t fw_type)
  416. {
  417. switch (fw_type) {
  418. case AMDGPU_UCODE_ID_SDMA0:
  419. return UCODE_ID_SDMA0_MASK;
  420. case AMDGPU_UCODE_ID_SDMA1:
  421. return UCODE_ID_SDMA1_MASK;
  422. case AMDGPU_UCODE_ID_CP_CE:
  423. return UCODE_ID_CP_CE_MASK;
  424. case AMDGPU_UCODE_ID_CP_PFP:
  425. return UCODE_ID_CP_PFP_MASK;
  426. case AMDGPU_UCODE_ID_CP_ME:
  427. return UCODE_ID_CP_ME_MASK;
  428. case AMDGPU_UCODE_ID_CP_MEC1:
  429. return UCODE_ID_CP_MEC_MASK;
  430. case AMDGPU_UCODE_ID_CP_MEC2:
  431. return UCODE_ID_CP_MEC_MASK;
  432. case AMDGPU_UCODE_ID_RLC_G:
  433. return UCODE_ID_RLC_G_MASK;
  434. default:
  435. DRM_ERROR("ucode type is out of range!\n");
  436. return 0;
  437. }
  438. }
  439. static int tonga_smu_check_fw_load_finish(struct amdgpu_device *adev,
  440. uint32_t fw_type)
  441. {
  442. uint32_t fw_mask = tonga_smu_get_mask_for_fw_type(fw_type);
  443. int i;
  444. for (i = 0; i < adev->usec_timeout; i++) {
  445. if (fw_mask == (RREG32_SMC(ixSOFT_REGISTERS_TABLE_28) & fw_mask))
  446. break;
  447. udelay(1);
  448. }
  449. if (i == adev->usec_timeout) {
  450. DRM_ERROR("check firmware loading failed\n");
  451. return -EINVAL;
  452. }
  453. return 0;
  454. }
  455. static int tonga_smu_start_in_protection_mode(struct amdgpu_device *adev)
  456. {
  457. int result;
  458. uint32_t val;
  459. int i;
  460. /* Assert reset */
  461. val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
  462. val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
  463. WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
  464. result = tonga_smu_upload_firmware_image(adev);
  465. if (result)
  466. return result;
  467. /* Clear status */
  468. WREG32_SMC(ixSMU_STATUS, 0);
  469. /* Enable clock */
  470. val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
  471. val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
  472. WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
  473. /* De-assert reset */
  474. val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
  475. val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
  476. WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
  477. /* Set SMU Auto Start */
  478. val = RREG32_SMC(ixSMU_INPUT_DATA);
  479. val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1);
  480. WREG32_SMC(ixSMU_INPUT_DATA, val);
  481. /* Clear firmware interrupt enable flag */
  482. WREG32_SMC(ixFIRMWARE_FLAGS, 0);
  483. for (i = 0; i < adev->usec_timeout; i++) {
  484. val = RREG32_SMC(ixRCU_UC_EVENTS);
  485. if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED))
  486. break;
  487. udelay(1);
  488. }
  489. if (i == adev->usec_timeout) {
  490. DRM_ERROR("Interrupt is not enabled by firmware\n");
  491. return -EINVAL;
  492. }
  493. /* Call Test SMU message with 0x20000 offset
  494. * to trigger SMU start
  495. */
  496. tonga_send_msg_to_smc_offset(adev);
  497. /* Wait for done bit to be set */
  498. for (i = 0; i < adev->usec_timeout; i++) {
  499. val = RREG32_SMC(ixSMU_STATUS);
  500. if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE))
  501. break;
  502. udelay(1);
  503. }
  504. if (i == adev->usec_timeout) {
  505. DRM_ERROR("Timeout for SMU start\n");
  506. return -EINVAL;
  507. }
  508. /* Check pass/failed indicator */
  509. val = RREG32_SMC(ixSMU_STATUS);
  510. if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) {
  511. DRM_ERROR("SMU Firmware start failed\n");
  512. return -EINVAL;
  513. }
  514. /* Wait for firmware to initialize */
  515. for (i = 0; i < adev->usec_timeout; i++) {
  516. val = RREG32_SMC(ixFIRMWARE_FLAGS);
  517. if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
  518. break;
  519. udelay(1);
  520. }
  521. if (i == adev->usec_timeout) {
  522. DRM_ERROR("SMU firmware initialization failed\n");
  523. return -EINVAL;
  524. }
  525. return 0;
  526. }
  527. static int tonga_smu_start_in_non_protection_mode(struct amdgpu_device *adev)
  528. {
  529. int i, result;
  530. uint32_t val;
  531. /* wait for smc boot up */
  532. for (i = 0; i < adev->usec_timeout; i++) {
  533. val = RREG32_SMC(ixRCU_UC_EVENTS);
  534. val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done);
  535. if (val)
  536. break;
  537. udelay(1);
  538. }
  539. if (i == adev->usec_timeout) {
  540. DRM_ERROR("SMC boot sequence is not completed\n");
  541. return -EINVAL;
  542. }
  543. /* Clear firmware interrupt enable flag */
  544. WREG32_SMC(ixFIRMWARE_FLAGS, 0);
  545. /* Assert reset */
  546. val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
  547. val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
  548. WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
  549. result = tonga_smu_upload_firmware_image(adev);
  550. if (result)
  551. return result;
  552. /* Set smc instruct start point at 0x0 */
  553. tonga_program_jump_on_start(adev);
  554. /* Enable clock */
  555. val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
  556. val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
  557. WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
  558. /* De-assert reset */
  559. val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
  560. val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
  561. WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
  562. /* Wait for firmware to initialize */
  563. for (i = 0; i < adev->usec_timeout; i++) {
  564. val = RREG32_SMC(ixFIRMWARE_FLAGS);
  565. if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))
  566. break;
  567. udelay(1);
  568. }
  569. if (i == adev->usec_timeout) {
  570. DRM_ERROR("Timeout for SMC firmware initialization\n");
  571. return -EINVAL;
  572. }
  573. return 0;
  574. }
  575. int tonga_smu_start(struct amdgpu_device *adev)
  576. {
  577. int result;
  578. uint32_t val;
  579. if (!tonga_is_smc_ram_running(adev)) {
  580. val = RREG32_SMC(ixSMU_FIRMWARE);
  581. if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) {
  582. result = tonga_smu_start_in_non_protection_mode(adev);
  583. if (result)
  584. return result;
  585. } else {
  586. result = tonga_smu_start_in_protection_mode(adev);
  587. if (result)
  588. return result;
  589. }
  590. }
  591. return tonga_smu_request_load_fw(adev);
  592. }
  593. static const struct amdgpu_smumgr_funcs tonga_smumgr_funcs = {
  594. .check_fw_load_finish = tonga_smu_check_fw_load_finish,
  595. .request_smu_load_fw = NULL,
  596. .request_smu_specific_fw = NULL,
  597. };
  598. int tonga_smu_init(struct amdgpu_device *adev)
  599. {
  600. struct tonga_smu_private_data *private;
  601. uint32_t image_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
  602. uint32_t smu_internal_buffer_size = 200*4096;
  603. struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;
  604. struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;
  605. uint64_t mc_addr;
  606. void *toc_buf_ptr;
  607. void *smu_buf_ptr;
  608. int ret;
  609. private = kzalloc(sizeof(struct tonga_smu_private_data), GFP_KERNEL);
  610. if (NULL == private)
  611. return -ENOMEM;
  612. /* allocate firmware buffers */
  613. if (adev->firmware.smu_load)
  614. amdgpu_ucode_init_bo(adev);
  615. adev->smu.priv = private;
  616. adev->smu.fw_flags = 0;
  617. /* Allocate FW image data structure and header buffer */
  618. ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,
  619. true, AMDGPU_GEM_DOMAIN_VRAM,
  620. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
  621. NULL, NULL, toc_buf);
  622. if (ret) {
  623. DRM_ERROR("Failed to allocate memory for TOC buffer\n");
  624. return -ENOMEM;
  625. }
  626. /* Allocate buffer for SMU internal buffer */
  627. ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE,
  628. true, AMDGPU_GEM_DOMAIN_VRAM,
  629. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
  630. NULL, NULL, smu_buf);
  631. if (ret) {
  632. DRM_ERROR("Failed to allocate memory for SMU internal buffer\n");
  633. return -ENOMEM;
  634. }
  635. /* Retrieve GPU address for header buffer and internal buffer */
  636. ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);
  637. if (ret) {
  638. amdgpu_bo_unref(&adev->smu.toc_buf);
  639. DRM_ERROR("Failed to reserve the TOC buffer\n");
  640. return -EINVAL;
  641. }
  642. ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
  643. if (ret) {
  644. amdgpu_bo_unreserve(adev->smu.toc_buf);
  645. amdgpu_bo_unref(&adev->smu.toc_buf);
  646. DRM_ERROR("Failed to pin the TOC buffer\n");
  647. return -EINVAL;
  648. }
  649. ret = amdgpu_bo_kmap(*toc_buf, &toc_buf_ptr);
  650. if (ret) {
  651. amdgpu_bo_unreserve(adev->smu.toc_buf);
  652. amdgpu_bo_unref(&adev->smu.toc_buf);
  653. DRM_ERROR("Failed to map the TOC buffer\n");
  654. return -EINVAL;
  655. }
  656. amdgpu_bo_unreserve(adev->smu.toc_buf);
  657. private->header_addr_low = lower_32_bits(mc_addr);
  658. private->header_addr_high = upper_32_bits(mc_addr);
  659. private->header = toc_buf_ptr;
  660. ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);
  661. if (ret) {
  662. amdgpu_bo_unref(&adev->smu.smu_buf);
  663. amdgpu_bo_unref(&adev->smu.toc_buf);
  664. DRM_ERROR("Failed to reserve the SMU internal buffer\n");
  665. return -EINVAL;
  666. }
  667. ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);
  668. if (ret) {
  669. amdgpu_bo_unreserve(adev->smu.smu_buf);
  670. amdgpu_bo_unref(&adev->smu.smu_buf);
  671. amdgpu_bo_unref(&adev->smu.toc_buf);
  672. DRM_ERROR("Failed to pin the SMU internal buffer\n");
  673. return -EINVAL;
  674. }
  675. ret = amdgpu_bo_kmap(*smu_buf, &smu_buf_ptr);
  676. if (ret) {
  677. amdgpu_bo_unreserve(adev->smu.smu_buf);
  678. amdgpu_bo_unref(&adev->smu.smu_buf);
  679. amdgpu_bo_unref(&adev->smu.toc_buf);
  680. DRM_ERROR("Failed to map the SMU internal buffer\n");
  681. return -EINVAL;
  682. }
  683. amdgpu_bo_unreserve(adev->smu.smu_buf);
  684. private->smu_buffer_addr_low = lower_32_bits(mc_addr);
  685. private->smu_buffer_addr_high = upper_32_bits(mc_addr);
  686. adev->smu.smumgr_funcs = &tonga_smumgr_funcs;
  687. return 0;
  688. }
  689. int tonga_smu_fini(struct amdgpu_device *adev)
  690. {
  691. amdgpu_bo_unref(&adev->smu.toc_buf);
  692. amdgpu_bo_unref(&adev->smu.smu_buf);
  693. kfree(adev->smu.priv);
  694. adev->smu.priv = NULL;
  695. if (adev->firmware.fw_buf)
  696. amdgpu_ucode_fini_bo(adev);
  697. return 0;
  698. }