fsl_dcu_drm_crtc.c 6.0 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * Freescale DCU drm device driver
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/regmap.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_atomic.h>
  15. #include <drm/drm_atomic_helper.h>
  16. #include <drm/drm_crtc.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include "fsl_dcu_drm_crtc.h"
  19. #include "fsl_dcu_drm_drv.h"
  20. #include "fsl_dcu_drm_plane.h"
  21. static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc,
  22. struct drm_crtc_state *old_crtc_state)
  23. {
  24. }
  25. static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
  26. struct drm_crtc_state *state)
  27. {
  28. return 0;
  29. }
  30. static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  31. struct drm_crtc_state *old_crtc_state)
  32. {
  33. }
  34. static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
  35. {
  36. struct drm_device *dev = crtc->dev;
  37. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  38. int ret;
  39. ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  40. DCU_MODE_DCU_MODE_MASK,
  41. DCU_MODE_DCU_MODE(DCU_MODE_OFF));
  42. if (ret)
  43. dev_err(fsl_dev->dev, "Disable CRTC failed\n");
  44. ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  45. DCU_UPDATE_MODE_READREG);
  46. if (ret)
  47. dev_err(fsl_dev->dev, "Enable CRTC failed\n");
  48. }
  49. static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
  50. {
  51. struct drm_device *dev = crtc->dev;
  52. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  53. int ret;
  54. ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  55. DCU_MODE_DCU_MODE_MASK,
  56. DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
  57. if (ret)
  58. dev_err(fsl_dev->dev, "Enable CRTC failed\n");
  59. ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  60. DCU_UPDATE_MODE_READREG);
  61. if (ret)
  62. dev_err(fsl_dev->dev, "Enable CRTC failed\n");
  63. }
  64. static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
  65. const struct drm_display_mode *mode,
  66. struct drm_display_mode *adjusted_mode)
  67. {
  68. return true;
  69. }
  70. static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
  71. {
  72. struct drm_device *dev = crtc->dev;
  73. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  74. struct drm_display_mode *mode = &crtc->state->mode;
  75. unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index;
  76. unsigned long dcuclk;
  77. int ret;
  78. index = drm_crtc_index(crtc);
  79. dcuclk = clk_get_rate(fsl_dev->clk);
  80. div = dcuclk / mode->clock / 1000;
  81. /* Configure timings: */
  82. hbp = mode->htotal - mode->hsync_end;
  83. hfp = mode->hsync_start - mode->hdisplay;
  84. hsw = mode->hsync_end - mode->hsync_start;
  85. vbp = mode->vtotal - mode->vsync_end;
  86. vfp = mode->vsync_start - mode->vdisplay;
  87. vsw = mode->vsync_end - mode->vsync_start;
  88. ret = regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
  89. DCU_HSYN_PARA_BP(hbp) |
  90. DCU_HSYN_PARA_PW(hsw) |
  91. DCU_HSYN_PARA_FP(hfp));
  92. if (ret)
  93. goto set_failed;
  94. ret = regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
  95. DCU_VSYN_PARA_BP(vbp) |
  96. DCU_VSYN_PARA_PW(vsw) |
  97. DCU_VSYN_PARA_FP(vfp));
  98. if (ret)
  99. goto set_failed;
  100. ret = regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
  101. DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
  102. DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
  103. if (ret)
  104. goto set_failed;
  105. ret = regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
  106. if (ret)
  107. goto set_failed;
  108. ret = regmap_write(fsl_dev->regmap, DCU_SYN_POL,
  109. DCU_SYN_POL_INV_VS_LOW | DCU_SYN_POL_INV_HS_LOW);
  110. if (ret)
  111. goto set_failed;
  112. ret = regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
  113. DCU_BGND_G(0) | DCU_BGND_B(0));
  114. if (ret)
  115. goto set_failed;
  116. ret = regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
  117. DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
  118. if (ret)
  119. goto set_failed;
  120. ret = regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
  121. DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
  122. DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
  123. DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
  124. if (ret)
  125. goto set_failed;
  126. ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  127. DCU_UPDATE_MODE_READREG);
  128. if (ret)
  129. goto set_failed;
  130. return;
  131. set_failed:
  132. dev_err(dev->dev, "set DCU register failed\n");
  133. }
  134. static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
  135. .atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
  136. .atomic_check = fsl_dcu_drm_crtc_atomic_check,
  137. .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
  138. .disable = fsl_dcu_drm_disable_crtc,
  139. .enable = fsl_dcu_drm_crtc_enable,
  140. .mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
  141. .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
  142. };
  143. static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
  144. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  145. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  146. .destroy = drm_crtc_cleanup,
  147. .page_flip = drm_atomic_helper_page_flip,
  148. .reset = drm_atomic_helper_crtc_reset,
  149. .set_config = drm_atomic_helper_set_config,
  150. };
  151. int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
  152. {
  153. struct drm_plane *primary;
  154. struct drm_crtc *crtc = &fsl_dev->crtc;
  155. unsigned int i, j, reg_num;
  156. int ret;
  157. primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
  158. ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
  159. &fsl_dcu_drm_crtc_funcs);
  160. if (ret < 0)
  161. return ret;
  162. drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
  163. if (!strcmp(fsl_dev->soc->name, "ls1021a"))
  164. reg_num = LS1021A_LAYER_REG_NUM;
  165. else
  166. reg_num = VF610_LAYER_REG_NUM;
  167. for (i = 0; i <= fsl_dev->soc->total_layer; i++) {
  168. for (j = 0; j < reg_num; j++) {
  169. ret = regmap_write(fsl_dev->regmap,
  170. DCU_CTRLDESCLN(i, j), 0);
  171. if (ret)
  172. goto init_failed;
  173. }
  174. }
  175. ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  176. DCU_MODE_DCU_MODE_MASK,
  177. DCU_MODE_DCU_MODE(DCU_MODE_OFF));
  178. if (ret)
  179. goto init_failed;
  180. ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  181. DCU_UPDATE_MODE_READREG);
  182. if (ret)
  183. goto init_failed;
  184. return 0;
  185. init_failed:
  186. dev_err(fsl_dev->dev, "init DCU register failed\n");
  187. return ret;
  188. }