intel_gmbus.c 13 KB

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  1. /*
  2. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2008,2010 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. * Chris Wilson <chris@chris-wilson.co.uk>
  28. */
  29. #include <linux/module.h>
  30. #include <linux/i2c.h>
  31. #include <linux/i2c-algo-bit.h>
  32. #include <drm/drmP.h>
  33. #include "psb_intel_drv.h"
  34. #include <drm/gma_drm.h>
  35. #include "psb_drv.h"
  36. #include "psb_intel_reg.h"
  37. #define _wait_for(COND, MS, W) ({ \
  38. unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
  39. int ret__ = 0; \
  40. while (! (COND)) { \
  41. if (time_after(jiffies, timeout__)) { \
  42. ret__ = -ETIMEDOUT; \
  43. break; \
  44. } \
  45. if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
  46. } \
  47. ret__; \
  48. })
  49. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  50. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  51. #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
  52. #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
  53. /* Intel GPIO access functions */
  54. #define I2C_RISEFALL_TIME 20
  55. static inline struct intel_gmbus *
  56. to_intel_gmbus(struct i2c_adapter *i2c)
  57. {
  58. return container_of(i2c, struct intel_gmbus, adapter);
  59. }
  60. struct intel_gpio {
  61. struct i2c_adapter adapter;
  62. struct i2c_algo_bit_data algo;
  63. struct drm_psb_private *dev_priv;
  64. u32 reg;
  65. };
  66. void
  67. gma_intel_i2c_reset(struct drm_device *dev)
  68. {
  69. struct drm_psb_private *dev_priv = dev->dev_private;
  70. GMBUS_REG_WRITE(GMBUS0, 0);
  71. }
  72. static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
  73. {
  74. /* When using bit bashing for I2C, this bit needs to be set to 1 */
  75. /* FIXME: We are never Pineview, right?
  76. u32 val;
  77. if (!IS_PINEVIEW(dev_priv->dev))
  78. return;
  79. val = REG_READ(DSPCLK_GATE_D);
  80. if (enable)
  81. val |= DPCUNIT_CLOCK_GATE_DISABLE;
  82. else
  83. val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  84. REG_WRITE(DSPCLK_GATE_D, val);
  85. return;
  86. */
  87. }
  88. static u32 get_reserved(struct intel_gpio *gpio)
  89. {
  90. struct drm_psb_private *dev_priv = gpio->dev_priv;
  91. u32 reserved = 0;
  92. /* On most chips, these bits must be preserved in software. */
  93. reserved = GMBUS_REG_READ(gpio->reg) &
  94. (GPIO_DATA_PULLUP_DISABLE |
  95. GPIO_CLOCK_PULLUP_DISABLE);
  96. return reserved;
  97. }
  98. static int get_clock(void *data)
  99. {
  100. struct intel_gpio *gpio = data;
  101. struct drm_psb_private *dev_priv = gpio->dev_priv;
  102. u32 reserved = get_reserved(gpio);
  103. GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
  104. GMBUS_REG_WRITE(gpio->reg, reserved);
  105. return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
  106. }
  107. static int get_data(void *data)
  108. {
  109. struct intel_gpio *gpio = data;
  110. struct drm_psb_private *dev_priv = gpio->dev_priv;
  111. u32 reserved = get_reserved(gpio);
  112. GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
  113. GMBUS_REG_WRITE(gpio->reg, reserved);
  114. return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
  115. }
  116. static void set_clock(void *data, int state_high)
  117. {
  118. struct intel_gpio *gpio = data;
  119. struct drm_psb_private *dev_priv = gpio->dev_priv;
  120. u32 reserved = get_reserved(gpio);
  121. u32 clock_bits;
  122. if (state_high)
  123. clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  124. else
  125. clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  126. GPIO_CLOCK_VAL_MASK;
  127. GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
  128. GMBUS_REG_READ(gpio->reg); /* Posting */
  129. }
  130. static void set_data(void *data, int state_high)
  131. {
  132. struct intel_gpio *gpio = data;
  133. struct drm_psb_private *dev_priv = gpio->dev_priv;
  134. u32 reserved = get_reserved(gpio);
  135. u32 data_bits;
  136. if (state_high)
  137. data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  138. else
  139. data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  140. GPIO_DATA_VAL_MASK;
  141. GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
  142. GMBUS_REG_READ(gpio->reg);
  143. }
  144. static struct i2c_adapter *
  145. intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
  146. {
  147. static const int map_pin_to_reg[] = {
  148. 0,
  149. GPIOB,
  150. GPIOA,
  151. GPIOC,
  152. GPIOD,
  153. GPIOE,
  154. 0,
  155. GPIOF,
  156. };
  157. struct intel_gpio *gpio;
  158. if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
  159. return NULL;
  160. gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
  161. if (gpio == NULL)
  162. return NULL;
  163. gpio->reg = map_pin_to_reg[pin];
  164. gpio->dev_priv = dev_priv;
  165. snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
  166. "gma500 GPIO%c", "?BACDE?F"[pin]);
  167. gpio->adapter.owner = THIS_MODULE;
  168. gpio->adapter.algo_data = &gpio->algo;
  169. gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
  170. gpio->algo.setsda = set_data;
  171. gpio->algo.setscl = set_clock;
  172. gpio->algo.getsda = get_data;
  173. gpio->algo.getscl = get_clock;
  174. gpio->algo.udelay = I2C_RISEFALL_TIME;
  175. gpio->algo.timeout = usecs_to_jiffies(2200);
  176. gpio->algo.data = gpio;
  177. if (i2c_bit_add_bus(&gpio->adapter))
  178. goto out_free;
  179. return &gpio->adapter;
  180. out_free:
  181. kfree(gpio);
  182. return NULL;
  183. }
  184. static int
  185. intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
  186. struct i2c_adapter *adapter,
  187. struct i2c_msg *msgs,
  188. int num)
  189. {
  190. struct intel_gpio *gpio = container_of(adapter,
  191. struct intel_gpio,
  192. adapter);
  193. int ret;
  194. gma_intel_i2c_reset(dev_priv->dev);
  195. intel_i2c_quirk_set(dev_priv, true);
  196. set_data(gpio, 1);
  197. set_clock(gpio, 1);
  198. udelay(I2C_RISEFALL_TIME);
  199. ret = adapter->algo->master_xfer(adapter, msgs, num);
  200. set_data(gpio, 1);
  201. set_clock(gpio, 1);
  202. intel_i2c_quirk_set(dev_priv, false);
  203. return ret;
  204. }
  205. static int
  206. gmbus_xfer(struct i2c_adapter *adapter,
  207. struct i2c_msg *msgs,
  208. int num)
  209. {
  210. struct intel_gmbus *bus = container_of(adapter,
  211. struct intel_gmbus,
  212. adapter);
  213. struct drm_psb_private *dev_priv = adapter->algo_data;
  214. int i, reg_offset;
  215. if (bus->force_bit)
  216. return intel_i2c_quirk_xfer(dev_priv,
  217. bus->force_bit, msgs, num);
  218. reg_offset = 0;
  219. GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
  220. for (i = 0; i < num; i++) {
  221. u16 len = msgs[i].len;
  222. u8 *buf = msgs[i].buf;
  223. if (msgs[i].flags & I2C_M_RD) {
  224. GMBUS_REG_WRITE(GMBUS1 + reg_offset,
  225. GMBUS_CYCLE_WAIT |
  226. (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
  227. (len << GMBUS_BYTE_COUNT_SHIFT) |
  228. (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  229. GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  230. GMBUS_REG_READ(GMBUS2+reg_offset);
  231. do {
  232. u32 val, loop = 0;
  233. if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
  234. (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  235. goto timeout;
  236. if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  237. goto clear_err;
  238. val = GMBUS_REG_READ(GMBUS3 + reg_offset);
  239. do {
  240. *buf++ = val & 0xff;
  241. val >>= 8;
  242. } while (--len && ++loop < 4);
  243. } while (len);
  244. } else {
  245. u32 val, loop;
  246. val = loop = 0;
  247. do {
  248. val |= *buf++ << (8 * loop);
  249. } while (--len && ++loop < 4);
  250. GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
  251. GMBUS_REG_WRITE(GMBUS1 + reg_offset,
  252. (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
  253. (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
  254. (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  255. GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  256. GMBUS_REG_READ(GMBUS2+reg_offset);
  257. while (len) {
  258. if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
  259. (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  260. goto timeout;
  261. if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
  262. GMBUS_SATOER)
  263. goto clear_err;
  264. val = loop = 0;
  265. do {
  266. val |= *buf++ << (8 * loop);
  267. } while (--len && ++loop < 4);
  268. GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
  269. GMBUS_REG_READ(GMBUS2+reg_offset);
  270. }
  271. }
  272. if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
  273. goto timeout;
  274. if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  275. goto clear_err;
  276. }
  277. goto done;
  278. clear_err:
  279. /* Toggle the Software Clear Interrupt bit. This has the effect
  280. * of resetting the GMBUS controller and so clearing the
  281. * BUS_ERROR raised by the slave's NAK.
  282. */
  283. GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  284. GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
  285. done:
  286. /* Mark the GMBUS interface as disabled. We will re-enable it at the
  287. * start of the next xfer, till then let it sleep.
  288. */
  289. GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
  290. return i;
  291. timeout:
  292. DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
  293. bus->reg0 & 0xff, bus->adapter.name);
  294. GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
  295. /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  296. bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
  297. if (!bus->force_bit)
  298. return -ENOMEM;
  299. return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
  300. }
  301. static u32 gmbus_func(struct i2c_adapter *adapter)
  302. {
  303. struct intel_gmbus *bus = container_of(adapter,
  304. struct intel_gmbus,
  305. adapter);
  306. if (bus->force_bit)
  307. bus->force_bit->algo->functionality(bus->force_bit);
  308. return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  309. /* I2C_FUNC_10BIT_ADDR | */
  310. I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  311. I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  312. }
  313. static const struct i2c_algorithm gmbus_algorithm = {
  314. .master_xfer = gmbus_xfer,
  315. .functionality = gmbus_func
  316. };
  317. /**
  318. * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  319. * @dev: DRM device
  320. */
  321. int gma_intel_setup_gmbus(struct drm_device *dev)
  322. {
  323. static const char *names[GMBUS_NUM_PORTS] = {
  324. "disabled",
  325. "ssc",
  326. "vga",
  327. "panel",
  328. "dpc",
  329. "dpb",
  330. "reserved",
  331. "dpd",
  332. };
  333. struct drm_psb_private *dev_priv = dev->dev_private;
  334. int ret, i;
  335. dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
  336. GFP_KERNEL);
  337. if (dev_priv->gmbus == NULL)
  338. return -ENOMEM;
  339. if (IS_MRST(dev))
  340. dev_priv->gmbus_reg = dev_priv->aux_reg;
  341. else
  342. dev_priv->gmbus_reg = dev_priv->vdc_reg;
  343. for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  344. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  345. bus->adapter.owner = THIS_MODULE;
  346. bus->adapter.class = I2C_CLASS_DDC;
  347. snprintf(bus->adapter.name,
  348. sizeof(bus->adapter.name),
  349. "gma500 gmbus %s",
  350. names[i]);
  351. bus->adapter.dev.parent = &dev->pdev->dev;
  352. bus->adapter.algo_data = dev_priv;
  353. bus->adapter.algo = &gmbus_algorithm;
  354. ret = i2c_add_adapter(&bus->adapter);
  355. if (ret)
  356. goto err;
  357. /* By default use a conservative clock rate */
  358. bus->reg0 = i | GMBUS_RATE_100KHZ;
  359. /* XXX force bit banging until GMBUS is fully debugged */
  360. bus->force_bit = intel_gpio_create(dev_priv, i);
  361. }
  362. gma_intel_i2c_reset(dev_priv->dev);
  363. return 0;
  364. err:
  365. while (--i) {
  366. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  367. i2c_del_adapter(&bus->adapter);
  368. }
  369. kfree(dev_priv->gmbus);
  370. dev_priv->gmbus = NULL;
  371. return ret;
  372. }
  373. void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  374. {
  375. struct intel_gmbus *bus = to_intel_gmbus(adapter);
  376. /* speed:
  377. * 0x0 = 100 KHz
  378. * 0x1 = 50 KHz
  379. * 0x2 = 400 KHz
  380. * 0x3 = 1000 Khz
  381. */
  382. bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
  383. }
  384. void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  385. {
  386. struct intel_gmbus *bus = to_intel_gmbus(adapter);
  387. if (force_bit) {
  388. if (bus->force_bit == NULL) {
  389. struct drm_psb_private *dev_priv = adapter->algo_data;
  390. bus->force_bit = intel_gpio_create(dev_priv,
  391. bus->reg0 & 0xff);
  392. }
  393. } else {
  394. if (bus->force_bit) {
  395. i2c_del_adapter(bus->force_bit);
  396. kfree(bus->force_bit);
  397. bus->force_bit = NULL;
  398. }
  399. }
  400. }
  401. void gma_intel_teardown_gmbus(struct drm_device *dev)
  402. {
  403. struct drm_psb_private *dev_priv = dev->dev_private;
  404. int i;
  405. if (dev_priv->gmbus == NULL)
  406. return;
  407. for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  408. struct intel_gmbus *bus = &dev_priv->gmbus[i];
  409. if (bus->force_bit) {
  410. i2c_del_adapter(bus->force_bit);
  411. kfree(bus->force_bit);
  412. }
  413. i2c_del_adapter(&bus->adapter);
  414. }
  415. dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
  416. kfree(dev_priv->gmbus);
  417. dev_priv->gmbus = NULL;
  418. }