oaktrail_hdmi.c 24 KB

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  1. /*
  2. * Copyright © 2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Li Peng <peng.li@intel.com>
  25. */
  26. #include <drm/drmP.h>
  27. #include <drm/drm.h>
  28. #include "psb_intel_drv.h"
  29. #include "psb_intel_reg.h"
  30. #include "psb_drv.h"
  31. #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
  32. #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
  33. #define HDMI_HCR 0x1000
  34. #define HCR_ENABLE_HDCP (1 << 5)
  35. #define HCR_ENABLE_AUDIO (1 << 2)
  36. #define HCR_ENABLE_PIXEL (1 << 1)
  37. #define HCR_ENABLE_TMDS (1 << 0)
  38. #define HDMI_HICR 0x1004
  39. #define HDMI_HSR 0x1008
  40. #define HDMI_HISR 0x100C
  41. #define HDMI_DETECT_HDP (1 << 0)
  42. #define HDMI_VIDEO_REG 0x3000
  43. #define HDMI_UNIT_EN (1 << 7)
  44. #define HDMI_MODE_OUTPUT (1 << 0)
  45. #define HDMI_HBLANK_A 0x3100
  46. #define HDMI_AUDIO_CTRL 0x4000
  47. #define HDMI_ENABLE_AUDIO (1 << 0)
  48. #define PCH_HTOTAL_B 0x3100
  49. #define PCH_HBLANK_B 0x3104
  50. #define PCH_HSYNC_B 0x3108
  51. #define PCH_VTOTAL_B 0x310C
  52. #define PCH_VBLANK_B 0x3110
  53. #define PCH_VSYNC_B 0x3114
  54. #define PCH_PIPEBSRC 0x311C
  55. #define PCH_PIPEB_DSL 0x3800
  56. #define PCH_PIPEB_SLC 0x3804
  57. #define PCH_PIPEBCONF 0x3808
  58. #define PCH_PIPEBSTAT 0x3824
  59. #define CDVO_DFT 0x5000
  60. #define CDVO_SLEWRATE 0x5004
  61. #define CDVO_STRENGTH 0x5008
  62. #define CDVO_RCOMP 0x500C
  63. #define DPLL_CTRL 0x6000
  64. #define DPLL_PDIV_SHIFT 16
  65. #define DPLL_PDIV_MASK (0xf << 16)
  66. #define DPLL_PWRDN (1 << 4)
  67. #define DPLL_RESET (1 << 3)
  68. #define DPLL_FASTEN (1 << 2)
  69. #define DPLL_ENSTAT (1 << 1)
  70. #define DPLL_DITHEN (1 << 0)
  71. #define DPLL_DIV_CTRL 0x6004
  72. #define DPLL_CLKF_MASK 0xffffffc0
  73. #define DPLL_CLKR_MASK (0x3f)
  74. #define DPLL_CLK_ENABLE 0x6008
  75. #define DPLL_EN_DISP (1 << 31)
  76. #define DPLL_SEL_HDMI (1 << 8)
  77. #define DPLL_EN_HDMI (1 << 1)
  78. #define DPLL_EN_VGA (1 << 0)
  79. #define DPLL_ADJUST 0x600C
  80. #define DPLL_STATUS 0x6010
  81. #define DPLL_UPDATE 0x6014
  82. #define DPLL_DFT 0x6020
  83. struct intel_range {
  84. int min, max;
  85. };
  86. struct oaktrail_hdmi_limit {
  87. struct intel_range vco, np, nr, nf;
  88. };
  89. struct oaktrail_hdmi_clock {
  90. int np;
  91. int nr;
  92. int nf;
  93. int dot;
  94. };
  95. #define VCO_MIN 320000
  96. #define VCO_MAX 1650000
  97. #define NP_MIN 1
  98. #define NP_MAX 15
  99. #define NR_MIN 1
  100. #define NR_MAX 64
  101. #define NF_MIN 2
  102. #define NF_MAX 4095
  103. static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = {
  104. .vco = { .min = VCO_MIN, .max = VCO_MAX },
  105. .np = { .min = NP_MIN, .max = NP_MAX },
  106. .nr = { .min = NR_MIN, .max = NR_MAX },
  107. .nf = { .min = NF_MIN, .max = NF_MAX },
  108. };
  109. static void oaktrail_hdmi_audio_enable(struct drm_device *dev)
  110. {
  111. struct drm_psb_private *dev_priv = dev->dev_private;
  112. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  113. HDMI_WRITE(HDMI_HCR, 0x67);
  114. HDMI_READ(HDMI_HCR);
  115. HDMI_WRITE(0x51a8, 0x10);
  116. HDMI_READ(0x51a8);
  117. HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1);
  118. HDMI_READ(HDMI_AUDIO_CTRL);
  119. }
  120. static void oaktrail_hdmi_audio_disable(struct drm_device *dev)
  121. {
  122. struct drm_psb_private *dev_priv = dev->dev_private;
  123. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  124. HDMI_WRITE(0x51a8, 0x0);
  125. HDMI_READ(0x51a8);
  126. HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0);
  127. HDMI_READ(HDMI_AUDIO_CTRL);
  128. HDMI_WRITE(HDMI_HCR, 0x47);
  129. HDMI_READ(HDMI_HCR);
  130. }
  131. static unsigned int htotal_calculate(struct drm_display_mode *mode)
  132. {
  133. u32 htotal, new_crtc_htotal;
  134. htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16);
  135. /*
  136. * 1024 x 768 new_crtc_htotal = 0x1024;
  137. * 1280 x 1024 new_crtc_htotal = 0x0c34;
  138. */
  139. new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
  140. DRM_DEBUG_KMS("new crtc htotal 0x%4x\n", new_crtc_htotal);
  141. return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16);
  142. }
  143. static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target,
  144. int refclk, struct oaktrail_hdmi_clock *best_clock)
  145. {
  146. int np_min, np_max, nr_min, nr_max;
  147. int np, nr, nf;
  148. np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10);
  149. np_max = oaktrail_hdmi_limit.vco.max / (target * 10);
  150. if (np_min < oaktrail_hdmi_limit.np.min)
  151. np_min = oaktrail_hdmi_limit.np.min;
  152. if (np_max > oaktrail_hdmi_limit.np.max)
  153. np_max = oaktrail_hdmi_limit.np.max;
  154. nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max));
  155. nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min));
  156. if (nr_min < oaktrail_hdmi_limit.nr.min)
  157. nr_min = oaktrail_hdmi_limit.nr.min;
  158. if (nr_max > oaktrail_hdmi_limit.nr.max)
  159. nr_max = oaktrail_hdmi_limit.nr.max;
  160. np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max));
  161. nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np));
  162. nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk);
  163. DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf);
  164. /*
  165. * 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000;
  166. * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000;
  167. */
  168. best_clock->np = np;
  169. best_clock->nr = nr - 1;
  170. best_clock->nf = (nf << 14);
  171. }
  172. static void scu_busy_loop(void __iomem *scu_base)
  173. {
  174. u32 status = 0;
  175. u32 loop_count = 0;
  176. status = readl(scu_base + 0x04);
  177. while (status & 1) {
  178. udelay(1); /* scu processing time is in few u secods */
  179. status = readl(scu_base + 0x04);
  180. loop_count++;
  181. /* break if scu doesn't reset busy bit after huge retry */
  182. if (loop_count > 1000) {
  183. DRM_DEBUG_KMS("SCU IPC timed out");
  184. return;
  185. }
  186. }
  187. }
  188. /*
  189. * You don't want to know, you really really don't want to know....
  190. *
  191. * This is magic. However it's safe magic because of the way the platform
  192. * works and it is necessary magic.
  193. */
  194. static void oaktrail_hdmi_reset(struct drm_device *dev)
  195. {
  196. void __iomem *base;
  197. unsigned long scu_ipc_mmio = 0xff11c000UL;
  198. int scu_len = 1024;
  199. base = ioremap((resource_size_t)scu_ipc_mmio, scu_len);
  200. if (base == NULL) {
  201. DRM_ERROR("failed to map scu mmio\n");
  202. return;
  203. }
  204. /* scu ipc: assert hdmi controller reset */
  205. writel(0xff11d118, base + 0x0c);
  206. writel(0x7fffffdf, base + 0x80);
  207. writel(0x42005, base + 0x0);
  208. scu_busy_loop(base);
  209. /* scu ipc: de-assert hdmi controller reset */
  210. writel(0xff11d118, base + 0x0c);
  211. writel(0x7fffffff, base + 0x80);
  212. writel(0x42005, base + 0x0);
  213. scu_busy_loop(base);
  214. iounmap(base);
  215. }
  216. int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc,
  217. struct drm_display_mode *mode,
  218. struct drm_display_mode *adjusted_mode,
  219. int x, int y,
  220. struct drm_framebuffer *old_fb)
  221. {
  222. struct drm_device *dev = crtc->dev;
  223. struct drm_psb_private *dev_priv = dev->dev_private;
  224. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  225. int pipe = 1;
  226. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  227. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  228. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  229. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  230. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  231. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  232. int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
  233. int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
  234. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  235. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  236. int refclk;
  237. struct oaktrail_hdmi_clock clock;
  238. u32 dspcntr, pipeconf, dpll, temp;
  239. int dspcntr_reg = DSPBCNTR;
  240. if (!gma_power_begin(dev, true))
  241. return 0;
  242. /* Disable the VGA plane that we never use */
  243. REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
  244. /* Disable dpll if necessary */
  245. dpll = REG_READ(DPLL_CTRL);
  246. if ((dpll & DPLL_PWRDN) == 0) {
  247. REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
  248. REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
  249. REG_WRITE(DPLL_STATUS, 0x1);
  250. }
  251. udelay(150);
  252. /* Reset controller */
  253. oaktrail_hdmi_reset(dev);
  254. /* program and enable dpll */
  255. refclk = 25000;
  256. oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
  257. /* Set the DPLL */
  258. dpll = REG_READ(DPLL_CTRL);
  259. dpll &= ~DPLL_PDIV_MASK;
  260. dpll &= ~(DPLL_PWRDN | DPLL_RESET);
  261. REG_WRITE(DPLL_CTRL, 0x00000008);
  262. REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
  263. REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
  264. REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
  265. REG_WRITE(DPLL_UPDATE, 0x80000000);
  266. REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
  267. udelay(150);
  268. /* configure HDMI */
  269. HDMI_WRITE(0x1004, 0x1fd);
  270. HDMI_WRITE(0x2000, 0x1);
  271. HDMI_WRITE(0x2008, 0x0);
  272. HDMI_WRITE(0x3130, 0x8);
  273. HDMI_WRITE(0x101c, 0x1800810);
  274. temp = htotal_calculate(adjusted_mode);
  275. REG_WRITE(htot_reg, temp);
  276. REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
  277. REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
  278. REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
  279. REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
  280. REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
  281. REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
  282. REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
  283. REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
  284. REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
  285. REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
  286. REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
  287. REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
  288. REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
  289. temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
  290. HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
  291. REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
  292. REG_WRITE(dsppos_reg, 0);
  293. /* Flush the plane changes */
  294. {
  295. const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  296. crtc_funcs->mode_set_base(crtc, x, y, old_fb);
  297. }
  298. /* Set up the display plane register */
  299. dspcntr = REG_READ(dspcntr_reg);
  300. dspcntr |= DISPPLANE_GAMMA_ENABLE;
  301. dspcntr |= DISPPLANE_SEL_PIPE_B;
  302. dspcntr |= DISPLAY_PLANE_ENABLE;
  303. /* setup pipeconf */
  304. pipeconf = REG_READ(pipeconf_reg);
  305. pipeconf |= PIPEACONF_ENABLE;
  306. REG_WRITE(pipeconf_reg, pipeconf);
  307. REG_READ(pipeconf_reg);
  308. REG_WRITE(PCH_PIPEBCONF, pipeconf);
  309. REG_READ(PCH_PIPEBCONF);
  310. gma_wait_for_vblank(dev);
  311. REG_WRITE(dspcntr_reg, dspcntr);
  312. gma_wait_for_vblank(dev);
  313. gma_power_end(dev);
  314. return 0;
  315. }
  316. void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode)
  317. {
  318. struct drm_device *dev = crtc->dev;
  319. u32 temp;
  320. DRM_DEBUG_KMS("%s %d\n", __func__, mode);
  321. switch (mode) {
  322. case DRM_MODE_DPMS_OFF:
  323. REG_WRITE(VGACNTRL, 0x80000000);
  324. /* Disable plane */
  325. temp = REG_READ(DSPBCNTR);
  326. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  327. REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
  328. REG_READ(DSPBCNTR);
  329. /* Flush the plane changes */
  330. REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
  331. REG_READ(DSPBSURF);
  332. }
  333. /* Disable pipe B */
  334. temp = REG_READ(PIPEBCONF);
  335. if ((temp & PIPEACONF_ENABLE) != 0) {
  336. REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
  337. REG_READ(PIPEBCONF);
  338. }
  339. /* Disable LNW Pipes, etc */
  340. temp = REG_READ(PCH_PIPEBCONF);
  341. if ((temp & PIPEACONF_ENABLE) != 0) {
  342. REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
  343. REG_READ(PCH_PIPEBCONF);
  344. }
  345. /* wait for pipe off */
  346. udelay(150);
  347. /* Disable dpll */
  348. temp = REG_READ(DPLL_CTRL);
  349. if ((temp & DPLL_PWRDN) == 0) {
  350. REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
  351. REG_WRITE(DPLL_STATUS, 0x1);
  352. }
  353. /* wait for dpll off */
  354. udelay(150);
  355. break;
  356. case DRM_MODE_DPMS_ON:
  357. case DRM_MODE_DPMS_STANDBY:
  358. case DRM_MODE_DPMS_SUSPEND:
  359. /* Enable dpll */
  360. temp = REG_READ(DPLL_CTRL);
  361. if ((temp & DPLL_PWRDN) != 0) {
  362. REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
  363. temp = REG_READ(DPLL_CLK_ENABLE);
  364. REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
  365. REG_READ(DPLL_CLK_ENABLE);
  366. }
  367. /* wait for dpll warm up */
  368. udelay(150);
  369. /* Enable pipe B */
  370. temp = REG_READ(PIPEBCONF);
  371. if ((temp & PIPEACONF_ENABLE) == 0) {
  372. REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
  373. REG_READ(PIPEBCONF);
  374. }
  375. /* Enable LNW Pipe B */
  376. temp = REG_READ(PCH_PIPEBCONF);
  377. if ((temp & PIPEACONF_ENABLE) == 0) {
  378. REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
  379. REG_READ(PCH_PIPEBCONF);
  380. }
  381. gma_wait_for_vblank(dev);
  382. /* Enable plane */
  383. temp = REG_READ(DSPBCNTR);
  384. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  385. REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
  386. /* Flush the plane changes */
  387. REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
  388. REG_READ(DSPBSURF);
  389. }
  390. gma_crtc_load_lut(crtc);
  391. }
  392. /* DSPARB */
  393. REG_WRITE(DSPARB, 0x00003fbf);
  394. /* FW1 */
  395. REG_WRITE(0x70034, 0x3f880a0a);
  396. /* FW2 */
  397. REG_WRITE(0x70038, 0x0b060808);
  398. /* FW4 */
  399. REG_WRITE(0x70050, 0x08030404);
  400. /* FW5 */
  401. REG_WRITE(0x70054, 0x04040404);
  402. /* LNC Chicken Bits - Squawk! */
  403. REG_WRITE(0x70400, 0x4000);
  404. return;
  405. }
  406. static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode)
  407. {
  408. static int dpms_mode = -1;
  409. struct drm_device *dev = encoder->dev;
  410. struct drm_psb_private *dev_priv = dev->dev_private;
  411. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  412. u32 temp;
  413. if (dpms_mode == mode)
  414. return;
  415. if (mode != DRM_MODE_DPMS_ON)
  416. temp = 0x0;
  417. else
  418. temp = 0x99;
  419. dpms_mode = mode;
  420. HDMI_WRITE(HDMI_VIDEO_REG, temp);
  421. }
  422. static int oaktrail_hdmi_mode_valid(struct drm_connector *connector,
  423. struct drm_display_mode *mode)
  424. {
  425. if (mode->clock > 165000)
  426. return MODE_CLOCK_HIGH;
  427. if (mode->clock < 20000)
  428. return MODE_CLOCK_LOW;
  429. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  430. return MODE_NO_DBLESCAN;
  431. return MODE_OK;
  432. }
  433. static enum drm_connector_status
  434. oaktrail_hdmi_detect(struct drm_connector *connector, bool force)
  435. {
  436. enum drm_connector_status status;
  437. struct drm_device *dev = connector->dev;
  438. struct drm_psb_private *dev_priv = dev->dev_private;
  439. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  440. u32 temp;
  441. temp = HDMI_READ(HDMI_HSR);
  442. DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
  443. if ((temp & HDMI_DETECT_HDP) != 0)
  444. status = connector_status_connected;
  445. else
  446. status = connector_status_disconnected;
  447. return status;
  448. }
  449. static const unsigned char raw_edid[] = {
  450. 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0,
  451. 0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78,
  452. 0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5,
  453. 0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01,
  454. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
  455. 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a,
  456. 0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35,
  457. 0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44,
  458. 0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20,
  459. 0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a,
  460. 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d
  461. };
  462. static int oaktrail_hdmi_get_modes(struct drm_connector *connector)
  463. {
  464. struct i2c_adapter *i2c_adap;
  465. struct edid *edid;
  466. int ret = 0;
  467. /*
  468. * FIXME: We need to figure this lot out. In theory we can
  469. * read the EDID somehow but I've yet to find working reference
  470. * code.
  471. */
  472. i2c_adap = i2c_get_adapter(3);
  473. if (i2c_adap == NULL) {
  474. DRM_ERROR("No ddc adapter available!\n");
  475. edid = (struct edid *)raw_edid;
  476. } else {
  477. edid = (struct edid *)raw_edid;
  478. /* FIXME ? edid = drm_get_edid(connector, i2c_adap); */
  479. }
  480. if (edid) {
  481. drm_mode_connector_update_edid_property(connector, edid);
  482. ret = drm_add_edid_modes(connector, edid);
  483. }
  484. return ret;
  485. }
  486. static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder,
  487. struct drm_display_mode *mode,
  488. struct drm_display_mode *adjusted_mode)
  489. {
  490. struct drm_device *dev = encoder->dev;
  491. oaktrail_hdmi_audio_enable(dev);
  492. return;
  493. }
  494. static void oaktrail_hdmi_destroy(struct drm_connector *connector)
  495. {
  496. return;
  497. }
  498. static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = {
  499. .dpms = oaktrail_hdmi_dpms,
  500. .mode_fixup = gma_encoder_mode_fixup,
  501. .prepare = gma_encoder_prepare,
  502. .mode_set = oaktrail_hdmi_mode_set,
  503. .commit = gma_encoder_commit,
  504. };
  505. static const struct drm_connector_helper_funcs
  506. oaktrail_hdmi_connector_helper_funcs = {
  507. .get_modes = oaktrail_hdmi_get_modes,
  508. .mode_valid = oaktrail_hdmi_mode_valid,
  509. .best_encoder = gma_best_encoder,
  510. };
  511. static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = {
  512. .dpms = drm_helper_connector_dpms,
  513. .detect = oaktrail_hdmi_detect,
  514. .fill_modes = drm_helper_probe_single_connector_modes,
  515. .destroy = oaktrail_hdmi_destroy,
  516. };
  517. static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder)
  518. {
  519. drm_encoder_cleanup(encoder);
  520. }
  521. static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = {
  522. .destroy = oaktrail_hdmi_enc_destroy,
  523. };
  524. void oaktrail_hdmi_init(struct drm_device *dev,
  525. struct psb_intel_mode_device *mode_dev)
  526. {
  527. struct gma_encoder *gma_encoder;
  528. struct gma_connector *gma_connector;
  529. struct drm_connector *connector;
  530. struct drm_encoder *encoder;
  531. gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
  532. if (!gma_encoder)
  533. return;
  534. gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
  535. if (!gma_connector)
  536. goto failed_connector;
  537. connector = &gma_connector->base;
  538. encoder = &gma_encoder->base;
  539. drm_connector_init(dev, connector,
  540. &oaktrail_hdmi_connector_funcs,
  541. DRM_MODE_CONNECTOR_DVID);
  542. drm_encoder_init(dev, encoder,
  543. &oaktrail_hdmi_enc_funcs,
  544. DRM_MODE_ENCODER_TMDS);
  545. gma_connector_attach_encoder(gma_connector, gma_encoder);
  546. gma_encoder->type = INTEL_OUTPUT_HDMI;
  547. drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
  548. drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs);
  549. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  550. connector->interlace_allowed = false;
  551. connector->doublescan_allowed = false;
  552. drm_connector_register(connector);
  553. dev_info(dev->dev, "HDMI initialised.\n");
  554. return;
  555. failed_connector:
  556. kfree(gma_encoder);
  557. }
  558. static const struct pci_device_id hdmi_ids[] = {
  559. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) },
  560. { 0 }
  561. };
  562. void oaktrail_hdmi_setup(struct drm_device *dev)
  563. {
  564. struct drm_psb_private *dev_priv = dev->dev_private;
  565. struct pci_dev *pdev;
  566. struct oaktrail_hdmi_dev *hdmi_dev;
  567. int ret;
  568. pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL);
  569. if (!pdev)
  570. return;
  571. hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL);
  572. if (!hdmi_dev) {
  573. dev_err(dev->dev, "failed to allocate memory\n");
  574. goto out;
  575. }
  576. ret = pci_enable_device(pdev);
  577. if (ret) {
  578. dev_err(dev->dev, "failed to enable hdmi controller\n");
  579. goto free;
  580. }
  581. hdmi_dev->mmio = pci_resource_start(pdev, 0);
  582. hdmi_dev->mmio_len = pci_resource_len(pdev, 0);
  583. hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len);
  584. if (!hdmi_dev->regs) {
  585. dev_err(dev->dev, "failed to map hdmi mmio\n");
  586. goto free;
  587. }
  588. hdmi_dev->dev = pdev;
  589. pci_set_drvdata(pdev, hdmi_dev);
  590. /* Initialize i2c controller */
  591. ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev);
  592. if (ret)
  593. dev_err(dev->dev, "HDMI I2C initialization failed\n");
  594. dev_priv->hdmi_priv = hdmi_dev;
  595. oaktrail_hdmi_audio_disable(dev);
  596. dev_info(dev->dev, "HDMI hardware present.\n");
  597. return;
  598. free:
  599. kfree(hdmi_dev);
  600. out:
  601. return;
  602. }
  603. void oaktrail_hdmi_teardown(struct drm_device *dev)
  604. {
  605. struct drm_psb_private *dev_priv = dev->dev_private;
  606. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  607. struct pci_dev *pdev;
  608. if (hdmi_dev) {
  609. pdev = hdmi_dev->dev;
  610. pci_set_drvdata(pdev, NULL);
  611. oaktrail_hdmi_i2c_exit(pdev);
  612. iounmap(hdmi_dev->regs);
  613. kfree(hdmi_dev);
  614. pci_dev_put(pdev);
  615. }
  616. }
  617. /* save HDMI register state */
  618. void oaktrail_hdmi_save(struct drm_device *dev)
  619. {
  620. struct drm_psb_private *dev_priv = dev->dev_private;
  621. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  622. struct psb_state *regs = &dev_priv->regs.psb;
  623. struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
  624. int i;
  625. /* dpll */
  626. hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL);
  627. hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL);
  628. hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST);
  629. hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE);
  630. hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
  631. /* pipe B */
  632. pipeb->conf = PSB_RVDC32(PIPEBCONF);
  633. pipeb->src = PSB_RVDC32(PIPEBSRC);
  634. pipeb->htotal = PSB_RVDC32(HTOTAL_B);
  635. pipeb->hblank = PSB_RVDC32(HBLANK_B);
  636. pipeb->hsync = PSB_RVDC32(HSYNC_B);
  637. pipeb->vtotal = PSB_RVDC32(VTOTAL_B);
  638. pipeb->vblank = PSB_RVDC32(VBLANK_B);
  639. pipeb->vsync = PSB_RVDC32(VSYNC_B);
  640. hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
  641. hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
  642. hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B);
  643. hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B);
  644. hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B);
  645. hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B);
  646. hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B);
  647. hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
  648. /* plane */
  649. pipeb->cntr = PSB_RVDC32(DSPBCNTR);
  650. pipeb->stride = PSB_RVDC32(DSPBSTRIDE);
  651. pipeb->addr = PSB_RVDC32(DSPBBASE);
  652. pipeb->surf = PSB_RVDC32(DSPBSURF);
  653. pipeb->linoff = PSB_RVDC32(DSPBLINOFF);
  654. pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF);
  655. /* cursor B */
  656. regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
  657. regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE);
  658. regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS);
  659. /* save palette */
  660. for (i = 0; i < 256; i++)
  661. pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2));
  662. }
  663. /* restore HDMI register state */
  664. void oaktrail_hdmi_restore(struct drm_device *dev)
  665. {
  666. struct drm_psb_private *dev_priv = dev->dev_private;
  667. struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
  668. struct psb_state *regs = &dev_priv->regs.psb;
  669. struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
  670. int i;
  671. /* dpll */
  672. PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
  673. PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
  674. PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
  675. PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
  676. PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
  677. DRM_UDELAY(150);
  678. /* pipe */
  679. PSB_WVDC32(pipeb->src, PIPEBSRC);
  680. PSB_WVDC32(pipeb->htotal, HTOTAL_B);
  681. PSB_WVDC32(pipeb->hblank, HBLANK_B);
  682. PSB_WVDC32(pipeb->hsync, HSYNC_B);
  683. PSB_WVDC32(pipeb->vtotal, VTOTAL_B);
  684. PSB_WVDC32(pipeb->vblank, VBLANK_B);
  685. PSB_WVDC32(pipeb->vsync, VSYNC_B);
  686. PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
  687. PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
  688. PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B);
  689. PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B);
  690. PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B);
  691. PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
  692. PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
  693. PSB_WVDC32(pipeb->conf, PIPEBCONF);
  694. PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
  695. /* plane */
  696. PSB_WVDC32(pipeb->linoff, DSPBLINOFF);
  697. PSB_WVDC32(pipeb->stride, DSPBSTRIDE);
  698. PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF);
  699. PSB_WVDC32(pipeb->cntr, DSPBCNTR);
  700. PSB_WVDC32(pipeb->surf, DSPBSURF);
  701. /* cursor B */
  702. PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
  703. PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS);
  704. PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE);
  705. /* restore palette */
  706. for (i = 0; i < 256; i++)
  707. PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2));
  708. }