psb_intel_display.c 16 KB

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  1. /*
  2. * Copyright © 2006-2011 Intel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program; if not, write to the Free Software Foundation, Inc.,
  15. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16. *
  17. * Authors:
  18. * Eric Anholt <eric@anholt.net>
  19. */
  20. #include <linux/i2c.h>
  21. #include <drm/drmP.h>
  22. #include <drm/drm_plane_helper.h>
  23. #include "framebuffer.h"
  24. #include "psb_drv.h"
  25. #include "psb_intel_drv.h"
  26. #include "psb_intel_reg.h"
  27. #include "gma_display.h"
  28. #include "power.h"
  29. #define INTEL_LIMIT_I9XX_SDVO_DAC 0
  30. #define INTEL_LIMIT_I9XX_LVDS 1
  31. static const struct gma_limit_t psb_intel_limits[] = {
  32. { /* INTEL_LIMIT_I9XX_SDVO_DAC */
  33. .dot = {.min = 20000, .max = 400000},
  34. .vco = {.min = 1400000, .max = 2800000},
  35. .n = {.min = 1, .max = 6},
  36. .m = {.min = 70, .max = 120},
  37. .m1 = {.min = 8, .max = 18},
  38. .m2 = {.min = 3, .max = 7},
  39. .p = {.min = 5, .max = 80},
  40. .p1 = {.min = 1, .max = 8},
  41. .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
  42. .find_pll = gma_find_best_pll,
  43. },
  44. { /* INTEL_LIMIT_I9XX_LVDS */
  45. .dot = {.min = 20000, .max = 400000},
  46. .vco = {.min = 1400000, .max = 2800000},
  47. .n = {.min = 1, .max = 6},
  48. .m = {.min = 70, .max = 120},
  49. .m1 = {.min = 8, .max = 18},
  50. .m2 = {.min = 3, .max = 7},
  51. .p = {.min = 7, .max = 98},
  52. .p1 = {.min = 1, .max = 8},
  53. /* The single-channel range is 25-112Mhz, and dual-channel
  54. * is 80-224Mhz. Prefer single channel as much as possible.
  55. */
  56. .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
  57. .find_pll = gma_find_best_pll,
  58. },
  59. };
  60. static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
  61. int refclk)
  62. {
  63. const struct gma_limit_t *limit;
  64. if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  65. limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
  66. else
  67. limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
  68. return limit;
  69. }
  70. static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
  71. {
  72. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  73. clock->p = clock->p1 * clock->p2;
  74. clock->vco = refclk * clock->m / (clock->n + 2);
  75. clock->dot = clock->vco / clock->p;
  76. }
  77. /**
  78. * Return the pipe currently connected to the panel fitter,
  79. * or -1 if the panel fitter is not present or not in use
  80. */
  81. static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
  82. {
  83. u32 pfit_control;
  84. pfit_control = REG_READ(PFIT_CONTROL);
  85. /* See if the panel fitter is in use */
  86. if ((pfit_control & PFIT_ENABLE) == 0)
  87. return -1;
  88. /* Must be on PIPE 1 for PSB */
  89. return 1;
  90. }
  91. static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
  92. struct drm_display_mode *mode,
  93. struct drm_display_mode *adjusted_mode,
  94. int x, int y,
  95. struct drm_framebuffer *old_fb)
  96. {
  97. struct drm_device *dev = crtc->dev;
  98. struct drm_psb_private *dev_priv = dev->dev_private;
  99. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  100. const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  101. int pipe = gma_crtc->pipe;
  102. const struct psb_offset *map = &dev_priv->regmap[pipe];
  103. int refclk;
  104. struct gma_clock_t clock;
  105. u32 dpll = 0, fp = 0, dspcntr, pipeconf;
  106. bool ok, is_sdvo = false;
  107. bool is_lvds = false, is_tv = false;
  108. struct drm_mode_config *mode_config = &dev->mode_config;
  109. struct drm_connector *connector;
  110. const struct gma_limit_t *limit;
  111. /* No scan out no play */
  112. if (crtc->primary->fb == NULL) {
  113. crtc_funcs->mode_set_base(crtc, x, y, old_fb);
  114. return 0;
  115. }
  116. list_for_each_entry(connector, &mode_config->connector_list, head) {
  117. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  118. if (!connector->encoder
  119. || connector->encoder->crtc != crtc)
  120. continue;
  121. switch (gma_encoder->type) {
  122. case INTEL_OUTPUT_LVDS:
  123. is_lvds = true;
  124. break;
  125. case INTEL_OUTPUT_SDVO:
  126. is_sdvo = true;
  127. break;
  128. case INTEL_OUTPUT_TVOUT:
  129. is_tv = true;
  130. break;
  131. }
  132. }
  133. refclk = 96000;
  134. limit = gma_crtc->clock_funcs->limit(crtc, refclk);
  135. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
  136. &clock);
  137. if (!ok) {
  138. DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
  139. adjusted_mode->clock, clock.dot);
  140. return 0;
  141. }
  142. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  143. dpll = DPLL_VGA_MODE_DIS;
  144. if (is_lvds) {
  145. dpll |= DPLLB_MODE_LVDS;
  146. dpll |= DPLL_DVO_HIGH_SPEED;
  147. } else
  148. dpll |= DPLLB_MODE_DAC_SERIAL;
  149. if (is_sdvo) {
  150. int sdvo_pixel_multiply =
  151. adjusted_mode->clock / mode->clock;
  152. dpll |= DPLL_DVO_HIGH_SPEED;
  153. dpll |=
  154. (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  155. }
  156. /* compute bitmask from p1 value */
  157. dpll |= (1 << (clock.p1 - 1)) << 16;
  158. switch (clock.p2) {
  159. case 5:
  160. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  161. break;
  162. case 7:
  163. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  164. break;
  165. case 10:
  166. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  167. break;
  168. case 14:
  169. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  170. break;
  171. }
  172. if (is_tv) {
  173. /* XXX: just matching BIOS for now */
  174. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  175. dpll |= 3;
  176. }
  177. dpll |= PLL_REF_INPUT_DREFCLK;
  178. /* setup pipeconf */
  179. pipeconf = REG_READ(map->conf);
  180. /* Set up the display plane register */
  181. dspcntr = DISPPLANE_GAMMA_ENABLE;
  182. if (pipe == 0)
  183. dspcntr |= DISPPLANE_SEL_PIPE_A;
  184. else
  185. dspcntr |= DISPPLANE_SEL_PIPE_B;
  186. dspcntr |= DISPLAY_PLANE_ENABLE;
  187. pipeconf |= PIPEACONF_ENABLE;
  188. dpll |= DPLL_VCO_ENABLE;
  189. /* Disable the panel fitter if it was on our pipe */
  190. if (psb_intel_panel_fitter_pipe(dev) == pipe)
  191. REG_WRITE(PFIT_CONTROL, 0);
  192. drm_mode_debug_printmodeline(mode);
  193. if (dpll & DPLL_VCO_ENABLE) {
  194. REG_WRITE(map->fp0, fp);
  195. REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
  196. REG_READ(map->dpll);
  197. udelay(150);
  198. }
  199. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  200. * This is an exception to the general rule that mode_set doesn't turn
  201. * things on.
  202. */
  203. if (is_lvds) {
  204. u32 lvds = REG_READ(LVDS);
  205. lvds &= ~LVDS_PIPEB_SELECT;
  206. if (pipe == 1)
  207. lvds |= LVDS_PIPEB_SELECT;
  208. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  209. /* Set the B0-B3 data pairs corresponding to
  210. * whether we're going to
  211. * set the DPLLs for dual-channel mode or not.
  212. */
  213. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  214. if (clock.p2 == 7)
  215. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  216. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  217. * appropriately here, but we need to look more
  218. * thoroughly into how panels behave in the two modes.
  219. */
  220. REG_WRITE(LVDS, lvds);
  221. REG_READ(LVDS);
  222. }
  223. REG_WRITE(map->fp0, fp);
  224. REG_WRITE(map->dpll, dpll);
  225. REG_READ(map->dpll);
  226. /* Wait for the clocks to stabilize. */
  227. udelay(150);
  228. /* write it again -- the BIOS does, after all */
  229. REG_WRITE(map->dpll, dpll);
  230. REG_READ(map->dpll);
  231. /* Wait for the clocks to stabilize. */
  232. udelay(150);
  233. REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
  234. ((adjusted_mode->crtc_htotal - 1) << 16));
  235. REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
  236. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  237. REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
  238. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  239. REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
  240. ((adjusted_mode->crtc_vtotal - 1) << 16));
  241. REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
  242. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  243. REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
  244. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  245. /* pipesrc and dspsize control the size that is scaled from,
  246. * which should always be the user's requested size.
  247. */
  248. REG_WRITE(map->size,
  249. ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
  250. REG_WRITE(map->pos, 0);
  251. REG_WRITE(map->src,
  252. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  253. REG_WRITE(map->conf, pipeconf);
  254. REG_READ(map->conf);
  255. gma_wait_for_vblank(dev);
  256. REG_WRITE(map->cntr, dspcntr);
  257. /* Flush the plane changes */
  258. crtc_funcs->mode_set_base(crtc, x, y, old_fb);
  259. gma_wait_for_vblank(dev);
  260. return 0;
  261. }
  262. /* Returns the clock of the currently programmed mode of the given pipe. */
  263. static int psb_intel_crtc_clock_get(struct drm_device *dev,
  264. struct drm_crtc *crtc)
  265. {
  266. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  267. struct drm_psb_private *dev_priv = dev->dev_private;
  268. int pipe = gma_crtc->pipe;
  269. const struct psb_offset *map = &dev_priv->regmap[pipe];
  270. u32 dpll;
  271. u32 fp;
  272. struct gma_clock_t clock;
  273. bool is_lvds;
  274. struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
  275. if (gma_power_begin(dev, false)) {
  276. dpll = REG_READ(map->dpll);
  277. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  278. fp = REG_READ(map->fp0);
  279. else
  280. fp = REG_READ(map->fp1);
  281. is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
  282. gma_power_end(dev);
  283. } else {
  284. dpll = p->dpll;
  285. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  286. fp = p->fp0;
  287. else
  288. fp = p->fp1;
  289. is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
  290. LVDS_PORT_EN);
  291. }
  292. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  293. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  294. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  295. if (is_lvds) {
  296. clock.p1 =
  297. ffs((dpll &
  298. DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  299. DPLL_FPA01_P1_POST_DIV_SHIFT);
  300. clock.p2 = 14;
  301. if ((dpll & PLL_REF_INPUT_MASK) ==
  302. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  303. /* XXX: might not be 66MHz */
  304. psb_intel_clock(66000, &clock);
  305. } else
  306. psb_intel_clock(48000, &clock);
  307. } else {
  308. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  309. clock.p1 = 2;
  310. else {
  311. clock.p1 =
  312. ((dpll &
  313. DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  314. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  315. }
  316. if (dpll & PLL_P2_DIVIDE_BY_4)
  317. clock.p2 = 4;
  318. else
  319. clock.p2 = 2;
  320. psb_intel_clock(48000, &clock);
  321. }
  322. /* XXX: It would be nice to validate the clocks, but we can't reuse
  323. * i830PllIsValid() because it relies on the xf86_config connector
  324. * configuration being accurate, which it isn't necessarily.
  325. */
  326. return clock.dot;
  327. }
  328. /** Returns the currently programmed mode of the given pipe. */
  329. struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
  330. struct drm_crtc *crtc)
  331. {
  332. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  333. int pipe = gma_crtc->pipe;
  334. struct drm_display_mode *mode;
  335. int htot;
  336. int hsync;
  337. int vtot;
  338. int vsync;
  339. struct drm_psb_private *dev_priv = dev->dev_private;
  340. struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
  341. const struct psb_offset *map = &dev_priv->regmap[pipe];
  342. if (gma_power_begin(dev, false)) {
  343. htot = REG_READ(map->htotal);
  344. hsync = REG_READ(map->hsync);
  345. vtot = REG_READ(map->vtotal);
  346. vsync = REG_READ(map->vsync);
  347. gma_power_end(dev);
  348. } else {
  349. htot = p->htotal;
  350. hsync = p->hsync;
  351. vtot = p->vtotal;
  352. vsync = p->vsync;
  353. }
  354. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  355. if (!mode)
  356. return NULL;
  357. mode->clock = psb_intel_crtc_clock_get(dev, crtc);
  358. mode->hdisplay = (htot & 0xffff) + 1;
  359. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  360. mode->hsync_start = (hsync & 0xffff) + 1;
  361. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  362. mode->vdisplay = (vtot & 0xffff) + 1;
  363. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  364. mode->vsync_start = (vsync & 0xffff) + 1;
  365. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  366. drm_mode_set_name(mode);
  367. drm_mode_set_crtcinfo(mode, 0);
  368. return mode;
  369. }
  370. const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
  371. .dpms = gma_crtc_dpms,
  372. .mode_fixup = gma_crtc_mode_fixup,
  373. .mode_set = psb_intel_crtc_mode_set,
  374. .mode_set_base = gma_pipe_set_base,
  375. .prepare = gma_crtc_prepare,
  376. .commit = gma_crtc_commit,
  377. .disable = gma_crtc_disable,
  378. };
  379. const struct drm_crtc_funcs psb_intel_crtc_funcs = {
  380. .save = gma_crtc_save,
  381. .restore = gma_crtc_restore,
  382. .cursor_set = gma_crtc_cursor_set,
  383. .cursor_move = gma_crtc_cursor_move,
  384. .gamma_set = gma_crtc_gamma_set,
  385. .set_config = gma_crtc_set_config,
  386. .destroy = gma_crtc_destroy,
  387. };
  388. const struct gma_clock_funcs psb_clock_funcs = {
  389. .clock = psb_intel_clock,
  390. .limit = psb_intel_limit,
  391. .pll_is_valid = gma_pll_is_valid,
  392. };
  393. /*
  394. * Set the default value of cursor control and base register
  395. * to zero. This is a workaround for h/w defect on Oaktrail
  396. */
  397. static void psb_intel_cursor_init(struct drm_device *dev,
  398. struct gma_crtc *gma_crtc)
  399. {
  400. struct drm_psb_private *dev_priv = dev->dev_private;
  401. u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
  402. u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
  403. struct gtt_range *cursor_gt;
  404. if (dev_priv->ops->cursor_needs_phys) {
  405. /* Allocate 4 pages of stolen mem for a hardware cursor. That
  406. * is enough for the 64 x 64 ARGB cursors we support.
  407. */
  408. cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
  409. PAGE_SIZE);
  410. if (!cursor_gt) {
  411. gma_crtc->cursor_gt = NULL;
  412. goto out;
  413. }
  414. gma_crtc->cursor_gt = cursor_gt;
  415. gma_crtc->cursor_addr = dev_priv->stolen_base +
  416. cursor_gt->offset;
  417. } else {
  418. gma_crtc->cursor_gt = NULL;
  419. }
  420. out:
  421. REG_WRITE(control[gma_crtc->pipe], 0);
  422. REG_WRITE(base[gma_crtc->pipe], 0);
  423. }
  424. void psb_intel_crtc_init(struct drm_device *dev, int pipe,
  425. struct psb_intel_mode_device *mode_dev)
  426. {
  427. struct drm_psb_private *dev_priv = dev->dev_private;
  428. struct gma_crtc *gma_crtc;
  429. int i;
  430. uint16_t *r_base, *g_base, *b_base;
  431. /* We allocate a extra array of drm_connector pointers
  432. * for fbdev after the crtc */
  433. gma_crtc = kzalloc(sizeof(struct gma_crtc) +
  434. (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
  435. GFP_KERNEL);
  436. if (gma_crtc == NULL)
  437. return;
  438. gma_crtc->crtc_state =
  439. kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
  440. if (!gma_crtc->crtc_state) {
  441. dev_err(dev->dev, "Crtc state error: No memory\n");
  442. kfree(gma_crtc);
  443. return;
  444. }
  445. /* Set the CRTC operations from the chip specific data */
  446. drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
  447. /* Set the CRTC clock functions from chip specific data */
  448. gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
  449. drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
  450. gma_crtc->pipe = pipe;
  451. gma_crtc->plane = pipe;
  452. r_base = gma_crtc->base.gamma_store;
  453. g_base = r_base + 256;
  454. b_base = g_base + 256;
  455. for (i = 0; i < 256; i++) {
  456. gma_crtc->lut_r[i] = i;
  457. gma_crtc->lut_g[i] = i;
  458. gma_crtc->lut_b[i] = i;
  459. r_base[i] = i << 8;
  460. g_base[i] = i << 8;
  461. b_base[i] = i << 8;
  462. gma_crtc->lut_adj[i] = 0;
  463. }
  464. gma_crtc->mode_dev = mode_dev;
  465. gma_crtc->cursor_addr = 0;
  466. drm_crtc_helper_add(&gma_crtc->base,
  467. dev_priv->ops->crtc_helper);
  468. /* Setup the array of drm_connector pointer array */
  469. gma_crtc->mode_set.crtc = &gma_crtc->base;
  470. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  471. dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
  472. dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
  473. dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
  474. gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
  475. gma_crtc->mode_set.num_connectors = 0;
  476. psb_intel_cursor_init(dev, gma_crtc);
  477. /* Set to true so that the pipe is forced off on initial config. */
  478. gma_crtc->active = true;
  479. }
  480. struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  481. {
  482. struct drm_crtc *crtc = NULL;
  483. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  484. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  485. if (gma_crtc->pipe == pipe)
  486. break;
  487. }
  488. return crtc;
  489. }
  490. int gma_connector_clones(struct drm_device *dev, int type_mask)
  491. {
  492. int index_mask = 0;
  493. struct drm_connector *connector;
  494. int entry = 0;
  495. list_for_each_entry(connector, &dev->mode_config.connector_list,
  496. head) {
  497. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  498. if (type_mask & (1 << gma_encoder->type))
  499. index_mask |= (1 << entry);
  500. entry++;
  501. }
  502. return index_mask;
  503. }