psb_intel_sdvo.c 80 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/module.h>
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "psb_intel_drv.h"
  36. #include <drm/gma_drm.h>
  37. #include "psb_drv.h"
  38. #include "psb_intel_sdvo_regs.h"
  39. #include "psb_intel_reg.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct psb_intel_sdvo {
  61. struct gma_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. int sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct psb_intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /**
  82. * This is used to select the color range of RBG outputs in HDMI mode.
  83. * It is only valid when using TMDS encoding and 8 bit per color mode.
  84. */
  85. uint32_t color_range;
  86. /**
  87. * This is set if we're going to treat the device as TV-out.
  88. *
  89. * While we have these nice friendly flags for output types that ought
  90. * to decide this for us, the S-Video output on our HDMI+S-Video card
  91. * shows up as RGB1 (VGA).
  92. */
  93. bool is_tv;
  94. /* This is for current tv format name */
  95. int tv_format_index;
  96. /**
  97. * This is set if we treat the device as HDMI, instead of DVI.
  98. */
  99. bool is_hdmi;
  100. bool has_hdmi_monitor;
  101. bool has_hdmi_audio;
  102. /**
  103. * This is set if we detect output of sdvo device as LVDS and
  104. * have a valid fixed mode to use with the panel.
  105. */
  106. bool is_lvds;
  107. /**
  108. * This is sdvo fixed pannel mode pointer
  109. */
  110. struct drm_display_mode *sdvo_lvds_fixed_mode;
  111. /* DDC bus used by this SDVO encoder */
  112. uint8_t ddc_bus;
  113. /* Input timings for adjusted_mode */
  114. struct psb_intel_sdvo_dtd input_dtd;
  115. /* Saved SDVO output states */
  116. uint32_t saveSDVO; /* Can be SDVOB or SDVOC depending on sdvo_reg */
  117. };
  118. struct psb_intel_sdvo_connector {
  119. struct gma_connector base;
  120. /* Mark the type of connector */
  121. uint16_t output_flag;
  122. int force_audio;
  123. /* This contains all current supported TV format */
  124. u8 tv_format_supported[TV_FORMAT_NUM];
  125. int format_supported_num;
  126. struct drm_property *tv_format;
  127. /* add the property for the SDVO-TV */
  128. struct drm_property *left;
  129. struct drm_property *right;
  130. struct drm_property *top;
  131. struct drm_property *bottom;
  132. struct drm_property *hpos;
  133. struct drm_property *vpos;
  134. struct drm_property *contrast;
  135. struct drm_property *saturation;
  136. struct drm_property *hue;
  137. struct drm_property *sharpness;
  138. struct drm_property *flicker_filter;
  139. struct drm_property *flicker_filter_adaptive;
  140. struct drm_property *flicker_filter_2d;
  141. struct drm_property *tv_chroma_filter;
  142. struct drm_property *tv_luma_filter;
  143. struct drm_property *dot_crawl;
  144. /* add the property for the SDVO-TV/LVDS */
  145. struct drm_property *brightness;
  146. /* Add variable to record current setting for the above property */
  147. u32 left_margin, right_margin, top_margin, bottom_margin;
  148. /* this is to get the range of margin.*/
  149. u32 max_hscan, max_vscan;
  150. u32 max_hpos, cur_hpos;
  151. u32 max_vpos, cur_vpos;
  152. u32 cur_brightness, max_brightness;
  153. u32 cur_contrast, max_contrast;
  154. u32 cur_saturation, max_saturation;
  155. u32 cur_hue, max_hue;
  156. u32 cur_sharpness, max_sharpness;
  157. u32 cur_flicker_filter, max_flicker_filter;
  158. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  159. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  160. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  161. u32 cur_tv_luma_filter, max_tv_luma_filter;
  162. u32 cur_dot_crawl, max_dot_crawl;
  163. };
  164. static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
  165. {
  166. return container_of(encoder, struct psb_intel_sdvo, base.base);
  167. }
  168. static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  169. {
  170. return container_of(gma_attached_encoder(connector),
  171. struct psb_intel_sdvo, base);
  172. }
  173. static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
  174. {
  175. return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base);
  176. }
  177. static bool
  178. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
  179. static bool
  180. psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  181. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  182. int type);
  183. static bool
  184. psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  185. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
  186. /**
  187. * Writes the SDVOB or SDVOC with the given value, but always writes both
  188. * SDVOB and SDVOC to work around apparent hardware issues (according to
  189. * comments in the BIOS).
  190. */
  191. static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
  192. {
  193. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  194. u32 bval = val, cval = val;
  195. int i, j;
  196. int need_aux = IS_MRST(dev) ? 1 : 0;
  197. for (j = 0; j <= need_aux; j++) {
  198. if (psb_intel_sdvo->sdvo_reg == SDVOB)
  199. cval = REG_READ_WITH_AUX(SDVOC, j);
  200. else
  201. bval = REG_READ_WITH_AUX(SDVOB, j);
  202. /*
  203. * Write the registers twice for luck. Sometimes,
  204. * writing them only once doesn't appear to 'stick'.
  205. * The BIOS does this too. Yay, magic
  206. */
  207. for (i = 0; i < 2; i++) {
  208. REG_WRITE_WITH_AUX(SDVOB, bval, j);
  209. REG_READ_WITH_AUX(SDVOB, j);
  210. REG_WRITE_WITH_AUX(SDVOC, cval, j);
  211. REG_READ_WITH_AUX(SDVOC, j);
  212. }
  213. }
  214. }
  215. static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
  216. {
  217. struct i2c_msg msgs[] = {
  218. {
  219. .addr = psb_intel_sdvo->slave_addr,
  220. .flags = 0,
  221. .len = 1,
  222. .buf = &addr,
  223. },
  224. {
  225. .addr = psb_intel_sdvo->slave_addr,
  226. .flags = I2C_M_RD,
  227. .len = 1,
  228. .buf = ch,
  229. }
  230. };
  231. int ret;
  232. if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
  233. return true;
  234. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  235. return false;
  236. }
  237. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  238. /** Mapping of command numbers to names, for debug output */
  239. static const struct _sdvo_cmd_name {
  240. u8 cmd;
  241. const char *name;
  242. } sdvo_cmd_names[] = {
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  286. /* Add the op code for SDVO enhancements */
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  331. /* HDMI op code */
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  352. };
  353. #define IS_SDVOB(reg) (reg == SDVOB)
  354. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  355. static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  356. const void *args, int args_len)
  357. {
  358. int i;
  359. DRM_DEBUG_KMS("%s: W: %02X ",
  360. SDVO_NAME(psb_intel_sdvo), cmd);
  361. for (i = 0; i < args_len; i++)
  362. DRM_DEBUG_KMS("%02X ", ((u8 *)args)[i]);
  363. for (; i < 8; i++)
  364. DRM_DEBUG_KMS(" ");
  365. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  366. if (cmd == sdvo_cmd_names[i].cmd) {
  367. DRM_DEBUG_KMS("(%s)", sdvo_cmd_names[i].name);
  368. break;
  369. }
  370. }
  371. if (i == ARRAY_SIZE(sdvo_cmd_names))
  372. DRM_DEBUG_KMS("(%02X)", cmd);
  373. DRM_DEBUG_KMS("\n");
  374. }
  375. static const char *cmd_status_names[] = {
  376. "Power on",
  377. "Success",
  378. "Not supported",
  379. "Invalid arg",
  380. "Pending",
  381. "Target not specified",
  382. "Scaling not supported"
  383. };
  384. static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  385. const void *args, int args_len)
  386. {
  387. u8 buf[args_len*2 + 2], status;
  388. struct i2c_msg msgs[args_len + 3];
  389. int i, ret;
  390. psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
  391. for (i = 0; i < args_len; i++) {
  392. msgs[i].addr = psb_intel_sdvo->slave_addr;
  393. msgs[i].flags = 0;
  394. msgs[i].len = 2;
  395. msgs[i].buf = buf + 2 *i;
  396. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  397. buf[2*i + 1] = ((u8*)args)[i];
  398. }
  399. msgs[i].addr = psb_intel_sdvo->slave_addr;
  400. msgs[i].flags = 0;
  401. msgs[i].len = 2;
  402. msgs[i].buf = buf + 2*i;
  403. buf[2*i + 0] = SDVO_I2C_OPCODE;
  404. buf[2*i + 1] = cmd;
  405. /* the following two are to read the response */
  406. status = SDVO_I2C_CMD_STATUS;
  407. msgs[i+1].addr = psb_intel_sdvo->slave_addr;
  408. msgs[i+1].flags = 0;
  409. msgs[i+1].len = 1;
  410. msgs[i+1].buf = &status;
  411. msgs[i+2].addr = psb_intel_sdvo->slave_addr;
  412. msgs[i+2].flags = I2C_M_RD;
  413. msgs[i+2].len = 1;
  414. msgs[i+2].buf = &status;
  415. ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
  416. if (ret < 0) {
  417. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  418. return false;
  419. }
  420. if (ret != i+3) {
  421. /* failure in I2C transfer */
  422. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  423. return false;
  424. }
  425. return true;
  426. }
  427. static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
  428. void *response, int response_len)
  429. {
  430. u8 retry = 5;
  431. u8 status;
  432. int i;
  433. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
  434. /*
  435. * The documentation states that all commands will be
  436. * processed within 15µs, and that we need only poll
  437. * the status byte a maximum of 3 times in order for the
  438. * command to be complete.
  439. *
  440. * Check 5 times in case the hardware failed to read the docs.
  441. */
  442. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  443. SDVO_I2C_CMD_STATUS,
  444. &status))
  445. goto log_fail;
  446. while ((status == SDVO_CMD_STATUS_PENDING ||
  447. status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && retry--) {
  448. udelay(15);
  449. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  450. SDVO_I2C_CMD_STATUS,
  451. &status))
  452. goto log_fail;
  453. }
  454. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  455. DRM_DEBUG_KMS("(%s)", cmd_status_names[status]);
  456. else
  457. DRM_DEBUG_KMS("(??? %d)", status);
  458. if (status != SDVO_CMD_STATUS_SUCCESS)
  459. goto log_fail;
  460. /* Read the command response */
  461. for (i = 0; i < response_len; i++) {
  462. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  463. SDVO_I2C_RETURN_0 + i,
  464. &((u8 *)response)[i]))
  465. goto log_fail;
  466. DRM_DEBUG_KMS(" %02X", ((u8 *)response)[i]);
  467. }
  468. DRM_DEBUG_KMS("\n");
  469. return true;
  470. log_fail:
  471. DRM_DEBUG_KMS("... failed\n");
  472. return false;
  473. }
  474. static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  475. {
  476. if (mode->clock >= 100000)
  477. return 1;
  478. else if (mode->clock >= 50000)
  479. return 2;
  480. else
  481. return 4;
  482. }
  483. static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
  484. u8 ddc_bus)
  485. {
  486. /* This must be the immediately preceding write before the i2c xfer */
  487. return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  488. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  489. &ddc_bus, 1);
  490. }
  491. static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
  492. {
  493. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
  494. return false;
  495. return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
  496. }
  497. static bool
  498. psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
  499. {
  500. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
  501. return false;
  502. return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
  503. }
  504. static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
  505. {
  506. struct psb_intel_sdvo_set_target_input_args targets = {0};
  507. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  508. SDVO_CMD_SET_TARGET_INPUT,
  509. &targets, sizeof(targets));
  510. }
  511. /**
  512. * Return whether each input is trained.
  513. *
  514. * This function is making an assumption about the layout of the response,
  515. * which should be checked against the docs.
  516. */
  517. static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
  518. {
  519. struct psb_intel_sdvo_get_trained_inputs_response response;
  520. BUILD_BUG_ON(sizeof(response) != 1);
  521. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  522. &response, sizeof(response)))
  523. return false;
  524. *input_1 = response.input0_trained;
  525. *input_2 = response.input1_trained;
  526. return true;
  527. }
  528. static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
  529. u16 outputs)
  530. {
  531. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  532. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  533. &outputs, sizeof(outputs));
  534. }
  535. static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
  536. int mode)
  537. {
  538. u8 state = SDVO_ENCODER_STATE_ON;
  539. switch (mode) {
  540. case DRM_MODE_DPMS_ON:
  541. state = SDVO_ENCODER_STATE_ON;
  542. break;
  543. case DRM_MODE_DPMS_STANDBY:
  544. state = SDVO_ENCODER_STATE_STANDBY;
  545. break;
  546. case DRM_MODE_DPMS_SUSPEND:
  547. state = SDVO_ENCODER_STATE_SUSPEND;
  548. break;
  549. case DRM_MODE_DPMS_OFF:
  550. state = SDVO_ENCODER_STATE_OFF;
  551. break;
  552. }
  553. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  554. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  555. }
  556. static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
  557. int *clock_min,
  558. int *clock_max)
  559. {
  560. struct psb_intel_sdvo_pixel_clock_range clocks;
  561. BUILD_BUG_ON(sizeof(clocks) != 4);
  562. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  563. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  564. &clocks, sizeof(clocks)))
  565. return false;
  566. /* Convert the values from units of 10 kHz to kHz. */
  567. *clock_min = clocks.min * 10;
  568. *clock_max = clocks.max * 10;
  569. return true;
  570. }
  571. static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
  572. u16 outputs)
  573. {
  574. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  575. SDVO_CMD_SET_TARGET_OUTPUT,
  576. &outputs, sizeof(outputs));
  577. }
  578. static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  579. struct psb_intel_sdvo_dtd *dtd)
  580. {
  581. return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  582. psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  583. }
  584. static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  585. struct psb_intel_sdvo_dtd *dtd)
  586. {
  587. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  588. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  589. }
  590. static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  591. struct psb_intel_sdvo_dtd *dtd)
  592. {
  593. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  594. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  595. }
  596. static bool
  597. psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  598. uint16_t clock,
  599. uint16_t width,
  600. uint16_t height)
  601. {
  602. struct psb_intel_sdvo_preferred_input_timing_args args;
  603. memset(&args, 0, sizeof(args));
  604. args.clock = clock;
  605. args.width = width;
  606. args.height = height;
  607. args.interlace = 0;
  608. if (psb_intel_sdvo->is_lvds &&
  609. (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  610. psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  611. args.scaled = 1;
  612. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  613. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  614. &args, sizeof(args));
  615. }
  616. static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  617. struct psb_intel_sdvo_dtd *dtd)
  618. {
  619. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  620. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  621. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  622. &dtd->part1, sizeof(dtd->part1)) &&
  623. psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  624. &dtd->part2, sizeof(dtd->part2));
  625. }
  626. static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
  627. {
  628. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  629. }
  630. static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
  631. const struct drm_display_mode *mode)
  632. {
  633. uint16_t width, height;
  634. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  635. uint16_t h_sync_offset, v_sync_offset;
  636. width = mode->crtc_hdisplay;
  637. height = mode->crtc_vdisplay;
  638. /* do some mode translations */
  639. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  640. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  641. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  642. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  643. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  644. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  645. dtd->part1.clock = mode->clock / 10;
  646. dtd->part1.h_active = width & 0xff;
  647. dtd->part1.h_blank = h_blank_len & 0xff;
  648. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  649. ((h_blank_len >> 8) & 0xf);
  650. dtd->part1.v_active = height & 0xff;
  651. dtd->part1.v_blank = v_blank_len & 0xff;
  652. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  653. ((v_blank_len >> 8) & 0xf);
  654. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  655. dtd->part2.h_sync_width = h_sync_len & 0xff;
  656. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  657. (v_sync_len & 0xf);
  658. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  659. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  660. ((v_sync_len & 0x30) >> 4);
  661. dtd->part2.dtd_flags = 0x18;
  662. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  663. dtd->part2.dtd_flags |= 0x2;
  664. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  665. dtd->part2.dtd_flags |= 0x4;
  666. dtd->part2.sdvo_flags = 0;
  667. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  668. dtd->part2.reserved = 0;
  669. }
  670. static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  671. const struct psb_intel_sdvo_dtd *dtd)
  672. {
  673. mode->hdisplay = dtd->part1.h_active;
  674. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  675. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  676. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  677. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  678. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  679. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  680. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  681. mode->vdisplay = dtd->part1.v_active;
  682. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  683. mode->vsync_start = mode->vdisplay;
  684. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  685. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  686. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  687. mode->vsync_end = mode->vsync_start +
  688. (dtd->part2.v_sync_off_width & 0xf);
  689. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  690. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  691. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  692. mode->clock = dtd->part1.clock * 10;
  693. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  694. if (dtd->part2.dtd_flags & 0x2)
  695. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  696. if (dtd->part2.dtd_flags & 0x4)
  697. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  698. }
  699. static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
  700. {
  701. struct psb_intel_sdvo_encode encode;
  702. BUILD_BUG_ON(sizeof(encode) != 2);
  703. return psb_intel_sdvo_get_value(psb_intel_sdvo,
  704. SDVO_CMD_GET_SUPP_ENCODE,
  705. &encode, sizeof(encode));
  706. }
  707. static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
  708. uint8_t mode)
  709. {
  710. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  711. }
  712. static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
  713. uint8_t mode)
  714. {
  715. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  716. }
  717. #if 0
  718. static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
  719. {
  720. int i, j;
  721. uint8_t set_buf_index[2];
  722. uint8_t av_split;
  723. uint8_t buf_size;
  724. uint8_t buf[48];
  725. uint8_t *pos;
  726. psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  727. for (i = 0; i <= av_split; i++) {
  728. set_buf_index[0] = i; set_buf_index[1] = 0;
  729. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  730. set_buf_index, 2);
  731. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  732. psb_intel_sdvo_read_response(encoder, &buf_size, 1);
  733. pos = buf;
  734. for (j = 0; j <= buf_size; j += 8) {
  735. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  736. NULL, 0);
  737. psb_intel_sdvo_read_response(encoder, pos, 8);
  738. pos += 8;
  739. }
  740. }
  741. }
  742. #endif
  743. static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
  744. {
  745. DRM_INFO("HDMI is not supported yet");
  746. return false;
  747. #if 0
  748. struct dip_infoframe avi_if = {
  749. .type = DIP_TYPE_AVI,
  750. .ver = DIP_VERSION_AVI,
  751. .len = DIP_LEN_AVI,
  752. };
  753. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  754. uint8_t set_buf_index[2] = { 1, 0 };
  755. uint64_t *data = (uint64_t *)&avi_if;
  756. unsigned i;
  757. intel_dip_infoframe_csum(&avi_if);
  758. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  759. SDVO_CMD_SET_HBUF_INDEX,
  760. set_buf_index, 2))
  761. return false;
  762. for (i = 0; i < sizeof(avi_if); i += 8) {
  763. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  764. SDVO_CMD_SET_HBUF_DATA,
  765. data, 8))
  766. return false;
  767. data++;
  768. }
  769. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  770. SDVO_CMD_SET_HBUF_TXRATE,
  771. &tx_rate, 1);
  772. #endif
  773. }
  774. static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
  775. {
  776. struct psb_intel_sdvo_tv_format format;
  777. uint32_t format_map;
  778. format_map = 1 << psb_intel_sdvo->tv_format_index;
  779. memset(&format, 0, sizeof(format));
  780. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  781. BUILD_BUG_ON(sizeof(format) != 6);
  782. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  783. SDVO_CMD_SET_TV_FORMAT,
  784. &format, sizeof(format));
  785. }
  786. static bool
  787. psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  788. const struct drm_display_mode *mode)
  789. {
  790. struct psb_intel_sdvo_dtd output_dtd;
  791. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  792. psb_intel_sdvo->attached_output))
  793. return false;
  794. psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  795. if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
  796. return false;
  797. return true;
  798. }
  799. static bool
  800. psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  801. const struct drm_display_mode *mode,
  802. struct drm_display_mode *adjusted_mode)
  803. {
  804. /* Reset the input timing to the screen. Assume always input 0. */
  805. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  806. return false;
  807. if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
  808. mode->clock / 10,
  809. mode->hdisplay,
  810. mode->vdisplay))
  811. return false;
  812. if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
  813. &psb_intel_sdvo->input_dtd))
  814. return false;
  815. psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
  816. drm_mode_set_crtcinfo(adjusted_mode, 0);
  817. return true;
  818. }
  819. static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  820. const struct drm_display_mode *mode,
  821. struct drm_display_mode *adjusted_mode)
  822. {
  823. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  824. int multiplier;
  825. /* We need to construct preferred input timings based on our
  826. * output timings. To do that, we have to set the output
  827. * timings, even though this isn't really the right place in
  828. * the sequence to do it. Oh well.
  829. */
  830. if (psb_intel_sdvo->is_tv) {
  831. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
  832. return false;
  833. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  834. mode,
  835. adjusted_mode);
  836. } else if (psb_intel_sdvo->is_lvds) {
  837. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
  838. psb_intel_sdvo->sdvo_lvds_fixed_mode))
  839. return false;
  840. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  841. mode,
  842. adjusted_mode);
  843. }
  844. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  845. * SDVO device will factor out the multiplier during mode_set.
  846. */
  847. multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
  848. psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  849. return true;
  850. }
  851. static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
  852. struct drm_display_mode *mode,
  853. struct drm_display_mode *adjusted_mode)
  854. {
  855. struct drm_device *dev = encoder->dev;
  856. struct drm_crtc *crtc = encoder->crtc;
  857. struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  858. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  859. u32 sdvox;
  860. struct psb_intel_sdvo_in_out_map in_out;
  861. struct psb_intel_sdvo_dtd input_dtd;
  862. int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
  863. int rate;
  864. int need_aux = IS_MRST(dev) ? 1 : 0;
  865. if (!mode)
  866. return;
  867. /* First, set the input mapping for the first input to our controlled
  868. * output. This is only correct if we're a single-input device, in
  869. * which case the first input is the output from the appropriate SDVO
  870. * channel on the motherboard. In a two-input device, the first input
  871. * will be SDVOB and the second SDVOC.
  872. */
  873. in_out.in0 = psb_intel_sdvo->attached_output;
  874. in_out.in1 = 0;
  875. psb_intel_sdvo_set_value(psb_intel_sdvo,
  876. SDVO_CMD_SET_IN_OUT_MAP,
  877. &in_out, sizeof(in_out));
  878. /* Set the output timings to the screen */
  879. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  880. psb_intel_sdvo->attached_output))
  881. return;
  882. /* We have tried to get input timing in mode_fixup, and filled into
  883. * adjusted_mode.
  884. */
  885. if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
  886. input_dtd = psb_intel_sdvo->input_dtd;
  887. } else {
  888. /* Set the output timing to the screen */
  889. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  890. psb_intel_sdvo->attached_output))
  891. return;
  892. psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  893. (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
  894. }
  895. /* Set the input timing to the screen. Assume always input 0. */
  896. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  897. return;
  898. if (psb_intel_sdvo->has_hdmi_monitor) {
  899. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
  900. psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
  901. SDVO_COLORIMETRY_RGB256);
  902. psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
  903. } else
  904. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
  905. if (psb_intel_sdvo->is_tv &&
  906. !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
  907. return;
  908. (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
  909. switch (pixel_multiplier) {
  910. default:
  911. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  912. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  913. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  914. }
  915. if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
  916. return;
  917. /* Set the SDVO control regs. */
  918. if (need_aux)
  919. sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
  920. else
  921. sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
  922. switch (psb_intel_sdvo->sdvo_reg) {
  923. case SDVOB:
  924. sdvox &= SDVOB_PRESERVE_MASK;
  925. break;
  926. case SDVOC:
  927. sdvox &= SDVOC_PRESERVE_MASK;
  928. break;
  929. }
  930. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  931. if (gma_crtc->pipe == 1)
  932. sdvox |= SDVO_PIPE_B_SELECT;
  933. if (psb_intel_sdvo->has_hdmi_audio)
  934. sdvox |= SDVO_AUDIO_ENABLE;
  935. /* FIXME: Check if this is needed for PSB
  936. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  937. */
  938. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
  939. sdvox |= SDVO_STALL_SELECT;
  940. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
  941. }
  942. static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  943. {
  944. struct drm_device *dev = encoder->dev;
  945. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  946. u32 temp;
  947. int i;
  948. int need_aux = IS_MRST(dev) ? 1 : 0;
  949. switch (mode) {
  950. case DRM_MODE_DPMS_ON:
  951. DRM_DEBUG("DPMS_ON");
  952. break;
  953. case DRM_MODE_DPMS_OFF:
  954. DRM_DEBUG("DPMS_OFF");
  955. break;
  956. default:
  957. DRM_DEBUG("DPMS: %d", mode);
  958. }
  959. if (mode != DRM_MODE_DPMS_ON) {
  960. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
  961. if (0)
  962. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  963. if (mode == DRM_MODE_DPMS_OFF) {
  964. if (need_aux)
  965. temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
  966. else
  967. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  968. if ((temp & SDVO_ENABLE) != 0) {
  969. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
  970. }
  971. }
  972. } else {
  973. bool input1, input2;
  974. u8 status;
  975. if (need_aux)
  976. temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
  977. else
  978. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  979. if ((temp & SDVO_ENABLE) == 0)
  980. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
  981. for (i = 0; i < 2; i++)
  982. gma_wait_for_vblank(dev);
  983. status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
  984. /* Warn if the device reported failure to sync.
  985. * A lot of SDVO devices fail to notify of sync, but it's
  986. * a given it the status is a success, we succeeded.
  987. */
  988. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  989. DRM_DEBUG_KMS("First %s output reported failure to "
  990. "sync\n", SDVO_NAME(psb_intel_sdvo));
  991. }
  992. if (0)
  993. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  994. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
  995. }
  996. return;
  997. }
  998. static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
  999. struct drm_display_mode *mode)
  1000. {
  1001. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1002. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1003. return MODE_NO_DBLESCAN;
  1004. if (psb_intel_sdvo->pixel_clock_min > mode->clock)
  1005. return MODE_CLOCK_LOW;
  1006. if (psb_intel_sdvo->pixel_clock_max < mode->clock)
  1007. return MODE_CLOCK_HIGH;
  1008. if (psb_intel_sdvo->is_lvds) {
  1009. if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1010. return MODE_PANEL;
  1011. if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1012. return MODE_PANEL;
  1013. }
  1014. return MODE_OK;
  1015. }
  1016. static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
  1017. {
  1018. BUILD_BUG_ON(sizeof(*caps) != 8);
  1019. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1020. SDVO_CMD_GET_DEVICE_CAPS,
  1021. caps, sizeof(*caps)))
  1022. return false;
  1023. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1024. " vendor_id: %d\n"
  1025. " device_id: %d\n"
  1026. " device_rev_id: %d\n"
  1027. " sdvo_version_major: %d\n"
  1028. " sdvo_version_minor: %d\n"
  1029. " sdvo_inputs_mask: %d\n"
  1030. " smooth_scaling: %d\n"
  1031. " sharp_scaling: %d\n"
  1032. " up_scaling: %d\n"
  1033. " down_scaling: %d\n"
  1034. " stall_support: %d\n"
  1035. " output_flags: %d\n",
  1036. caps->vendor_id,
  1037. caps->device_id,
  1038. caps->device_rev_id,
  1039. caps->sdvo_version_major,
  1040. caps->sdvo_version_minor,
  1041. caps->sdvo_inputs_mask,
  1042. caps->smooth_scaling,
  1043. caps->sharp_scaling,
  1044. caps->up_scaling,
  1045. caps->down_scaling,
  1046. caps->stall_support,
  1047. caps->output_flags);
  1048. return true;
  1049. }
  1050. /* No use! */
  1051. #if 0
  1052. struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1053. {
  1054. struct drm_connector *connector = NULL;
  1055. struct psb_intel_sdvo *iout = NULL;
  1056. struct psb_intel_sdvo *sdvo;
  1057. /* find the sdvo connector */
  1058. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1059. iout = to_psb_intel_sdvo(connector);
  1060. if (iout->type != INTEL_OUTPUT_SDVO)
  1061. continue;
  1062. sdvo = iout->dev_priv;
  1063. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1064. return connector;
  1065. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1066. return connector;
  1067. }
  1068. return NULL;
  1069. }
  1070. int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1071. {
  1072. u8 response[2];
  1073. u8 status;
  1074. struct psb_intel_sdvo *psb_intel_sdvo;
  1075. DRM_DEBUG_KMS("\n");
  1076. if (!connector)
  1077. return 0;
  1078. psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1079. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1080. &response, 2) && response[0];
  1081. }
  1082. void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1083. {
  1084. u8 response[2];
  1085. u8 status;
  1086. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1087. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1088. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1089. if (on) {
  1090. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1091. status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1092. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1093. } else {
  1094. response[0] = 0;
  1095. response[1] = 0;
  1096. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1097. }
  1098. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1099. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1100. }
  1101. #endif
  1102. static bool
  1103. psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
  1104. {
  1105. /* Is there more than one type of output? */
  1106. int caps = psb_intel_sdvo->caps.output_flags & 0xf;
  1107. return caps & -caps;
  1108. }
  1109. static struct edid *
  1110. psb_intel_sdvo_get_edid(struct drm_connector *connector)
  1111. {
  1112. struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1113. return drm_get_edid(connector, &sdvo->ddc);
  1114. }
  1115. /* Mac mini hack -- use the same DDC as the analog connector */
  1116. static struct edid *
  1117. psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1118. {
  1119. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1120. return drm_get_edid(connector,
  1121. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1122. }
  1123. static enum drm_connector_status
  1124. psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1125. {
  1126. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1127. enum drm_connector_status status;
  1128. struct edid *edid;
  1129. edid = psb_intel_sdvo_get_edid(connector);
  1130. if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
  1131. u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
  1132. /*
  1133. * Don't use the 1 as the argument of DDC bus switch to get
  1134. * the EDID. It is used for SDVO SPD ROM.
  1135. */
  1136. for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1137. psb_intel_sdvo->ddc_bus = ddc;
  1138. edid = psb_intel_sdvo_get_edid(connector);
  1139. if (edid)
  1140. break;
  1141. }
  1142. /*
  1143. * If we found the EDID on the other bus,
  1144. * assume that is the correct DDC bus.
  1145. */
  1146. if (edid == NULL)
  1147. psb_intel_sdvo->ddc_bus = saved_ddc;
  1148. }
  1149. /*
  1150. * When there is no edid and no monitor is connected with VGA
  1151. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1152. */
  1153. if (edid == NULL)
  1154. edid = psb_intel_sdvo_get_analog_edid(connector);
  1155. status = connector_status_unknown;
  1156. if (edid != NULL) {
  1157. /* DDC bus is shared, match EDID to connector type */
  1158. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1159. status = connector_status_connected;
  1160. if (psb_intel_sdvo->is_hdmi) {
  1161. psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1162. psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1163. }
  1164. } else
  1165. status = connector_status_disconnected;
  1166. kfree(edid);
  1167. }
  1168. if (status == connector_status_connected) {
  1169. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1170. if (psb_intel_sdvo_connector->force_audio)
  1171. psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
  1172. }
  1173. return status;
  1174. }
  1175. static enum drm_connector_status
  1176. psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
  1177. {
  1178. uint16_t response;
  1179. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1180. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1181. enum drm_connector_status ret;
  1182. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1183. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1184. return connector_status_unknown;
  1185. /* add 30ms delay when the output type might be TV */
  1186. if (psb_intel_sdvo->caps.output_flags &
  1187. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1188. mdelay(30);
  1189. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
  1190. return connector_status_unknown;
  1191. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1192. response & 0xff, response >> 8,
  1193. psb_intel_sdvo_connector->output_flag);
  1194. if (response == 0)
  1195. return connector_status_disconnected;
  1196. psb_intel_sdvo->attached_output = response;
  1197. psb_intel_sdvo->has_hdmi_monitor = false;
  1198. psb_intel_sdvo->has_hdmi_audio = false;
  1199. if ((psb_intel_sdvo_connector->output_flag & response) == 0)
  1200. ret = connector_status_disconnected;
  1201. else if (IS_TMDS(psb_intel_sdvo_connector))
  1202. ret = psb_intel_sdvo_hdmi_sink_detect(connector);
  1203. else {
  1204. struct edid *edid;
  1205. /* if we have an edid check it matches the connection */
  1206. edid = psb_intel_sdvo_get_edid(connector);
  1207. if (edid == NULL)
  1208. edid = psb_intel_sdvo_get_analog_edid(connector);
  1209. if (edid != NULL) {
  1210. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1211. ret = connector_status_disconnected;
  1212. else
  1213. ret = connector_status_connected;
  1214. kfree(edid);
  1215. } else
  1216. ret = connector_status_connected;
  1217. }
  1218. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1219. if (ret == connector_status_connected) {
  1220. psb_intel_sdvo->is_tv = false;
  1221. psb_intel_sdvo->is_lvds = false;
  1222. psb_intel_sdvo->base.needs_tv_clock = false;
  1223. if (response & SDVO_TV_MASK) {
  1224. psb_intel_sdvo->is_tv = true;
  1225. psb_intel_sdvo->base.needs_tv_clock = true;
  1226. }
  1227. if (response & SDVO_LVDS_MASK)
  1228. psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1229. }
  1230. return ret;
  1231. }
  1232. static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1233. {
  1234. struct edid *edid;
  1235. /* set the bus switch and get the modes */
  1236. edid = psb_intel_sdvo_get_edid(connector);
  1237. /*
  1238. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1239. * link between analog and digital outputs. So, if the regular SDVO
  1240. * DDC fails, check to see if the analog output is disconnected, in
  1241. * which case we'll look there for the digital DDC data.
  1242. */
  1243. if (edid == NULL)
  1244. edid = psb_intel_sdvo_get_analog_edid(connector);
  1245. if (edid != NULL) {
  1246. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1247. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1248. bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
  1249. if (connector_is_digital == monitor_is_digital) {
  1250. drm_mode_connector_update_edid_property(connector, edid);
  1251. drm_add_edid_modes(connector, edid);
  1252. }
  1253. kfree(edid);
  1254. }
  1255. }
  1256. /*
  1257. * Set of SDVO TV modes.
  1258. * Note! This is in reply order (see loop in get_tv_modes).
  1259. * XXX: all 60Hz refresh?
  1260. */
  1261. static const struct drm_display_mode sdvo_tv_modes[] = {
  1262. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1263. 416, 0, 200, 201, 232, 233, 0,
  1264. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1265. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1266. 416, 0, 240, 241, 272, 273, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1268. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1269. 496, 0, 300, 301, 332, 333, 0,
  1270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1271. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1272. 736, 0, 350, 351, 382, 383, 0,
  1273. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1274. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1275. 736, 0, 400, 401, 432, 433, 0,
  1276. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1277. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1278. 736, 0, 480, 481, 512, 513, 0,
  1279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1280. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1281. 800, 0, 480, 481, 512, 513, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1283. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1284. 800, 0, 576, 577, 608, 609, 0,
  1285. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1286. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1287. 816, 0, 350, 351, 382, 383, 0,
  1288. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1289. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1290. 816, 0, 400, 401, 432, 433, 0,
  1291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1292. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1293. 816, 0, 480, 481, 512, 513, 0,
  1294. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1295. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1296. 816, 0, 540, 541, 572, 573, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1298. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1299. 816, 0, 576, 577, 608, 609, 0,
  1300. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1301. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1302. 864, 0, 576, 577, 608, 609, 0,
  1303. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1304. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1305. 896, 0, 600, 601, 632, 633, 0,
  1306. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1307. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1308. 928, 0, 624, 625, 656, 657, 0,
  1309. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1310. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1311. 1016, 0, 766, 767, 798, 799, 0,
  1312. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1313. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1314. 1120, 0, 768, 769, 800, 801, 0,
  1315. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1316. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1317. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1318. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1319. };
  1320. static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1321. {
  1322. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1323. struct psb_intel_sdvo_sdtv_resolution_request tv_res;
  1324. uint32_t reply = 0, format_map = 0;
  1325. int i;
  1326. /* Read the list of supported input resolutions for the selected TV
  1327. * format.
  1328. */
  1329. format_map = 1 << psb_intel_sdvo->tv_format_index;
  1330. memcpy(&tv_res, &format_map,
  1331. min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
  1332. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
  1333. return;
  1334. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1335. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1336. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1337. &tv_res, sizeof(tv_res)))
  1338. return;
  1339. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
  1340. return;
  1341. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1342. if (reply & (1 << i)) {
  1343. struct drm_display_mode *nmode;
  1344. nmode = drm_mode_duplicate(connector->dev,
  1345. &sdvo_tv_modes[i]);
  1346. if (nmode)
  1347. drm_mode_probed_add(connector, nmode);
  1348. }
  1349. }
  1350. static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1351. {
  1352. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1353. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1354. struct drm_display_mode *newmode;
  1355. /*
  1356. * Attempt to get the mode list from DDC.
  1357. * Assume that the preferred modes are
  1358. * arranged in priority order.
  1359. */
  1360. psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
  1361. if (list_empty(&connector->probed_modes) == false)
  1362. goto end;
  1363. /* Fetch modes from VBT */
  1364. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1365. newmode = drm_mode_duplicate(connector->dev,
  1366. dev_priv->sdvo_lvds_vbt_mode);
  1367. if (newmode != NULL) {
  1368. /* Guarantee the mode is preferred */
  1369. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1370. DRM_MODE_TYPE_DRIVER);
  1371. drm_mode_probed_add(connector, newmode);
  1372. }
  1373. }
  1374. end:
  1375. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1376. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1377. psb_intel_sdvo->sdvo_lvds_fixed_mode =
  1378. drm_mode_duplicate(connector->dev, newmode);
  1379. drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
  1380. 0);
  1381. psb_intel_sdvo->is_lvds = true;
  1382. break;
  1383. }
  1384. }
  1385. }
  1386. static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
  1387. {
  1388. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1389. if (IS_TV(psb_intel_sdvo_connector))
  1390. psb_intel_sdvo_get_tv_modes(connector);
  1391. else if (IS_LVDS(psb_intel_sdvo_connector))
  1392. psb_intel_sdvo_get_lvds_modes(connector);
  1393. else
  1394. psb_intel_sdvo_get_ddc_modes(connector);
  1395. return !list_empty(&connector->probed_modes);
  1396. }
  1397. static void psb_intel_sdvo_destroy(struct drm_connector *connector)
  1398. {
  1399. drm_connector_unregister(connector);
  1400. drm_connector_cleanup(connector);
  1401. kfree(connector);
  1402. }
  1403. static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1404. {
  1405. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1406. struct edid *edid;
  1407. bool has_audio = false;
  1408. if (!psb_intel_sdvo->is_hdmi)
  1409. return false;
  1410. edid = psb_intel_sdvo_get_edid(connector);
  1411. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1412. has_audio = drm_detect_monitor_audio(edid);
  1413. return has_audio;
  1414. }
  1415. static int
  1416. psb_intel_sdvo_set_property(struct drm_connector *connector,
  1417. struct drm_property *property,
  1418. uint64_t val)
  1419. {
  1420. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1421. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1422. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1423. uint16_t temp_value;
  1424. uint8_t cmd;
  1425. int ret;
  1426. ret = drm_object_property_set_value(&connector->base, property, val);
  1427. if (ret)
  1428. return ret;
  1429. if (property == dev_priv->force_audio_property) {
  1430. int i = val;
  1431. bool has_audio;
  1432. if (i == psb_intel_sdvo_connector->force_audio)
  1433. return 0;
  1434. psb_intel_sdvo_connector->force_audio = i;
  1435. if (i == 0)
  1436. has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
  1437. else
  1438. has_audio = i > 0;
  1439. if (has_audio == psb_intel_sdvo->has_hdmi_audio)
  1440. return 0;
  1441. psb_intel_sdvo->has_hdmi_audio = has_audio;
  1442. goto done;
  1443. }
  1444. if (property == dev_priv->broadcast_rgb_property) {
  1445. if (val == !!psb_intel_sdvo->color_range)
  1446. return 0;
  1447. psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1448. goto done;
  1449. }
  1450. #define CHECK_PROPERTY(name, NAME) \
  1451. if (psb_intel_sdvo_connector->name == property) { \
  1452. if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1453. if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1454. cmd = SDVO_CMD_SET_##NAME; \
  1455. psb_intel_sdvo_connector->cur_##name = temp_value; \
  1456. goto set_value; \
  1457. }
  1458. if (property == psb_intel_sdvo_connector->tv_format) {
  1459. if (val >= TV_FORMAT_NUM)
  1460. return -EINVAL;
  1461. if (psb_intel_sdvo->tv_format_index ==
  1462. psb_intel_sdvo_connector->tv_format_supported[val])
  1463. return 0;
  1464. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
  1465. goto done;
  1466. } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
  1467. temp_value = val;
  1468. if (psb_intel_sdvo_connector->left == property) {
  1469. drm_object_property_set_value(&connector->base,
  1470. psb_intel_sdvo_connector->right, val);
  1471. if (psb_intel_sdvo_connector->left_margin == temp_value)
  1472. return 0;
  1473. psb_intel_sdvo_connector->left_margin = temp_value;
  1474. psb_intel_sdvo_connector->right_margin = temp_value;
  1475. temp_value = psb_intel_sdvo_connector->max_hscan -
  1476. psb_intel_sdvo_connector->left_margin;
  1477. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1478. goto set_value;
  1479. } else if (psb_intel_sdvo_connector->right == property) {
  1480. drm_object_property_set_value(&connector->base,
  1481. psb_intel_sdvo_connector->left, val);
  1482. if (psb_intel_sdvo_connector->right_margin == temp_value)
  1483. return 0;
  1484. psb_intel_sdvo_connector->left_margin = temp_value;
  1485. psb_intel_sdvo_connector->right_margin = temp_value;
  1486. temp_value = psb_intel_sdvo_connector->max_hscan -
  1487. psb_intel_sdvo_connector->left_margin;
  1488. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1489. goto set_value;
  1490. } else if (psb_intel_sdvo_connector->top == property) {
  1491. drm_object_property_set_value(&connector->base,
  1492. psb_intel_sdvo_connector->bottom, val);
  1493. if (psb_intel_sdvo_connector->top_margin == temp_value)
  1494. return 0;
  1495. psb_intel_sdvo_connector->top_margin = temp_value;
  1496. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1497. temp_value = psb_intel_sdvo_connector->max_vscan -
  1498. psb_intel_sdvo_connector->top_margin;
  1499. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1500. goto set_value;
  1501. } else if (psb_intel_sdvo_connector->bottom == property) {
  1502. drm_object_property_set_value(&connector->base,
  1503. psb_intel_sdvo_connector->top, val);
  1504. if (psb_intel_sdvo_connector->bottom_margin == temp_value)
  1505. return 0;
  1506. psb_intel_sdvo_connector->top_margin = temp_value;
  1507. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1508. temp_value = psb_intel_sdvo_connector->max_vscan -
  1509. psb_intel_sdvo_connector->top_margin;
  1510. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1511. goto set_value;
  1512. }
  1513. CHECK_PROPERTY(hpos, HPOS)
  1514. CHECK_PROPERTY(vpos, VPOS)
  1515. CHECK_PROPERTY(saturation, SATURATION)
  1516. CHECK_PROPERTY(contrast, CONTRAST)
  1517. CHECK_PROPERTY(hue, HUE)
  1518. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1519. CHECK_PROPERTY(sharpness, SHARPNESS)
  1520. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1521. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1522. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1523. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1524. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1525. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1526. }
  1527. return -EINVAL; /* unknown property */
  1528. set_value:
  1529. if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
  1530. return -EIO;
  1531. done:
  1532. if (psb_intel_sdvo->base.base.crtc) {
  1533. struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
  1534. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1535. crtc->y, crtc->primary->fb);
  1536. }
  1537. return 0;
  1538. #undef CHECK_PROPERTY
  1539. }
  1540. static void psb_intel_sdvo_save(struct drm_connector *connector)
  1541. {
  1542. struct drm_device *dev = connector->dev;
  1543. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  1544. struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base);
  1545. sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);
  1546. }
  1547. static void psb_intel_sdvo_restore(struct drm_connector *connector)
  1548. {
  1549. struct drm_device *dev = connector->dev;
  1550. struct drm_encoder *encoder = &gma_attached_encoder(connector)->base;
  1551. struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder);
  1552. struct drm_crtc *crtc = encoder->crtc;
  1553. REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO);
  1554. /* Force a full mode set on the crtc. We're supposed to have the
  1555. mode_config lock already. */
  1556. if (connector->status == connector_status_connected)
  1557. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  1558. NULL);
  1559. }
  1560. static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
  1561. .dpms = psb_intel_sdvo_dpms,
  1562. .mode_fixup = psb_intel_sdvo_mode_fixup,
  1563. .prepare = gma_encoder_prepare,
  1564. .mode_set = psb_intel_sdvo_mode_set,
  1565. .commit = gma_encoder_commit,
  1566. };
  1567. static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
  1568. .dpms = drm_helper_connector_dpms,
  1569. .save = psb_intel_sdvo_save,
  1570. .restore = psb_intel_sdvo_restore,
  1571. .detect = psb_intel_sdvo_detect,
  1572. .fill_modes = drm_helper_probe_single_connector_modes,
  1573. .set_property = psb_intel_sdvo_set_property,
  1574. .destroy = psb_intel_sdvo_destroy,
  1575. };
  1576. static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
  1577. .get_modes = psb_intel_sdvo_get_modes,
  1578. .mode_valid = psb_intel_sdvo_mode_valid,
  1579. .best_encoder = gma_best_encoder,
  1580. };
  1581. static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1582. {
  1583. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  1584. if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1585. drm_mode_destroy(encoder->dev,
  1586. psb_intel_sdvo->sdvo_lvds_fixed_mode);
  1587. i2c_del_adapter(&psb_intel_sdvo->ddc);
  1588. gma_encoder_destroy(encoder);
  1589. }
  1590. static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
  1591. .destroy = psb_intel_sdvo_enc_destroy,
  1592. };
  1593. static void
  1594. psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
  1595. {
  1596. /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
  1597. * We need to figure out if this is true for all available poulsbo
  1598. * hardware, or if we need to fiddle with the guessing code above.
  1599. * The problem might go away if we can parse sdvo mappings from bios */
  1600. sdvo->ddc_bus = 2;
  1601. #if 0
  1602. uint16_t mask = 0;
  1603. unsigned int num_bits;
  1604. /* Make a mask of outputs less than or equal to our own priority in the
  1605. * list.
  1606. */
  1607. switch (sdvo->controlled_output) {
  1608. case SDVO_OUTPUT_LVDS1:
  1609. mask |= SDVO_OUTPUT_LVDS1;
  1610. case SDVO_OUTPUT_LVDS0:
  1611. mask |= SDVO_OUTPUT_LVDS0;
  1612. case SDVO_OUTPUT_TMDS1:
  1613. mask |= SDVO_OUTPUT_TMDS1;
  1614. case SDVO_OUTPUT_TMDS0:
  1615. mask |= SDVO_OUTPUT_TMDS0;
  1616. case SDVO_OUTPUT_RGB1:
  1617. mask |= SDVO_OUTPUT_RGB1;
  1618. case SDVO_OUTPUT_RGB0:
  1619. mask |= SDVO_OUTPUT_RGB0;
  1620. break;
  1621. }
  1622. /* Count bits to find what number we are in the priority list. */
  1623. mask &= sdvo->caps.output_flags;
  1624. num_bits = hweight16(mask);
  1625. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1626. if (num_bits > 3)
  1627. num_bits = 3;
  1628. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1629. sdvo->ddc_bus = 1 << num_bits;
  1630. #endif
  1631. }
  1632. /**
  1633. * Choose the appropriate DDC bus for control bus switch command for this
  1634. * SDVO output based on the controlled output.
  1635. *
  1636. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1637. * outputs, then LVDS outputs.
  1638. */
  1639. static void
  1640. psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
  1641. struct psb_intel_sdvo *sdvo, u32 reg)
  1642. {
  1643. struct sdvo_device_mapping *mapping;
  1644. if (IS_SDVOB(reg))
  1645. mapping = &(dev_priv->sdvo_mappings[0]);
  1646. else
  1647. mapping = &(dev_priv->sdvo_mappings[1]);
  1648. if (mapping->initialized)
  1649. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1650. else
  1651. psb_intel_sdvo_guess_ddc_bus(sdvo);
  1652. }
  1653. static void
  1654. psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
  1655. struct psb_intel_sdvo *sdvo, u32 reg)
  1656. {
  1657. struct sdvo_device_mapping *mapping;
  1658. u8 pin, speed;
  1659. if (IS_SDVOB(reg))
  1660. mapping = &dev_priv->sdvo_mappings[0];
  1661. else
  1662. mapping = &dev_priv->sdvo_mappings[1];
  1663. pin = GMBUS_PORT_DPB;
  1664. speed = GMBUS_RATE_1MHZ >> 8;
  1665. if (mapping->initialized) {
  1666. pin = mapping->i2c_pin;
  1667. speed = mapping->i2c_speed;
  1668. }
  1669. if (pin < GMBUS_NUM_PORTS) {
  1670. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1671. gma_intel_gmbus_set_speed(sdvo->i2c, speed);
  1672. gma_intel_gmbus_force_bit(sdvo->i2c, true);
  1673. } else
  1674. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1675. }
  1676. static bool
  1677. psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1678. {
  1679. return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
  1680. }
  1681. static u8
  1682. psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1683. {
  1684. struct drm_psb_private *dev_priv = dev->dev_private;
  1685. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1686. if (IS_SDVOB(sdvo_reg)) {
  1687. my_mapping = &dev_priv->sdvo_mappings[0];
  1688. other_mapping = &dev_priv->sdvo_mappings[1];
  1689. } else {
  1690. my_mapping = &dev_priv->sdvo_mappings[1];
  1691. other_mapping = &dev_priv->sdvo_mappings[0];
  1692. }
  1693. /* If the BIOS described our SDVO device, take advantage of it. */
  1694. if (my_mapping->slave_addr)
  1695. return my_mapping->slave_addr;
  1696. /* If the BIOS only described a different SDVO device, use the
  1697. * address that it isn't using.
  1698. */
  1699. if (other_mapping->slave_addr) {
  1700. if (other_mapping->slave_addr == 0x70)
  1701. return 0x72;
  1702. else
  1703. return 0x70;
  1704. }
  1705. /* No SDVO device info is found for another DVO port,
  1706. * so use mapping assumption we had before BIOS parsing.
  1707. */
  1708. if (IS_SDVOB(sdvo_reg))
  1709. return 0x70;
  1710. else
  1711. return 0x72;
  1712. }
  1713. static void
  1714. psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
  1715. struct psb_intel_sdvo *encoder)
  1716. {
  1717. drm_connector_init(encoder->base.base.dev,
  1718. &connector->base.base,
  1719. &psb_intel_sdvo_connector_funcs,
  1720. connector->base.base.connector_type);
  1721. drm_connector_helper_add(&connector->base.base,
  1722. &psb_intel_sdvo_connector_helper_funcs);
  1723. connector->base.base.interlace_allowed = 0;
  1724. connector->base.base.doublescan_allowed = 0;
  1725. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1726. gma_connector_attach_encoder(&connector->base, &encoder->base);
  1727. drm_connector_register(&connector->base.base);
  1728. }
  1729. static void
  1730. psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
  1731. {
  1732. /* FIXME: We don't support HDMI at the moment
  1733. struct drm_device *dev = connector->base.base.dev;
  1734. intel_attach_force_audio_property(&connector->base.base);
  1735. intel_attach_broadcast_rgb_property(&connector->base.base);
  1736. */
  1737. }
  1738. static bool
  1739. psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1740. {
  1741. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1742. struct drm_connector *connector;
  1743. struct gma_connector *intel_connector;
  1744. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1745. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1746. if (!psb_intel_sdvo_connector)
  1747. return false;
  1748. if (device == 0) {
  1749. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1750. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1751. } else if (device == 1) {
  1752. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1753. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1754. }
  1755. intel_connector = &psb_intel_sdvo_connector->base;
  1756. connector = &intel_connector->base;
  1757. // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1758. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1759. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1760. if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
  1761. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1762. psb_intel_sdvo->is_hdmi = true;
  1763. }
  1764. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1765. (1 << INTEL_ANALOG_CLONE_BIT));
  1766. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1767. if (psb_intel_sdvo->is_hdmi)
  1768. psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
  1769. return true;
  1770. }
  1771. static bool
  1772. psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
  1773. {
  1774. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1775. struct drm_connector *connector;
  1776. struct gma_connector *intel_connector;
  1777. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1778. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1779. if (!psb_intel_sdvo_connector)
  1780. return false;
  1781. intel_connector = &psb_intel_sdvo_connector->base;
  1782. connector = &intel_connector->base;
  1783. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1784. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1785. psb_intel_sdvo->controlled_output |= type;
  1786. psb_intel_sdvo_connector->output_flag = type;
  1787. psb_intel_sdvo->is_tv = true;
  1788. psb_intel_sdvo->base.needs_tv_clock = true;
  1789. psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1790. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1791. if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
  1792. goto err;
  1793. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1794. goto err;
  1795. return true;
  1796. err:
  1797. psb_intel_sdvo_destroy(connector);
  1798. return false;
  1799. }
  1800. static bool
  1801. psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1802. {
  1803. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1804. struct drm_connector *connector;
  1805. struct gma_connector *intel_connector;
  1806. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1807. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1808. if (!psb_intel_sdvo_connector)
  1809. return false;
  1810. intel_connector = &psb_intel_sdvo_connector->base;
  1811. connector = &intel_connector->base;
  1812. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1813. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1814. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1815. if (device == 0) {
  1816. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1817. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1818. } else if (device == 1) {
  1819. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1820. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1821. }
  1822. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1823. (1 << INTEL_ANALOG_CLONE_BIT));
  1824. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
  1825. psb_intel_sdvo);
  1826. return true;
  1827. }
  1828. static bool
  1829. psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1830. {
  1831. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1832. struct drm_connector *connector;
  1833. struct gma_connector *intel_connector;
  1834. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1835. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1836. if (!psb_intel_sdvo_connector)
  1837. return false;
  1838. intel_connector = &psb_intel_sdvo_connector->base;
  1839. connector = &intel_connector->base;
  1840. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1841. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1842. if (device == 0) {
  1843. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1844. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1845. } else if (device == 1) {
  1846. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1847. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1848. }
  1849. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1850. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1851. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1852. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1853. goto err;
  1854. return true;
  1855. err:
  1856. psb_intel_sdvo_destroy(connector);
  1857. return false;
  1858. }
  1859. static bool
  1860. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
  1861. {
  1862. psb_intel_sdvo->is_tv = false;
  1863. psb_intel_sdvo->base.needs_tv_clock = false;
  1864. psb_intel_sdvo->is_lvds = false;
  1865. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1866. if (flags & SDVO_OUTPUT_TMDS0)
  1867. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
  1868. return false;
  1869. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1870. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
  1871. return false;
  1872. /* TV has no XXX1 function block */
  1873. if (flags & SDVO_OUTPUT_SVID0)
  1874. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
  1875. return false;
  1876. if (flags & SDVO_OUTPUT_CVBS0)
  1877. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
  1878. return false;
  1879. if (flags & SDVO_OUTPUT_RGB0)
  1880. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
  1881. return false;
  1882. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1883. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
  1884. return false;
  1885. if (flags & SDVO_OUTPUT_LVDS0)
  1886. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
  1887. return false;
  1888. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1889. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
  1890. return false;
  1891. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1892. unsigned char bytes[2];
  1893. psb_intel_sdvo->controlled_output = 0;
  1894. memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
  1895. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1896. SDVO_NAME(psb_intel_sdvo),
  1897. bytes[0], bytes[1]);
  1898. return false;
  1899. }
  1900. psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1901. return true;
  1902. }
  1903. static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  1904. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1905. int type)
  1906. {
  1907. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1908. struct psb_intel_sdvo_tv_format format;
  1909. uint32_t format_map, i;
  1910. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
  1911. return false;
  1912. BUILD_BUG_ON(sizeof(format) != 6);
  1913. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1914. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1915. &format, sizeof(format)))
  1916. return false;
  1917. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1918. if (format_map == 0)
  1919. return false;
  1920. psb_intel_sdvo_connector->format_supported_num = 0;
  1921. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1922. if (format_map & (1 << i))
  1923. psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
  1924. psb_intel_sdvo_connector->tv_format =
  1925. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1926. "mode", psb_intel_sdvo_connector->format_supported_num);
  1927. if (!psb_intel_sdvo_connector->tv_format)
  1928. return false;
  1929. for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
  1930. drm_property_add_enum(
  1931. psb_intel_sdvo_connector->tv_format, i,
  1932. i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
  1933. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
  1934. drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base,
  1935. psb_intel_sdvo_connector->tv_format, 0);
  1936. return true;
  1937. }
  1938. #define ENHANCEMENT(name, NAME) do { \
  1939. if (enhancements.name) { \
  1940. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1941. !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1942. return false; \
  1943. psb_intel_sdvo_connector->max_##name = data_value[0]; \
  1944. psb_intel_sdvo_connector->cur_##name = response; \
  1945. psb_intel_sdvo_connector->name = \
  1946. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1947. if (!psb_intel_sdvo_connector->name) return false; \
  1948. drm_object_attach_property(&connector->base, \
  1949. psb_intel_sdvo_connector->name, \
  1950. psb_intel_sdvo_connector->cur_##name); \
  1951. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1952. data_value[0], data_value[1], response); \
  1953. } \
  1954. } while(0)
  1955. static bool
  1956. psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
  1957. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1958. struct psb_intel_sdvo_enhancements_reply enhancements)
  1959. {
  1960. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1961. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  1962. uint16_t response, data_value[2];
  1963. /* when horizontal overscan is supported, Add the left/right property */
  1964. if (enhancements.overscan_h) {
  1965. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1966. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1967. &data_value, 4))
  1968. return false;
  1969. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1970. SDVO_CMD_GET_OVERSCAN_H,
  1971. &response, 2))
  1972. return false;
  1973. psb_intel_sdvo_connector->max_hscan = data_value[0];
  1974. psb_intel_sdvo_connector->left_margin = data_value[0] - response;
  1975. psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
  1976. psb_intel_sdvo_connector->left =
  1977. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  1978. if (!psb_intel_sdvo_connector->left)
  1979. return false;
  1980. drm_object_attach_property(&connector->base,
  1981. psb_intel_sdvo_connector->left,
  1982. psb_intel_sdvo_connector->left_margin);
  1983. psb_intel_sdvo_connector->right =
  1984. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  1985. if (!psb_intel_sdvo_connector->right)
  1986. return false;
  1987. drm_object_attach_property(&connector->base,
  1988. psb_intel_sdvo_connector->right,
  1989. psb_intel_sdvo_connector->right_margin);
  1990. DRM_DEBUG_KMS("h_overscan: max %d, "
  1991. "default %d, current %d\n",
  1992. data_value[0], data_value[1], response);
  1993. }
  1994. if (enhancements.overscan_v) {
  1995. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1996. SDVO_CMD_GET_MAX_OVERSCAN_V,
  1997. &data_value, 4))
  1998. return false;
  1999. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2000. SDVO_CMD_GET_OVERSCAN_V,
  2001. &response, 2))
  2002. return false;
  2003. psb_intel_sdvo_connector->max_vscan = data_value[0];
  2004. psb_intel_sdvo_connector->top_margin = data_value[0] - response;
  2005. psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
  2006. psb_intel_sdvo_connector->top =
  2007. drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
  2008. if (!psb_intel_sdvo_connector->top)
  2009. return false;
  2010. drm_object_attach_property(&connector->base,
  2011. psb_intel_sdvo_connector->top,
  2012. psb_intel_sdvo_connector->top_margin);
  2013. psb_intel_sdvo_connector->bottom =
  2014. drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
  2015. if (!psb_intel_sdvo_connector->bottom)
  2016. return false;
  2017. drm_object_attach_property(&connector->base,
  2018. psb_intel_sdvo_connector->bottom,
  2019. psb_intel_sdvo_connector->bottom_margin);
  2020. DRM_DEBUG_KMS("v_overscan: max %d, "
  2021. "default %d, current %d\n",
  2022. data_value[0], data_value[1], response);
  2023. }
  2024. ENHANCEMENT(hpos, HPOS);
  2025. ENHANCEMENT(vpos, VPOS);
  2026. ENHANCEMENT(saturation, SATURATION);
  2027. ENHANCEMENT(contrast, CONTRAST);
  2028. ENHANCEMENT(hue, HUE);
  2029. ENHANCEMENT(sharpness, SHARPNESS);
  2030. ENHANCEMENT(brightness, BRIGHTNESS);
  2031. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2032. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2033. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2034. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2035. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2036. if (enhancements.dot_crawl) {
  2037. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2038. return false;
  2039. psb_intel_sdvo_connector->max_dot_crawl = 1;
  2040. psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2041. psb_intel_sdvo_connector->dot_crawl =
  2042. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2043. if (!psb_intel_sdvo_connector->dot_crawl)
  2044. return false;
  2045. drm_object_attach_property(&connector->base,
  2046. psb_intel_sdvo_connector->dot_crawl,
  2047. psb_intel_sdvo_connector->cur_dot_crawl);
  2048. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2049. }
  2050. return true;
  2051. }
  2052. static bool
  2053. psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
  2054. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  2055. struct psb_intel_sdvo_enhancements_reply enhancements)
  2056. {
  2057. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  2058. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  2059. uint16_t response, data_value[2];
  2060. ENHANCEMENT(brightness, BRIGHTNESS);
  2061. return true;
  2062. }
  2063. #undef ENHANCEMENT
  2064. static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  2065. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
  2066. {
  2067. union {
  2068. struct psb_intel_sdvo_enhancements_reply reply;
  2069. uint16_t response;
  2070. } enhancements;
  2071. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2072. enhancements.response = 0;
  2073. psb_intel_sdvo_get_value(psb_intel_sdvo,
  2074. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2075. &enhancements, sizeof(enhancements));
  2076. if (enhancements.response == 0) {
  2077. DRM_DEBUG_KMS("No enhancement is supported\n");
  2078. return true;
  2079. }
  2080. if (IS_TV(psb_intel_sdvo_connector))
  2081. return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2082. else if(IS_LVDS(psb_intel_sdvo_connector))
  2083. return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2084. else
  2085. return true;
  2086. }
  2087. static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2088. struct i2c_msg *msgs,
  2089. int num)
  2090. {
  2091. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2092. if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2093. return -EIO;
  2094. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2095. }
  2096. static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2097. {
  2098. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2099. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2100. }
  2101. static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
  2102. .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
  2103. .functionality = psb_intel_sdvo_ddc_proxy_func
  2104. };
  2105. static bool
  2106. psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
  2107. struct drm_device *dev)
  2108. {
  2109. sdvo->ddc.owner = THIS_MODULE;
  2110. sdvo->ddc.class = I2C_CLASS_DDC;
  2111. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2112. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2113. sdvo->ddc.algo_data = sdvo;
  2114. sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
  2115. return i2c_add_adapter(&sdvo->ddc) == 0;
  2116. }
  2117. bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2118. {
  2119. struct drm_psb_private *dev_priv = dev->dev_private;
  2120. struct gma_encoder *gma_encoder;
  2121. struct psb_intel_sdvo *psb_intel_sdvo;
  2122. int i;
  2123. psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
  2124. if (!psb_intel_sdvo)
  2125. return false;
  2126. psb_intel_sdvo->sdvo_reg = sdvo_reg;
  2127. psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2128. psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2129. if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
  2130. kfree(psb_intel_sdvo);
  2131. return false;
  2132. }
  2133. /* encoder type will be decided later */
  2134. gma_encoder = &psb_intel_sdvo->base;
  2135. gma_encoder->type = INTEL_OUTPUT_SDVO;
  2136. drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
  2137. /* Read the regs to test if we can talk to the device */
  2138. for (i = 0; i < 0x40; i++) {
  2139. u8 byte;
  2140. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
  2141. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2142. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2143. goto err;
  2144. }
  2145. }
  2146. if (IS_SDVOB(sdvo_reg))
  2147. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2148. else
  2149. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2150. drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs);
  2151. /* In default case sdvo lvds is false */
  2152. if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
  2153. goto err;
  2154. if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
  2155. psb_intel_sdvo->caps.output_flags) != true) {
  2156. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2157. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2158. goto err;
  2159. }
  2160. psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2161. /* Set the input timing to the screen. Assume always input 0. */
  2162. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  2163. goto err;
  2164. if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
  2165. &psb_intel_sdvo->pixel_clock_min,
  2166. &psb_intel_sdvo->pixel_clock_max))
  2167. goto err;
  2168. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2169. "clock range %dMHz - %dMHz, "
  2170. "input 1: %c, input 2: %c, "
  2171. "output 1: %c, output 2: %c\n",
  2172. SDVO_NAME(psb_intel_sdvo),
  2173. psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
  2174. psb_intel_sdvo->caps.device_rev_id,
  2175. psb_intel_sdvo->pixel_clock_min / 1000,
  2176. psb_intel_sdvo->pixel_clock_max / 1000,
  2177. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2178. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2179. /* check currently supported outputs */
  2180. psb_intel_sdvo->caps.output_flags &
  2181. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2182. psb_intel_sdvo->caps.output_flags &
  2183. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2184. return true;
  2185. err:
  2186. drm_encoder_cleanup(&gma_encoder->base);
  2187. i2c_del_adapter(&psb_intel_sdvo->ddc);
  2188. kfree(psb_intel_sdvo);
  2189. return false;
  2190. }