tda998x_drv.c 47 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include <linux/component.h>
  18. #include <linux/hdmi.h>
  19. #include <linux/module.h>
  20. #include <linux/irq.h>
  21. #include <sound/asoundef.h>
  22. #include <drm/drmP.h>
  23. #include <drm/drm_crtc_helper.h>
  24. #include <drm/drm_edid.h>
  25. #include <drm/drm_of.h>
  26. #include <drm/i2c/tda998x.h>
  27. #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  28. struct tda998x_priv {
  29. struct i2c_client *cec;
  30. struct i2c_client *hdmi;
  31. struct mutex mutex;
  32. u16 rev;
  33. u8 current_page;
  34. int dpms;
  35. bool is_hdmi_sink;
  36. u8 vip_cntrl_0;
  37. u8 vip_cntrl_1;
  38. u8 vip_cntrl_2;
  39. struct tda998x_encoder_params params;
  40. wait_queue_head_t wq_edid;
  41. volatile int wq_edid_wait;
  42. struct work_struct detect_work;
  43. struct timer_list edid_delay_timer;
  44. wait_queue_head_t edid_delay_waitq;
  45. bool edid_delay_active;
  46. struct drm_encoder encoder;
  47. struct drm_connector connector;
  48. };
  49. #define conn_to_tda998x_priv(x) \
  50. container_of(x, struct tda998x_priv, connector)
  51. #define enc_to_tda998x_priv(x) \
  52. container_of(x, struct tda998x_priv, encoder)
  53. /* The TDA9988 series of devices use a paged register scheme.. to simplify
  54. * things we encode the page # in upper bits of the register #. To read/
  55. * write a given register, we need to make sure CURPAGE register is set
  56. * appropriately. Which implies reads/writes are not atomic. Fun!
  57. */
  58. #define REG(page, addr) (((page) << 8) | (addr))
  59. #define REG2ADDR(reg) ((reg) & 0xff)
  60. #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
  61. #define REG_CURPAGE 0xff /* write */
  62. /* Page 00h: General Control */
  63. #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
  64. #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
  65. # define MAIN_CNTRL0_SR (1 << 0)
  66. # define MAIN_CNTRL0_DECS (1 << 1)
  67. # define MAIN_CNTRL0_DEHS (1 << 2)
  68. # define MAIN_CNTRL0_CECS (1 << 3)
  69. # define MAIN_CNTRL0_CEHS (1 << 4)
  70. # define MAIN_CNTRL0_SCALER (1 << 7)
  71. #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
  72. #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
  73. # define SOFTRESET_AUDIO (1 << 0)
  74. # define SOFTRESET_I2C_MASTER (1 << 1)
  75. #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
  76. #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
  77. #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
  78. # define I2C_MASTER_DIS_MM (1 << 0)
  79. # define I2C_MASTER_DIS_FILT (1 << 1)
  80. # define I2C_MASTER_APP_STRT_LAT (1 << 2)
  81. #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
  82. # define FEAT_POWERDOWN_SPDIF (1 << 3)
  83. #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
  84. #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
  85. #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
  86. # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
  87. #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
  88. #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
  89. #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
  90. #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
  91. #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
  92. #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
  93. # define VIP_CNTRL_0_MIRR_A (1 << 7)
  94. # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
  95. # define VIP_CNTRL_0_MIRR_B (1 << 3)
  96. # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
  97. #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
  98. # define VIP_CNTRL_1_MIRR_C (1 << 7)
  99. # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
  100. # define VIP_CNTRL_1_MIRR_D (1 << 3)
  101. # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
  102. #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
  103. # define VIP_CNTRL_2_MIRR_E (1 << 7)
  104. # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
  105. # define VIP_CNTRL_2_MIRR_F (1 << 3)
  106. # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
  107. #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
  108. # define VIP_CNTRL_3_X_TGL (1 << 0)
  109. # define VIP_CNTRL_3_H_TGL (1 << 1)
  110. # define VIP_CNTRL_3_V_TGL (1 << 2)
  111. # define VIP_CNTRL_3_EMB (1 << 3)
  112. # define VIP_CNTRL_3_SYNC_DE (1 << 4)
  113. # define VIP_CNTRL_3_SYNC_HS (1 << 5)
  114. # define VIP_CNTRL_3_DE_INT (1 << 6)
  115. # define VIP_CNTRL_3_EDGE (1 << 7)
  116. #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
  117. # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
  118. # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
  119. # define VIP_CNTRL_4_CCIR656 (1 << 4)
  120. # define VIP_CNTRL_4_656_ALT (1 << 5)
  121. # define VIP_CNTRL_4_TST_656 (1 << 6)
  122. # define VIP_CNTRL_4_TST_PAT (1 << 7)
  123. #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
  124. # define VIP_CNTRL_5_CKCASE (1 << 0)
  125. # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
  126. #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
  127. # define MUX_AP_SELECT_I2S 0x64
  128. # define MUX_AP_SELECT_SPDIF 0x40
  129. #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
  130. #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
  131. # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
  132. # define MAT_CONTRL_MAT_BP (1 << 2)
  133. #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
  134. #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
  135. #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
  136. #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
  137. #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
  138. #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
  139. #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
  140. #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
  141. #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
  142. #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
  143. #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
  144. #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
  145. #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
  146. #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
  147. #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
  148. #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
  149. #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
  150. #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
  151. #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
  152. #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
  153. #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
  154. #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
  155. #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
  156. #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
  157. #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
  158. #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
  159. #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
  160. #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
  161. #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
  162. #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
  163. #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
  164. #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
  165. #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
  166. #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
  167. #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
  168. #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
  169. #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
  170. #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
  171. #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
  172. #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
  173. #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
  174. #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
  175. # define TBG_CNTRL_0_TOP_TGL (1 << 0)
  176. # define TBG_CNTRL_0_TOP_SEL (1 << 1)
  177. # define TBG_CNTRL_0_DE_EXT (1 << 2)
  178. # define TBG_CNTRL_0_TOP_EXT (1 << 3)
  179. # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
  180. # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
  181. # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
  182. #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
  183. # define TBG_CNTRL_1_H_TGL (1 << 0)
  184. # define TBG_CNTRL_1_V_TGL (1 << 1)
  185. # define TBG_CNTRL_1_TGL_EN (1 << 2)
  186. # define TBG_CNTRL_1_X_EXT (1 << 3)
  187. # define TBG_CNTRL_1_H_EXT (1 << 4)
  188. # define TBG_CNTRL_1_V_EXT (1 << 5)
  189. # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
  190. #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
  191. #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
  192. # define HVF_CNTRL_0_SM (1 << 7)
  193. # define HVF_CNTRL_0_RWB (1 << 6)
  194. # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
  195. # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
  196. #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
  197. # define HVF_CNTRL_1_FOR (1 << 0)
  198. # define HVF_CNTRL_1_YUVBLK (1 << 1)
  199. # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
  200. # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
  201. # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
  202. #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
  203. #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
  204. # define I2S_FORMAT(x) (((x) & 3) << 0)
  205. #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
  206. # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
  207. # define AIP_CLKSEL_AIP_I2S (1 << 3)
  208. # define AIP_CLKSEL_FS_ACLK (0 << 0)
  209. # define AIP_CLKSEL_FS_MCLK (1 << 0)
  210. # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
  211. /* Page 02h: PLL settings */
  212. #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
  213. # define PLL_SERIAL_1_SRL_FDN (1 << 0)
  214. # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
  215. # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
  216. #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
  217. # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
  218. # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
  219. #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
  220. # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
  221. # define PLL_SERIAL_3_SRL_DE (1 << 2)
  222. # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
  223. #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
  224. #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
  225. #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
  226. #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
  227. #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
  228. #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
  229. #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
  230. #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
  231. #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
  232. # define AUDIO_DIV_SERCLK_1 0
  233. # define AUDIO_DIV_SERCLK_2 1
  234. # define AUDIO_DIV_SERCLK_4 2
  235. # define AUDIO_DIV_SERCLK_8 3
  236. # define AUDIO_DIV_SERCLK_16 4
  237. # define AUDIO_DIV_SERCLK_32 5
  238. #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
  239. # define SEL_CLK_SEL_CLK1 (1 << 0)
  240. # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
  241. # define SEL_CLK_ENA_SC_CLK (1 << 3)
  242. #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
  243. /* Page 09h: EDID Control */
  244. #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
  245. /* next 127 successive registers are the EDID block */
  246. #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
  247. #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
  248. #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
  249. #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
  250. #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
  251. /* Page 10h: information frames and packets */
  252. #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
  253. #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
  254. #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
  255. #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
  256. #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
  257. /* Page 11h: audio settings and content info packets */
  258. #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
  259. # define AIP_CNTRL_0_RST_FIFO (1 << 0)
  260. # define AIP_CNTRL_0_SWAP (1 << 1)
  261. # define AIP_CNTRL_0_LAYOUT (1 << 2)
  262. # define AIP_CNTRL_0_ACR_MAN (1 << 5)
  263. # define AIP_CNTRL_0_RST_CTS (1 << 6)
  264. #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
  265. # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
  266. # define CA_I2S_HBR_CHSTAT (1 << 6)
  267. #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
  268. #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
  269. #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
  270. #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
  271. #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
  272. #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
  273. #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
  274. #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
  275. # define CTS_N_K(x) (((x) & 7) << 0)
  276. # define CTS_N_M(x) (((x) & 3) << 4)
  277. #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
  278. # define ENC_CNTRL_RST_ENC (1 << 0)
  279. # define ENC_CNTRL_RST_SEL (1 << 1)
  280. # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
  281. #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
  282. # define DIP_FLAGS_ACR (1 << 0)
  283. # define DIP_FLAGS_GC (1 << 1)
  284. #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
  285. # define DIP_IF_FLAGS_IF1 (1 << 1)
  286. # define DIP_IF_FLAGS_IF2 (1 << 2)
  287. # define DIP_IF_FLAGS_IF3 (1 << 3)
  288. # define DIP_IF_FLAGS_IF4 (1 << 4)
  289. # define DIP_IF_FLAGS_IF5 (1 << 5)
  290. #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
  291. /* Page 12h: HDCP and OTP */
  292. #define REG_TX3 REG(0x12, 0x9a) /* read/write */
  293. #define REG_TX4 REG(0x12, 0x9b) /* read/write */
  294. # define TX4_PD_RAM (1 << 1)
  295. #define REG_TX33 REG(0x12, 0xb8) /* read/write */
  296. # define TX33_HDMI (1 << 1)
  297. /* Page 13h: Gamut related metadata packets */
  298. /* CEC registers: (not paged)
  299. */
  300. #define REG_CEC_INTSTATUS 0xee /* read */
  301. # define CEC_INTSTATUS_CEC (1 << 0)
  302. # define CEC_INTSTATUS_HDMI (1 << 1)
  303. #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
  304. # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
  305. # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
  306. # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
  307. # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
  308. #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
  309. #define REG_CEC_RXSHPDINT 0xfd /* read */
  310. # define CEC_RXSHPDINT_RXSENS BIT(0)
  311. # define CEC_RXSHPDINT_HPD BIT(1)
  312. #define REG_CEC_RXSHPDLEV 0xfe /* read */
  313. # define CEC_RXSHPDLEV_RXSENS (1 << 0)
  314. # define CEC_RXSHPDLEV_HPD (1 << 1)
  315. #define REG_CEC_ENAMODS 0xff /* read/write */
  316. # define CEC_ENAMODS_DIS_FRO (1 << 6)
  317. # define CEC_ENAMODS_DIS_CCLK (1 << 5)
  318. # define CEC_ENAMODS_EN_RXSENS (1 << 2)
  319. # define CEC_ENAMODS_EN_HDMI (1 << 1)
  320. # define CEC_ENAMODS_EN_CEC (1 << 0)
  321. /* Device versions: */
  322. #define TDA9989N2 0x0101
  323. #define TDA19989 0x0201
  324. #define TDA19989N2 0x0202
  325. #define TDA19988 0x0301
  326. static void
  327. cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
  328. {
  329. struct i2c_client *client = priv->cec;
  330. u8 buf[] = {addr, val};
  331. int ret;
  332. ret = i2c_master_send(client, buf, sizeof(buf));
  333. if (ret < 0)
  334. dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
  335. }
  336. static u8
  337. cec_read(struct tda998x_priv *priv, u8 addr)
  338. {
  339. struct i2c_client *client = priv->cec;
  340. u8 val;
  341. int ret;
  342. ret = i2c_master_send(client, &addr, sizeof(addr));
  343. if (ret < 0)
  344. goto fail;
  345. ret = i2c_master_recv(client, &val, sizeof(val));
  346. if (ret < 0)
  347. goto fail;
  348. return val;
  349. fail:
  350. dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
  351. return 0;
  352. }
  353. static int
  354. set_page(struct tda998x_priv *priv, u16 reg)
  355. {
  356. if (REG2PAGE(reg) != priv->current_page) {
  357. struct i2c_client *client = priv->hdmi;
  358. u8 buf[] = {
  359. REG_CURPAGE, REG2PAGE(reg)
  360. };
  361. int ret = i2c_master_send(client, buf, sizeof(buf));
  362. if (ret < 0) {
  363. dev_err(&client->dev, "%s %04x err %d\n", __func__,
  364. reg, ret);
  365. return ret;
  366. }
  367. priv->current_page = REG2PAGE(reg);
  368. }
  369. return 0;
  370. }
  371. static int
  372. reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
  373. {
  374. struct i2c_client *client = priv->hdmi;
  375. u8 addr = REG2ADDR(reg);
  376. int ret;
  377. mutex_lock(&priv->mutex);
  378. ret = set_page(priv, reg);
  379. if (ret < 0)
  380. goto out;
  381. ret = i2c_master_send(client, &addr, sizeof(addr));
  382. if (ret < 0)
  383. goto fail;
  384. ret = i2c_master_recv(client, buf, cnt);
  385. if (ret < 0)
  386. goto fail;
  387. goto out;
  388. fail:
  389. dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
  390. out:
  391. mutex_unlock(&priv->mutex);
  392. return ret;
  393. }
  394. static void
  395. reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
  396. {
  397. struct i2c_client *client = priv->hdmi;
  398. u8 buf[cnt+1];
  399. int ret;
  400. buf[0] = REG2ADDR(reg);
  401. memcpy(&buf[1], p, cnt);
  402. mutex_lock(&priv->mutex);
  403. ret = set_page(priv, reg);
  404. if (ret < 0)
  405. goto out;
  406. ret = i2c_master_send(client, buf, cnt + 1);
  407. if (ret < 0)
  408. dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
  409. out:
  410. mutex_unlock(&priv->mutex);
  411. }
  412. static int
  413. reg_read(struct tda998x_priv *priv, u16 reg)
  414. {
  415. u8 val = 0;
  416. int ret;
  417. ret = reg_read_range(priv, reg, &val, sizeof(val));
  418. if (ret < 0)
  419. return ret;
  420. return val;
  421. }
  422. static void
  423. reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
  424. {
  425. struct i2c_client *client = priv->hdmi;
  426. u8 buf[] = {REG2ADDR(reg), val};
  427. int ret;
  428. mutex_lock(&priv->mutex);
  429. ret = set_page(priv, reg);
  430. if (ret < 0)
  431. goto out;
  432. ret = i2c_master_send(client, buf, sizeof(buf));
  433. if (ret < 0)
  434. dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
  435. out:
  436. mutex_unlock(&priv->mutex);
  437. }
  438. static void
  439. reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
  440. {
  441. struct i2c_client *client = priv->hdmi;
  442. u8 buf[] = {REG2ADDR(reg), val >> 8, val};
  443. int ret;
  444. mutex_lock(&priv->mutex);
  445. ret = set_page(priv, reg);
  446. if (ret < 0)
  447. goto out;
  448. ret = i2c_master_send(client, buf, sizeof(buf));
  449. if (ret < 0)
  450. dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
  451. out:
  452. mutex_unlock(&priv->mutex);
  453. }
  454. static void
  455. reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
  456. {
  457. int old_val;
  458. old_val = reg_read(priv, reg);
  459. if (old_val >= 0)
  460. reg_write(priv, reg, old_val | val);
  461. }
  462. static void
  463. reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
  464. {
  465. int old_val;
  466. old_val = reg_read(priv, reg);
  467. if (old_val >= 0)
  468. reg_write(priv, reg, old_val & ~val);
  469. }
  470. static void
  471. tda998x_reset(struct tda998x_priv *priv)
  472. {
  473. /* reset audio and i2c master: */
  474. reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
  475. msleep(50);
  476. reg_write(priv, REG_SOFTRESET, 0);
  477. msleep(50);
  478. /* reset transmitter: */
  479. reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  480. reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
  481. /* PLL registers common configuration */
  482. reg_write(priv, REG_PLL_SERIAL_1, 0x00);
  483. reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
  484. reg_write(priv, REG_PLL_SERIAL_3, 0x00);
  485. reg_write(priv, REG_SERIALIZER, 0x00);
  486. reg_write(priv, REG_BUFFER_OUT, 0x00);
  487. reg_write(priv, REG_PLL_SCG1, 0x00);
  488. reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
  489. reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  490. reg_write(priv, REG_PLL_SCGN1, 0xfa);
  491. reg_write(priv, REG_PLL_SCGN2, 0x00);
  492. reg_write(priv, REG_PLL_SCGR1, 0x5b);
  493. reg_write(priv, REG_PLL_SCGR2, 0x00);
  494. reg_write(priv, REG_PLL_SCG2, 0x10);
  495. /* Write the default value MUX register */
  496. reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
  497. }
  498. /*
  499. * The TDA998x has a problem when trying to read the EDID close to a
  500. * HPD assertion: it needs a delay of 100ms to avoid timing out while
  501. * trying to read EDID data.
  502. *
  503. * However, tda998x_encoder_get_modes() may be called at any moment
  504. * after tda998x_connector_detect() indicates that we are connected, so
  505. * we need to delay probing modes in tda998x_encoder_get_modes() after
  506. * we have seen a HPD inactive->active transition. This code implements
  507. * that delay.
  508. */
  509. static void tda998x_edid_delay_done(unsigned long data)
  510. {
  511. struct tda998x_priv *priv = (struct tda998x_priv *)data;
  512. priv->edid_delay_active = false;
  513. wake_up(&priv->edid_delay_waitq);
  514. schedule_work(&priv->detect_work);
  515. }
  516. static void tda998x_edid_delay_start(struct tda998x_priv *priv)
  517. {
  518. priv->edid_delay_active = true;
  519. mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
  520. }
  521. static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
  522. {
  523. return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
  524. }
  525. /*
  526. * We need to run the KMS hotplug event helper outside of our threaded
  527. * interrupt routine as this can call back into our get_modes method,
  528. * which will want to make use of interrupts.
  529. */
  530. static void tda998x_detect_work(struct work_struct *work)
  531. {
  532. struct tda998x_priv *priv =
  533. container_of(work, struct tda998x_priv, detect_work);
  534. struct drm_device *dev = priv->encoder.dev;
  535. if (dev)
  536. drm_kms_helper_hotplug_event(dev);
  537. }
  538. /*
  539. * only 2 interrupts may occur: screen plug/unplug and EDID read
  540. */
  541. static irqreturn_t tda998x_irq_thread(int irq, void *data)
  542. {
  543. struct tda998x_priv *priv = data;
  544. u8 sta, cec, lvl, flag0, flag1, flag2;
  545. bool handled = false;
  546. sta = cec_read(priv, REG_CEC_INTSTATUS);
  547. cec = cec_read(priv, REG_CEC_RXSHPDINT);
  548. lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
  549. flag0 = reg_read(priv, REG_INT_FLAGS_0);
  550. flag1 = reg_read(priv, REG_INT_FLAGS_1);
  551. flag2 = reg_read(priv, REG_INT_FLAGS_2);
  552. DRM_DEBUG_DRIVER(
  553. "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
  554. sta, cec, lvl, flag0, flag1, flag2);
  555. if (cec & CEC_RXSHPDINT_HPD) {
  556. if (lvl & CEC_RXSHPDLEV_HPD)
  557. tda998x_edid_delay_start(priv);
  558. else
  559. schedule_work(&priv->detect_work);
  560. handled = true;
  561. }
  562. if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
  563. priv->wq_edid_wait = 0;
  564. wake_up(&priv->wq_edid);
  565. handled = true;
  566. }
  567. return IRQ_RETVAL(handled);
  568. }
  569. static void
  570. tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
  571. union hdmi_infoframe *frame)
  572. {
  573. u8 buf[32];
  574. ssize_t len;
  575. len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
  576. if (len < 0) {
  577. dev_err(&priv->hdmi->dev,
  578. "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
  579. frame->any.type, len);
  580. return;
  581. }
  582. reg_clear(priv, REG_DIP_IF_FLAGS, bit);
  583. reg_write_range(priv, addr, buf, len);
  584. reg_set(priv, REG_DIP_IF_FLAGS, bit);
  585. }
  586. static void
  587. tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
  588. {
  589. union hdmi_infoframe frame;
  590. hdmi_audio_infoframe_init(&frame.audio);
  591. frame.audio.channels = p->audio_frame[1] & 0x07;
  592. frame.audio.channel_allocation = p->audio_frame[4];
  593. frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
  594. frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
  595. /*
  596. * L-PCM and IEC61937 compressed audio shall always set sample
  597. * frequency to "refer to stream". For others, see the HDMI
  598. * specification.
  599. */
  600. frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
  601. tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
  602. }
  603. static void
  604. tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
  605. {
  606. union hdmi_infoframe frame;
  607. drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
  608. frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
  609. tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
  610. }
  611. static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
  612. {
  613. if (on) {
  614. reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
  615. reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
  616. reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
  617. } else {
  618. reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
  619. }
  620. }
  621. static void
  622. tda998x_configure_audio(struct tda998x_priv *priv,
  623. struct drm_display_mode *mode, struct tda998x_encoder_params *p)
  624. {
  625. u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
  626. u32 n;
  627. /* Enable audio ports */
  628. reg_write(priv, REG_ENA_AP, p->audio_cfg);
  629. reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
  630. /* Set audio input source */
  631. switch (p->audio_format) {
  632. case AFMT_SPDIF:
  633. reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
  634. clksel_aip = AIP_CLKSEL_AIP_SPDIF;
  635. clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
  636. cts_n = CTS_N_M(3) | CTS_N_K(3);
  637. break;
  638. case AFMT_I2S:
  639. reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
  640. clksel_aip = AIP_CLKSEL_AIP_I2S;
  641. clksel_fs = AIP_CLKSEL_FS_ACLK;
  642. cts_n = CTS_N_M(3) | CTS_N_K(3);
  643. break;
  644. default:
  645. BUG();
  646. return;
  647. }
  648. reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
  649. reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
  650. AIP_CNTRL_0_ACR_MAN); /* auto CTS */
  651. reg_write(priv, REG_CTS_N, cts_n);
  652. /*
  653. * Audio input somehow depends on HDMI line rate which is
  654. * related to pixclk. Testing showed that modes with pixclk
  655. * >100MHz need a larger divider while <40MHz need the default.
  656. * There is no detailed info in the datasheet, so we just
  657. * assume 100MHz requires larger divider.
  658. */
  659. adiv = AUDIO_DIV_SERCLK_8;
  660. if (mode->clock > 100000)
  661. adiv++; /* AUDIO_DIV_SERCLK_16 */
  662. /* S/PDIF asks for a larger divider */
  663. if (p->audio_format == AFMT_SPDIF)
  664. adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
  665. reg_write(priv, REG_AUDIO_DIV, adiv);
  666. /*
  667. * This is the approximate value of N, which happens to be
  668. * the recommended values for non-coherent clocks.
  669. */
  670. n = 128 * p->audio_sample_rate / 1000;
  671. /* Write the CTS and N values */
  672. buf[0] = 0x44;
  673. buf[1] = 0x42;
  674. buf[2] = 0x01;
  675. buf[3] = n;
  676. buf[4] = n >> 8;
  677. buf[5] = n >> 16;
  678. reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
  679. /* Set CTS clock reference */
  680. reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
  681. /* Reset CTS generator */
  682. reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
  683. reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
  684. /* Write the channel status */
  685. buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
  686. buf[1] = 0x00;
  687. buf[2] = IEC958_AES3_CON_FS_NOTID;
  688. buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
  689. IEC958_AES4_CON_MAX_WORDLEN_24;
  690. reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
  691. tda998x_audio_mute(priv, true);
  692. msleep(20);
  693. tda998x_audio_mute(priv, false);
  694. /* Write the audio information packet */
  695. tda998x_write_aif(priv, p);
  696. }
  697. /* DRM encoder functions */
  698. static void tda998x_encoder_set_config(struct tda998x_priv *priv,
  699. const struct tda998x_encoder_params *p)
  700. {
  701. priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
  702. (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
  703. VIP_CNTRL_0_SWAP_B(p->swap_b) |
  704. (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
  705. priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
  706. (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
  707. VIP_CNTRL_1_SWAP_D(p->swap_d) |
  708. (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
  709. priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
  710. (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
  711. VIP_CNTRL_2_SWAP_F(p->swap_f) |
  712. (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
  713. priv->params = *p;
  714. }
  715. static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
  716. {
  717. struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
  718. /* we only care about on or off: */
  719. if (mode != DRM_MODE_DPMS_ON)
  720. mode = DRM_MODE_DPMS_OFF;
  721. if (mode == priv->dpms)
  722. return;
  723. switch (mode) {
  724. case DRM_MODE_DPMS_ON:
  725. /* enable video ports, audio will be enabled later */
  726. reg_write(priv, REG_ENA_VP_0, 0xff);
  727. reg_write(priv, REG_ENA_VP_1, 0xff);
  728. reg_write(priv, REG_ENA_VP_2, 0xff);
  729. /* set muxing after enabling ports: */
  730. reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
  731. reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
  732. reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
  733. break;
  734. case DRM_MODE_DPMS_OFF:
  735. /* disable video ports */
  736. reg_write(priv, REG_ENA_VP_0, 0x00);
  737. reg_write(priv, REG_ENA_VP_1, 0x00);
  738. reg_write(priv, REG_ENA_VP_2, 0x00);
  739. break;
  740. }
  741. priv->dpms = mode;
  742. }
  743. static void
  744. tda998x_encoder_save(struct drm_encoder *encoder)
  745. {
  746. DBG("");
  747. }
  748. static void
  749. tda998x_encoder_restore(struct drm_encoder *encoder)
  750. {
  751. DBG("");
  752. }
  753. static bool
  754. tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
  755. const struct drm_display_mode *mode,
  756. struct drm_display_mode *adjusted_mode)
  757. {
  758. return true;
  759. }
  760. static int tda998x_connector_mode_valid(struct drm_connector *connector,
  761. struct drm_display_mode *mode)
  762. {
  763. if (mode->clock > 150000)
  764. return MODE_CLOCK_HIGH;
  765. if (mode->htotal >= BIT(13))
  766. return MODE_BAD_HVALUE;
  767. if (mode->vtotal >= BIT(11))
  768. return MODE_BAD_VVALUE;
  769. return MODE_OK;
  770. }
  771. static void
  772. tda998x_encoder_mode_set(struct drm_encoder *encoder,
  773. struct drm_display_mode *mode,
  774. struct drm_display_mode *adjusted_mode)
  775. {
  776. struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
  777. u16 ref_pix, ref_line, n_pix, n_line;
  778. u16 hs_pix_s, hs_pix_e;
  779. u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
  780. u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
  781. u16 vwin1_line_s, vwin1_line_e;
  782. u16 vwin2_line_s, vwin2_line_e;
  783. u16 de_pix_s, de_pix_e;
  784. u8 reg, div, rep;
  785. /*
  786. * Internally TDA998x is using ITU-R BT.656 style sync but
  787. * we get VESA style sync. TDA998x is using a reference pixel
  788. * relative to ITU to sync to the input frame and for output
  789. * sync generation. Currently, we are using reference detection
  790. * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
  791. * which is position of rising VS with coincident rising HS.
  792. *
  793. * Now there is some issues to take care of:
  794. * - HDMI data islands require sync-before-active
  795. * - TDA998x register values must be > 0 to be enabled
  796. * - REFLINE needs an additional offset of +1
  797. * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
  798. *
  799. * So we add +1 to all horizontal and vertical register values,
  800. * plus an additional +3 for REFPIX as we are using RGB input only.
  801. */
  802. n_pix = mode->htotal;
  803. n_line = mode->vtotal;
  804. hs_pix_e = mode->hsync_end - mode->hdisplay;
  805. hs_pix_s = mode->hsync_start - mode->hdisplay;
  806. de_pix_e = mode->htotal;
  807. de_pix_s = mode->htotal - mode->hdisplay;
  808. ref_pix = 3 + hs_pix_s;
  809. /*
  810. * Attached LCD controllers may generate broken sync. Allow
  811. * those to adjust the position of the rising VS edge by adding
  812. * HSKEW to ref_pix.
  813. */
  814. if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
  815. ref_pix += adjusted_mode->hskew;
  816. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
  817. ref_line = 1 + mode->vsync_start - mode->vdisplay;
  818. vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
  819. vwin1_line_e = vwin1_line_s + mode->vdisplay;
  820. vs1_pix_s = vs1_pix_e = hs_pix_s;
  821. vs1_line_s = mode->vsync_start - mode->vdisplay;
  822. vs1_line_e = vs1_line_s +
  823. mode->vsync_end - mode->vsync_start;
  824. vwin2_line_s = vwin2_line_e = 0;
  825. vs2_pix_s = vs2_pix_e = 0;
  826. vs2_line_s = vs2_line_e = 0;
  827. } else {
  828. ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
  829. vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
  830. vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
  831. vs1_pix_s = vs1_pix_e = hs_pix_s;
  832. vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
  833. vs1_line_e = vs1_line_s +
  834. (mode->vsync_end - mode->vsync_start)/2;
  835. vwin2_line_s = vwin1_line_s + mode->vtotal/2;
  836. vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
  837. vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
  838. vs2_line_s = vs1_line_s + mode->vtotal/2 ;
  839. vs2_line_e = vs2_line_s +
  840. (mode->vsync_end - mode->vsync_start)/2;
  841. }
  842. div = 148500 / mode->clock;
  843. if (div != 0) {
  844. div--;
  845. if (div > 3)
  846. div = 3;
  847. }
  848. /* mute the audio FIFO: */
  849. reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
  850. /* set HDMI HDCP mode off: */
  851. reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
  852. reg_clear(priv, REG_TX33, TX33_HDMI);
  853. reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
  854. /* no pre-filter or interpolator: */
  855. reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
  856. HVF_CNTRL_0_INTPOL(0));
  857. reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
  858. reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
  859. VIP_CNTRL_4_BLC(0));
  860. reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
  861. reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
  862. PLL_SERIAL_3_SRL_DE);
  863. reg_write(priv, REG_SERIALIZER, 0);
  864. reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
  865. /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
  866. rep = 0;
  867. reg_write(priv, REG_RPT_CNTRL, 0);
  868. reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
  869. SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
  870. reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
  871. PLL_SERIAL_2_SRL_PR(rep));
  872. /* set color matrix bypass flag: */
  873. reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
  874. MAT_CONTRL_MAT_SC(1));
  875. /* set BIAS tmds value: */
  876. reg_write(priv, REG_ANA_GENERAL, 0x09);
  877. /*
  878. * Sync on rising HSYNC/VSYNC
  879. */
  880. reg = VIP_CNTRL_3_SYNC_HS;
  881. /*
  882. * TDA19988 requires high-active sync at input stage,
  883. * so invert low-active sync provided by master encoder here
  884. */
  885. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  886. reg |= VIP_CNTRL_3_H_TGL;
  887. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  888. reg |= VIP_CNTRL_3_V_TGL;
  889. reg_write(priv, REG_VIP_CNTRL_3, reg);
  890. reg_write(priv, REG_VIDFORMAT, 0x00);
  891. reg_write16(priv, REG_REFPIX_MSB, ref_pix);
  892. reg_write16(priv, REG_REFLINE_MSB, ref_line);
  893. reg_write16(priv, REG_NPIX_MSB, n_pix);
  894. reg_write16(priv, REG_NLINE_MSB, n_line);
  895. reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
  896. reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
  897. reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
  898. reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
  899. reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
  900. reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
  901. reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
  902. reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
  903. reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
  904. reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
  905. reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
  906. reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
  907. reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
  908. reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
  909. reg_write16(priv, REG_DE_START_MSB, de_pix_s);
  910. reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
  911. if (priv->rev == TDA19988) {
  912. /* let incoming pixels fill the active space (if any) */
  913. reg_write(priv, REG_ENABLE_SPACE, 0x00);
  914. }
  915. /*
  916. * Always generate sync polarity relative to input sync and
  917. * revert input stage toggled sync at output stage
  918. */
  919. reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
  920. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  921. reg |= TBG_CNTRL_1_H_TGL;
  922. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  923. reg |= TBG_CNTRL_1_V_TGL;
  924. reg_write(priv, REG_TBG_CNTRL_1, reg);
  925. /* must be last register set: */
  926. reg_write(priv, REG_TBG_CNTRL_0, 0);
  927. /* Only setup the info frames if the sink is HDMI */
  928. if (priv->is_hdmi_sink) {
  929. /* We need to turn HDMI HDCP stuff on to get audio through */
  930. reg &= ~TBG_CNTRL_1_DWIN_DIS;
  931. reg_write(priv, REG_TBG_CNTRL_1, reg);
  932. reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
  933. reg_set(priv, REG_TX33, TX33_HDMI);
  934. tda998x_write_avi(priv, adjusted_mode);
  935. if (priv->params.audio_cfg)
  936. tda998x_configure_audio(priv, adjusted_mode,
  937. &priv->params);
  938. }
  939. }
  940. static enum drm_connector_status
  941. tda998x_connector_detect(struct drm_connector *connector, bool force)
  942. {
  943. struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
  944. u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
  945. return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
  946. connector_status_disconnected;
  947. }
  948. static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
  949. {
  950. struct tda998x_priv *priv = data;
  951. u8 offset, segptr;
  952. int ret, i;
  953. offset = (blk & 1) ? 128 : 0;
  954. segptr = blk / 2;
  955. reg_write(priv, REG_DDC_ADDR, 0xa0);
  956. reg_write(priv, REG_DDC_OFFS, offset);
  957. reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
  958. reg_write(priv, REG_DDC_SEGM, segptr);
  959. /* enable reading EDID: */
  960. priv->wq_edid_wait = 1;
  961. reg_write(priv, REG_EDID_CTRL, 0x1);
  962. /* flag must be cleared by sw: */
  963. reg_write(priv, REG_EDID_CTRL, 0x0);
  964. /* wait for block read to complete: */
  965. if (priv->hdmi->irq) {
  966. i = wait_event_timeout(priv->wq_edid,
  967. !priv->wq_edid_wait,
  968. msecs_to_jiffies(100));
  969. if (i < 0) {
  970. dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
  971. return i;
  972. }
  973. } else {
  974. for (i = 100; i > 0; i--) {
  975. msleep(1);
  976. ret = reg_read(priv, REG_INT_FLAGS_2);
  977. if (ret < 0)
  978. return ret;
  979. if (ret & INT_FLAGS_2_EDID_BLK_RD)
  980. break;
  981. }
  982. }
  983. if (i == 0) {
  984. dev_err(&priv->hdmi->dev, "read edid timeout\n");
  985. return -ETIMEDOUT;
  986. }
  987. ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
  988. if (ret != length) {
  989. dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
  990. blk, ret);
  991. return ret;
  992. }
  993. return 0;
  994. }
  995. static int tda998x_connector_get_modes(struct drm_connector *connector)
  996. {
  997. struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
  998. struct edid *edid;
  999. int n;
  1000. /*
  1001. * If we get killed while waiting for the HPD timeout, return
  1002. * no modes found: we are not in a restartable path, so we
  1003. * can't handle signals gracefully.
  1004. */
  1005. if (tda998x_edid_delay_wait(priv))
  1006. return 0;
  1007. if (priv->rev == TDA19988)
  1008. reg_clear(priv, REG_TX4, TX4_PD_RAM);
  1009. edid = drm_do_get_edid(connector, read_edid_block, priv);
  1010. if (priv->rev == TDA19988)
  1011. reg_set(priv, REG_TX4, TX4_PD_RAM);
  1012. if (!edid) {
  1013. dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
  1014. return 0;
  1015. }
  1016. drm_mode_connector_update_edid_property(connector, edid);
  1017. n = drm_add_edid_modes(connector, edid);
  1018. priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
  1019. kfree(edid);
  1020. return n;
  1021. }
  1022. static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
  1023. struct drm_connector *connector)
  1024. {
  1025. if (priv->hdmi->irq)
  1026. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1027. else
  1028. connector->polled = DRM_CONNECTOR_POLL_CONNECT |
  1029. DRM_CONNECTOR_POLL_DISCONNECT;
  1030. }
  1031. static void tda998x_destroy(struct tda998x_priv *priv)
  1032. {
  1033. /* disable all IRQs and free the IRQ handler */
  1034. cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
  1035. reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
  1036. if (priv->hdmi->irq)
  1037. free_irq(priv->hdmi->irq, priv);
  1038. del_timer_sync(&priv->edid_delay_timer);
  1039. cancel_work_sync(&priv->detect_work);
  1040. i2c_unregister_device(priv->cec);
  1041. }
  1042. /* I2C driver functions */
  1043. static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
  1044. {
  1045. struct device_node *np = client->dev.of_node;
  1046. u32 video;
  1047. int rev_lo, rev_hi, ret;
  1048. unsigned short cec_addr;
  1049. priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
  1050. priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
  1051. priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
  1052. priv->current_page = 0xff;
  1053. priv->hdmi = client;
  1054. /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
  1055. cec_addr = 0x34 + (client->addr & 0x03);
  1056. priv->cec = i2c_new_dummy(client->adapter, cec_addr);
  1057. if (!priv->cec)
  1058. return -ENODEV;
  1059. priv->dpms = DRM_MODE_DPMS_OFF;
  1060. mutex_init(&priv->mutex); /* protect the page access */
  1061. init_waitqueue_head(&priv->edid_delay_waitq);
  1062. setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
  1063. (unsigned long)priv);
  1064. INIT_WORK(&priv->detect_work, tda998x_detect_work);
  1065. /* wake up the device: */
  1066. cec_write(priv, REG_CEC_ENAMODS,
  1067. CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
  1068. tda998x_reset(priv);
  1069. /* read version: */
  1070. rev_lo = reg_read(priv, REG_VERSION_LSB);
  1071. rev_hi = reg_read(priv, REG_VERSION_MSB);
  1072. if (rev_lo < 0 || rev_hi < 0) {
  1073. ret = rev_lo < 0 ? rev_lo : rev_hi;
  1074. goto fail;
  1075. }
  1076. priv->rev = rev_lo | rev_hi << 8;
  1077. /* mask off feature bits: */
  1078. priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
  1079. switch (priv->rev) {
  1080. case TDA9989N2:
  1081. dev_info(&client->dev, "found TDA9989 n2");
  1082. break;
  1083. case TDA19989:
  1084. dev_info(&client->dev, "found TDA19989");
  1085. break;
  1086. case TDA19989N2:
  1087. dev_info(&client->dev, "found TDA19989 n2");
  1088. break;
  1089. case TDA19988:
  1090. dev_info(&client->dev, "found TDA19988");
  1091. break;
  1092. default:
  1093. dev_err(&client->dev, "found unsupported device: %04x\n",
  1094. priv->rev);
  1095. goto fail;
  1096. }
  1097. /* after reset, enable DDC: */
  1098. reg_write(priv, REG_DDC_DISABLE, 0x00);
  1099. /* set clock on DDC channel: */
  1100. reg_write(priv, REG_TX3, 39);
  1101. /* if necessary, disable multi-master: */
  1102. if (priv->rev == TDA19989)
  1103. reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
  1104. cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
  1105. CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
  1106. /* initialize the optional IRQ */
  1107. if (client->irq) {
  1108. int irqf_trigger;
  1109. /* init read EDID waitqueue and HDP work */
  1110. init_waitqueue_head(&priv->wq_edid);
  1111. /* clear pending interrupts */
  1112. reg_read(priv, REG_INT_FLAGS_0);
  1113. reg_read(priv, REG_INT_FLAGS_1);
  1114. reg_read(priv, REG_INT_FLAGS_2);
  1115. irqf_trigger =
  1116. irqd_get_trigger_type(irq_get_irq_data(client->irq));
  1117. ret = request_threaded_irq(client->irq, NULL,
  1118. tda998x_irq_thread,
  1119. irqf_trigger | IRQF_ONESHOT,
  1120. "tda998x", priv);
  1121. if (ret) {
  1122. dev_err(&client->dev,
  1123. "failed to request IRQ#%u: %d\n",
  1124. client->irq, ret);
  1125. goto fail;
  1126. }
  1127. /* enable HPD irq */
  1128. cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
  1129. }
  1130. /* enable EDID read irq: */
  1131. reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
  1132. if (!np)
  1133. return 0; /* non-DT */
  1134. /* get the optional video properties */
  1135. ret = of_property_read_u32(np, "video-ports", &video);
  1136. if (ret == 0) {
  1137. priv->vip_cntrl_0 = video >> 16;
  1138. priv->vip_cntrl_1 = video >> 8;
  1139. priv->vip_cntrl_2 = video;
  1140. }
  1141. return 0;
  1142. fail:
  1143. /* if encoder_init fails, the encoder slave is never registered,
  1144. * so cleanup here:
  1145. */
  1146. if (priv->cec)
  1147. i2c_unregister_device(priv->cec);
  1148. return -ENXIO;
  1149. }
  1150. static void tda998x_encoder_prepare(struct drm_encoder *encoder)
  1151. {
  1152. tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  1153. }
  1154. static void tda998x_encoder_commit(struct drm_encoder *encoder)
  1155. {
  1156. tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
  1157. }
  1158. static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
  1159. .dpms = tda998x_encoder_dpms,
  1160. .save = tda998x_encoder_save,
  1161. .restore = tda998x_encoder_restore,
  1162. .mode_fixup = tda998x_encoder_mode_fixup,
  1163. .prepare = tda998x_encoder_prepare,
  1164. .commit = tda998x_encoder_commit,
  1165. .mode_set = tda998x_encoder_mode_set,
  1166. };
  1167. static void tda998x_encoder_destroy(struct drm_encoder *encoder)
  1168. {
  1169. struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
  1170. tda998x_destroy(priv);
  1171. drm_encoder_cleanup(encoder);
  1172. }
  1173. static const struct drm_encoder_funcs tda998x_encoder_funcs = {
  1174. .destroy = tda998x_encoder_destroy,
  1175. };
  1176. static struct drm_encoder *
  1177. tda998x_connector_best_encoder(struct drm_connector *connector)
  1178. {
  1179. struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
  1180. return &priv->encoder;
  1181. }
  1182. static
  1183. const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
  1184. .get_modes = tda998x_connector_get_modes,
  1185. .mode_valid = tda998x_connector_mode_valid,
  1186. .best_encoder = tda998x_connector_best_encoder,
  1187. };
  1188. static void tda998x_connector_destroy(struct drm_connector *connector)
  1189. {
  1190. drm_connector_unregister(connector);
  1191. drm_connector_cleanup(connector);
  1192. }
  1193. static const struct drm_connector_funcs tda998x_connector_funcs = {
  1194. .dpms = drm_helper_connector_dpms,
  1195. .fill_modes = drm_helper_probe_single_connector_modes,
  1196. .detect = tda998x_connector_detect,
  1197. .destroy = tda998x_connector_destroy,
  1198. };
  1199. static int tda998x_bind(struct device *dev, struct device *master, void *data)
  1200. {
  1201. struct tda998x_encoder_params *params = dev->platform_data;
  1202. struct i2c_client *client = to_i2c_client(dev);
  1203. struct drm_device *drm = data;
  1204. struct tda998x_priv *priv;
  1205. u32 crtcs = 0;
  1206. int ret;
  1207. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  1208. if (!priv)
  1209. return -ENOMEM;
  1210. dev_set_drvdata(dev, priv);
  1211. if (dev->of_node)
  1212. crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
  1213. /* If no CRTCs were found, fall back to our old behaviour */
  1214. if (crtcs == 0) {
  1215. dev_warn(dev, "Falling back to first CRTC\n");
  1216. crtcs = 1 << 0;
  1217. }
  1218. priv->connector.interlace_allowed = 1;
  1219. priv->encoder.possible_crtcs = crtcs;
  1220. ret = tda998x_create(client, priv);
  1221. if (ret)
  1222. return ret;
  1223. if (!dev->of_node && params)
  1224. tda998x_encoder_set_config(priv, params);
  1225. tda998x_encoder_set_polling(priv, &priv->connector);
  1226. drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
  1227. ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
  1228. DRM_MODE_ENCODER_TMDS);
  1229. if (ret)
  1230. goto err_encoder;
  1231. drm_connector_helper_add(&priv->connector,
  1232. &tda998x_connector_helper_funcs);
  1233. ret = drm_connector_init(drm, &priv->connector,
  1234. &tda998x_connector_funcs,
  1235. DRM_MODE_CONNECTOR_HDMIA);
  1236. if (ret)
  1237. goto err_connector;
  1238. ret = drm_connector_register(&priv->connector);
  1239. if (ret)
  1240. goto err_sysfs;
  1241. priv->connector.encoder = &priv->encoder;
  1242. drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
  1243. return 0;
  1244. err_sysfs:
  1245. drm_connector_cleanup(&priv->connector);
  1246. err_connector:
  1247. drm_encoder_cleanup(&priv->encoder);
  1248. err_encoder:
  1249. tda998x_destroy(priv);
  1250. return ret;
  1251. }
  1252. static void tda998x_unbind(struct device *dev, struct device *master,
  1253. void *data)
  1254. {
  1255. struct tda998x_priv *priv = dev_get_drvdata(dev);
  1256. drm_connector_cleanup(&priv->connector);
  1257. drm_encoder_cleanup(&priv->encoder);
  1258. tda998x_destroy(priv);
  1259. }
  1260. static const struct component_ops tda998x_ops = {
  1261. .bind = tda998x_bind,
  1262. .unbind = tda998x_unbind,
  1263. };
  1264. static int
  1265. tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
  1266. {
  1267. return component_add(&client->dev, &tda998x_ops);
  1268. }
  1269. static int tda998x_remove(struct i2c_client *client)
  1270. {
  1271. component_del(&client->dev, &tda998x_ops);
  1272. return 0;
  1273. }
  1274. #ifdef CONFIG_OF
  1275. static const struct of_device_id tda998x_dt_ids[] = {
  1276. { .compatible = "nxp,tda998x", },
  1277. { }
  1278. };
  1279. MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
  1280. #endif
  1281. static struct i2c_device_id tda998x_ids[] = {
  1282. { "tda998x", 0 },
  1283. { }
  1284. };
  1285. MODULE_DEVICE_TABLE(i2c, tda998x_ids);
  1286. static struct i2c_driver tda998x_driver = {
  1287. .probe = tda998x_probe,
  1288. .remove = tda998x_remove,
  1289. .driver = {
  1290. .name = "tda998x",
  1291. .of_match_table = of_match_ptr(tda998x_dt_ids),
  1292. },
  1293. .id_table = tda998x_ids,
  1294. };
  1295. module_i2c_driver(tda998x_driver);
  1296. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  1297. MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
  1298. MODULE_LICENSE("GPL");