i915_gem_execbuffer.c 47 KB

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  1. /*
  2. * Copyright © 2008,2010 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Chris Wilson <chris@chris-wilson.co.uk>
  26. *
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include "i915_trace.h"
  32. #include "intel_drv.h"
  33. #include <linux/dma_remapping.h>
  34. #include <linux/uaccess.h>
  35. #define __EXEC_OBJECT_HAS_PIN (1<<31)
  36. #define __EXEC_OBJECT_HAS_FENCE (1<<30)
  37. #define __EXEC_OBJECT_NEEDS_MAP (1<<29)
  38. #define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
  39. #define BATCH_OFFSET_BIAS (256*1024)
  40. struct eb_vmas {
  41. struct list_head vmas;
  42. int and;
  43. union {
  44. struct i915_vma *lut[0];
  45. struct hlist_head buckets[0];
  46. };
  47. };
  48. static struct eb_vmas *
  49. eb_create(struct drm_i915_gem_execbuffer2 *args)
  50. {
  51. struct eb_vmas *eb = NULL;
  52. if (args->flags & I915_EXEC_HANDLE_LUT) {
  53. unsigned size = args->buffer_count;
  54. size *= sizeof(struct i915_vma *);
  55. size += sizeof(struct eb_vmas);
  56. eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  57. }
  58. if (eb == NULL) {
  59. unsigned size = args->buffer_count;
  60. unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  61. BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  62. while (count > 2*size)
  63. count >>= 1;
  64. eb = kzalloc(count*sizeof(struct hlist_head) +
  65. sizeof(struct eb_vmas),
  66. GFP_TEMPORARY);
  67. if (eb == NULL)
  68. return eb;
  69. eb->and = count - 1;
  70. } else
  71. eb->and = -args->buffer_count;
  72. INIT_LIST_HEAD(&eb->vmas);
  73. return eb;
  74. }
  75. static void
  76. eb_reset(struct eb_vmas *eb)
  77. {
  78. if (eb->and >= 0)
  79. memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
  80. }
  81. static int
  82. eb_lookup_vmas(struct eb_vmas *eb,
  83. struct drm_i915_gem_exec_object2 *exec,
  84. const struct drm_i915_gem_execbuffer2 *args,
  85. struct i915_address_space *vm,
  86. struct drm_file *file)
  87. {
  88. struct drm_i915_gem_object *obj;
  89. struct list_head objects;
  90. int i, ret;
  91. INIT_LIST_HEAD(&objects);
  92. spin_lock(&file->table_lock);
  93. /* Grab a reference to the object and release the lock so we can lookup
  94. * or create the VMA without using GFP_ATOMIC */
  95. for (i = 0; i < args->buffer_count; i++) {
  96. obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
  97. if (obj == NULL) {
  98. spin_unlock(&file->table_lock);
  99. DRM_DEBUG("Invalid object handle %d at index %d\n",
  100. exec[i].handle, i);
  101. ret = -ENOENT;
  102. goto err;
  103. }
  104. if (!list_empty(&obj->obj_exec_link)) {
  105. spin_unlock(&file->table_lock);
  106. DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
  107. obj, exec[i].handle, i);
  108. ret = -EINVAL;
  109. goto err;
  110. }
  111. drm_gem_object_reference(&obj->base);
  112. list_add_tail(&obj->obj_exec_link, &objects);
  113. }
  114. spin_unlock(&file->table_lock);
  115. i = 0;
  116. while (!list_empty(&objects)) {
  117. struct i915_vma *vma;
  118. obj = list_first_entry(&objects,
  119. struct drm_i915_gem_object,
  120. obj_exec_link);
  121. /*
  122. * NOTE: We can leak any vmas created here when something fails
  123. * later on. But that's no issue since vma_unbind can deal with
  124. * vmas which are not actually bound. And since only
  125. * lookup_or_create exists as an interface to get at the vma
  126. * from the (obj, vm) we don't run the risk of creating
  127. * duplicated vmas for the same vm.
  128. */
  129. vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
  130. if (IS_ERR(vma)) {
  131. DRM_DEBUG("Failed to lookup VMA\n");
  132. ret = PTR_ERR(vma);
  133. goto err;
  134. }
  135. /* Transfer ownership from the objects list to the vmas list. */
  136. list_add_tail(&vma->exec_list, &eb->vmas);
  137. list_del_init(&obj->obj_exec_link);
  138. vma->exec_entry = &exec[i];
  139. if (eb->and < 0) {
  140. eb->lut[i] = vma;
  141. } else {
  142. uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
  143. vma->exec_handle = handle;
  144. hlist_add_head(&vma->exec_node,
  145. &eb->buckets[handle & eb->and]);
  146. }
  147. ++i;
  148. }
  149. return 0;
  150. err:
  151. while (!list_empty(&objects)) {
  152. obj = list_first_entry(&objects,
  153. struct drm_i915_gem_object,
  154. obj_exec_link);
  155. list_del_init(&obj->obj_exec_link);
  156. drm_gem_object_unreference(&obj->base);
  157. }
  158. /*
  159. * Objects already transfered to the vmas list will be unreferenced by
  160. * eb_destroy.
  161. */
  162. return ret;
  163. }
  164. static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
  165. {
  166. if (eb->and < 0) {
  167. if (handle >= -eb->and)
  168. return NULL;
  169. return eb->lut[handle];
  170. } else {
  171. struct hlist_head *head;
  172. struct hlist_node *node;
  173. head = &eb->buckets[handle & eb->and];
  174. hlist_for_each(node, head) {
  175. struct i915_vma *vma;
  176. vma = hlist_entry(node, struct i915_vma, exec_node);
  177. if (vma->exec_handle == handle)
  178. return vma;
  179. }
  180. return NULL;
  181. }
  182. }
  183. static void
  184. i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
  185. {
  186. struct drm_i915_gem_exec_object2 *entry;
  187. struct drm_i915_gem_object *obj = vma->obj;
  188. if (!drm_mm_node_allocated(&vma->node))
  189. return;
  190. entry = vma->exec_entry;
  191. if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
  192. i915_gem_object_unpin_fence(obj);
  193. if (entry->flags & __EXEC_OBJECT_HAS_PIN)
  194. vma->pin_count--;
  195. entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
  196. }
  197. static void eb_destroy(struct eb_vmas *eb)
  198. {
  199. while (!list_empty(&eb->vmas)) {
  200. struct i915_vma *vma;
  201. vma = list_first_entry(&eb->vmas,
  202. struct i915_vma,
  203. exec_list);
  204. list_del_init(&vma->exec_list);
  205. i915_gem_execbuffer_unreserve_vma(vma);
  206. drm_gem_object_unreference(&vma->obj->base);
  207. }
  208. kfree(eb);
  209. }
  210. static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
  211. {
  212. return (HAS_LLC(obj->base.dev) ||
  213. obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
  214. obj->cache_level != I915_CACHE_NONE);
  215. }
  216. static int
  217. relocate_entry_cpu(struct drm_i915_gem_object *obj,
  218. struct drm_i915_gem_relocation_entry *reloc,
  219. uint64_t target_offset)
  220. {
  221. struct drm_device *dev = obj->base.dev;
  222. uint32_t page_offset = offset_in_page(reloc->offset);
  223. uint64_t delta = reloc->delta + target_offset;
  224. char *vaddr;
  225. int ret;
  226. ret = i915_gem_object_set_to_cpu_domain(obj, true);
  227. if (ret)
  228. return ret;
  229. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  230. reloc->offset >> PAGE_SHIFT));
  231. *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
  232. if (INTEL_INFO(dev)->gen >= 8) {
  233. page_offset = offset_in_page(page_offset + sizeof(uint32_t));
  234. if (page_offset == 0) {
  235. kunmap_atomic(vaddr);
  236. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  237. (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
  238. }
  239. *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
  240. }
  241. kunmap_atomic(vaddr);
  242. return 0;
  243. }
  244. static int
  245. relocate_entry_gtt(struct drm_i915_gem_object *obj,
  246. struct drm_i915_gem_relocation_entry *reloc,
  247. uint64_t target_offset)
  248. {
  249. struct drm_device *dev = obj->base.dev;
  250. struct drm_i915_private *dev_priv = dev->dev_private;
  251. uint64_t delta = reloc->delta + target_offset;
  252. uint64_t offset;
  253. void __iomem *reloc_page;
  254. int ret;
  255. ret = i915_gem_object_set_to_gtt_domain(obj, true);
  256. if (ret)
  257. return ret;
  258. ret = i915_gem_object_put_fence(obj);
  259. if (ret)
  260. return ret;
  261. /* Map the page containing the relocation we're going to perform. */
  262. offset = i915_gem_obj_ggtt_offset(obj);
  263. offset += reloc->offset;
  264. reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  265. offset & PAGE_MASK);
  266. iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
  267. if (INTEL_INFO(dev)->gen >= 8) {
  268. offset += sizeof(uint32_t);
  269. if (offset_in_page(offset) == 0) {
  270. io_mapping_unmap_atomic(reloc_page);
  271. reloc_page =
  272. io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  273. offset);
  274. }
  275. iowrite32(upper_32_bits(delta),
  276. reloc_page + offset_in_page(offset));
  277. }
  278. io_mapping_unmap_atomic(reloc_page);
  279. return 0;
  280. }
  281. static void
  282. clflush_write32(void *addr, uint32_t value)
  283. {
  284. /* This is not a fast path, so KISS. */
  285. drm_clflush_virt_range(addr, sizeof(uint32_t));
  286. *(uint32_t *)addr = value;
  287. drm_clflush_virt_range(addr, sizeof(uint32_t));
  288. }
  289. static int
  290. relocate_entry_clflush(struct drm_i915_gem_object *obj,
  291. struct drm_i915_gem_relocation_entry *reloc,
  292. uint64_t target_offset)
  293. {
  294. struct drm_device *dev = obj->base.dev;
  295. uint32_t page_offset = offset_in_page(reloc->offset);
  296. uint64_t delta = (int)reloc->delta + target_offset;
  297. char *vaddr;
  298. int ret;
  299. ret = i915_gem_object_set_to_gtt_domain(obj, true);
  300. if (ret)
  301. return ret;
  302. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  303. reloc->offset >> PAGE_SHIFT));
  304. clflush_write32(vaddr + page_offset, lower_32_bits(delta));
  305. if (INTEL_INFO(dev)->gen >= 8) {
  306. page_offset = offset_in_page(page_offset + sizeof(uint32_t));
  307. if (page_offset == 0) {
  308. kunmap_atomic(vaddr);
  309. vaddr = kmap_atomic(i915_gem_object_get_page(obj,
  310. (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
  311. }
  312. clflush_write32(vaddr + page_offset, upper_32_bits(delta));
  313. }
  314. kunmap_atomic(vaddr);
  315. return 0;
  316. }
  317. static int
  318. i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
  319. struct eb_vmas *eb,
  320. struct drm_i915_gem_relocation_entry *reloc)
  321. {
  322. struct drm_device *dev = obj->base.dev;
  323. struct drm_gem_object *target_obj;
  324. struct drm_i915_gem_object *target_i915_obj;
  325. struct i915_vma *target_vma;
  326. uint64_t target_offset;
  327. int ret;
  328. /* we've already hold a reference to all valid objects */
  329. target_vma = eb_get_vma(eb, reloc->target_handle);
  330. if (unlikely(target_vma == NULL))
  331. return -ENOENT;
  332. target_i915_obj = target_vma->obj;
  333. target_obj = &target_vma->obj->base;
  334. target_offset = target_vma->node.start;
  335. /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
  336. * pipe_control writes because the gpu doesn't properly redirect them
  337. * through the ppgtt for non_secure batchbuffers. */
  338. if (unlikely(IS_GEN6(dev) &&
  339. reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
  340. ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
  341. PIN_GLOBAL);
  342. if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
  343. return ret;
  344. }
  345. /* Validate that the target is in a valid r/w GPU domain */
  346. if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
  347. DRM_DEBUG("reloc with multiple write domains: "
  348. "obj %p target %d offset %d "
  349. "read %08x write %08x",
  350. obj, reloc->target_handle,
  351. (int) reloc->offset,
  352. reloc->read_domains,
  353. reloc->write_domain);
  354. return -EINVAL;
  355. }
  356. if (unlikely((reloc->write_domain | reloc->read_domains)
  357. & ~I915_GEM_GPU_DOMAINS)) {
  358. DRM_DEBUG("reloc with read/write non-GPU domains: "
  359. "obj %p target %d offset %d "
  360. "read %08x write %08x",
  361. obj, reloc->target_handle,
  362. (int) reloc->offset,
  363. reloc->read_domains,
  364. reloc->write_domain);
  365. return -EINVAL;
  366. }
  367. target_obj->pending_read_domains |= reloc->read_domains;
  368. target_obj->pending_write_domain |= reloc->write_domain;
  369. /* If the relocation already has the right value in it, no
  370. * more work needs to be done.
  371. */
  372. if (target_offset == reloc->presumed_offset)
  373. return 0;
  374. /* Check that the relocation address is valid... */
  375. if (unlikely(reloc->offset >
  376. obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
  377. DRM_DEBUG("Relocation beyond object bounds: "
  378. "obj %p target %d offset %d size %d.\n",
  379. obj, reloc->target_handle,
  380. (int) reloc->offset,
  381. (int) obj->base.size);
  382. return -EINVAL;
  383. }
  384. if (unlikely(reloc->offset & 3)) {
  385. DRM_DEBUG("Relocation not 4-byte aligned: "
  386. "obj %p target %d offset %d.\n",
  387. obj, reloc->target_handle,
  388. (int) reloc->offset);
  389. return -EINVAL;
  390. }
  391. /* We can't wait for rendering with pagefaults disabled */
  392. if (obj->active && pagefault_disabled())
  393. return -EFAULT;
  394. if (use_cpu_reloc(obj))
  395. ret = relocate_entry_cpu(obj, reloc, target_offset);
  396. else if (obj->map_and_fenceable)
  397. ret = relocate_entry_gtt(obj, reloc, target_offset);
  398. else if (cpu_has_clflush)
  399. ret = relocate_entry_clflush(obj, reloc, target_offset);
  400. else {
  401. WARN_ONCE(1, "Impossible case in relocation handling\n");
  402. ret = -ENODEV;
  403. }
  404. if (ret)
  405. return ret;
  406. /* and update the user's relocation entry */
  407. reloc->presumed_offset = target_offset;
  408. return 0;
  409. }
  410. static int
  411. i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
  412. struct eb_vmas *eb)
  413. {
  414. #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
  415. struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
  416. struct drm_i915_gem_relocation_entry __user *user_relocs;
  417. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  418. int remain, ret;
  419. user_relocs = to_user_ptr(entry->relocs_ptr);
  420. remain = entry->relocation_count;
  421. while (remain) {
  422. struct drm_i915_gem_relocation_entry *r = stack_reloc;
  423. int count = remain;
  424. if (count > ARRAY_SIZE(stack_reloc))
  425. count = ARRAY_SIZE(stack_reloc);
  426. remain -= count;
  427. if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
  428. return -EFAULT;
  429. do {
  430. u64 offset = r->presumed_offset;
  431. ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
  432. if (ret)
  433. return ret;
  434. if (r->presumed_offset != offset &&
  435. __copy_to_user_inatomic(&user_relocs->presumed_offset,
  436. &r->presumed_offset,
  437. sizeof(r->presumed_offset))) {
  438. return -EFAULT;
  439. }
  440. user_relocs++;
  441. r++;
  442. } while (--count);
  443. }
  444. return 0;
  445. #undef N_RELOC
  446. }
  447. static int
  448. i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
  449. struct eb_vmas *eb,
  450. struct drm_i915_gem_relocation_entry *relocs)
  451. {
  452. const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  453. int i, ret;
  454. for (i = 0; i < entry->relocation_count; i++) {
  455. ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
  456. if (ret)
  457. return ret;
  458. }
  459. return 0;
  460. }
  461. static int
  462. i915_gem_execbuffer_relocate(struct eb_vmas *eb)
  463. {
  464. struct i915_vma *vma;
  465. int ret = 0;
  466. /* This is the fast path and we cannot handle a pagefault whilst
  467. * holding the struct mutex lest the user pass in the relocations
  468. * contained within a mmaped bo. For in such a case we, the page
  469. * fault handler would call i915_gem_fault() and we would try to
  470. * acquire the struct mutex again. Obviously this is bad and so
  471. * lockdep complains vehemently.
  472. */
  473. pagefault_disable();
  474. list_for_each_entry(vma, &eb->vmas, exec_list) {
  475. ret = i915_gem_execbuffer_relocate_vma(vma, eb);
  476. if (ret)
  477. break;
  478. }
  479. pagefault_enable();
  480. return ret;
  481. }
  482. static bool only_mappable_for_reloc(unsigned int flags)
  483. {
  484. return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
  485. __EXEC_OBJECT_NEEDS_MAP;
  486. }
  487. static int
  488. i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
  489. struct intel_engine_cs *ring,
  490. bool *need_reloc)
  491. {
  492. struct drm_i915_gem_object *obj = vma->obj;
  493. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  494. uint64_t flags;
  495. int ret;
  496. flags = PIN_USER;
  497. if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
  498. flags |= PIN_GLOBAL;
  499. if (!drm_mm_node_allocated(&vma->node)) {
  500. /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
  501. * limit address to the first 4GBs for unflagged objects.
  502. */
  503. if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
  504. flags |= PIN_ZONE_4G;
  505. if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
  506. flags |= PIN_GLOBAL | PIN_MAPPABLE;
  507. if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
  508. flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
  509. if ((flags & PIN_MAPPABLE) == 0)
  510. flags |= PIN_HIGH;
  511. }
  512. ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
  513. if ((ret == -ENOSPC || ret == -E2BIG) &&
  514. only_mappable_for_reloc(entry->flags))
  515. ret = i915_gem_object_pin(obj, vma->vm,
  516. entry->alignment,
  517. flags & ~PIN_MAPPABLE);
  518. if (ret)
  519. return ret;
  520. entry->flags |= __EXEC_OBJECT_HAS_PIN;
  521. if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
  522. ret = i915_gem_object_get_fence(obj);
  523. if (ret)
  524. return ret;
  525. if (i915_gem_object_pin_fence(obj))
  526. entry->flags |= __EXEC_OBJECT_HAS_FENCE;
  527. }
  528. if (entry->offset != vma->node.start) {
  529. entry->offset = vma->node.start;
  530. *need_reloc = true;
  531. }
  532. if (entry->flags & EXEC_OBJECT_WRITE) {
  533. obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
  534. obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
  535. }
  536. return 0;
  537. }
  538. static bool
  539. need_reloc_mappable(struct i915_vma *vma)
  540. {
  541. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  542. if (entry->relocation_count == 0)
  543. return false;
  544. if (!i915_is_ggtt(vma->vm))
  545. return false;
  546. /* See also use_cpu_reloc() */
  547. if (HAS_LLC(vma->obj->base.dev))
  548. return false;
  549. if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
  550. return false;
  551. return true;
  552. }
  553. static bool
  554. eb_vma_misplaced(struct i915_vma *vma)
  555. {
  556. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  557. struct drm_i915_gem_object *obj = vma->obj;
  558. WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
  559. !i915_is_ggtt(vma->vm));
  560. if (entry->alignment &&
  561. vma->node.start & (entry->alignment - 1))
  562. return true;
  563. if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
  564. vma->node.start < BATCH_OFFSET_BIAS)
  565. return true;
  566. /* avoid costly ping-pong once a batch bo ended up non-mappable */
  567. if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
  568. return !only_mappable_for_reloc(entry->flags);
  569. if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
  570. (vma->node.start + vma->node.size - 1) >> 32)
  571. return true;
  572. return false;
  573. }
  574. static int
  575. i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
  576. struct list_head *vmas,
  577. struct intel_context *ctx,
  578. bool *need_relocs)
  579. {
  580. struct drm_i915_gem_object *obj;
  581. struct i915_vma *vma;
  582. struct i915_address_space *vm;
  583. struct list_head ordered_vmas;
  584. bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
  585. int retry;
  586. i915_gem_retire_requests_ring(ring);
  587. vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
  588. INIT_LIST_HEAD(&ordered_vmas);
  589. while (!list_empty(vmas)) {
  590. struct drm_i915_gem_exec_object2 *entry;
  591. bool need_fence, need_mappable;
  592. vma = list_first_entry(vmas, struct i915_vma, exec_list);
  593. obj = vma->obj;
  594. entry = vma->exec_entry;
  595. if (ctx->flags & CONTEXT_NO_ZEROMAP)
  596. entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
  597. if (!has_fenced_gpu_access)
  598. entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
  599. need_fence =
  600. entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
  601. obj->tiling_mode != I915_TILING_NONE;
  602. need_mappable = need_fence || need_reloc_mappable(vma);
  603. if (need_mappable) {
  604. entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
  605. list_move(&vma->exec_list, &ordered_vmas);
  606. } else
  607. list_move_tail(&vma->exec_list, &ordered_vmas);
  608. obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
  609. obj->base.pending_write_domain = 0;
  610. }
  611. list_splice(&ordered_vmas, vmas);
  612. /* Attempt to pin all of the buffers into the GTT.
  613. * This is done in 3 phases:
  614. *
  615. * 1a. Unbind all objects that do not match the GTT constraints for
  616. * the execbuffer (fenceable, mappable, alignment etc).
  617. * 1b. Increment pin count for already bound objects.
  618. * 2. Bind new objects.
  619. * 3. Decrement pin count.
  620. *
  621. * This avoid unnecessary unbinding of later objects in order to make
  622. * room for the earlier objects *unless* we need to defragment.
  623. */
  624. retry = 0;
  625. do {
  626. int ret = 0;
  627. /* Unbind any ill-fitting objects or pin. */
  628. list_for_each_entry(vma, vmas, exec_list) {
  629. if (!drm_mm_node_allocated(&vma->node))
  630. continue;
  631. if (eb_vma_misplaced(vma))
  632. ret = i915_vma_unbind(vma);
  633. else
  634. ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
  635. if (ret)
  636. goto err;
  637. }
  638. /* Bind fresh objects */
  639. list_for_each_entry(vma, vmas, exec_list) {
  640. if (drm_mm_node_allocated(&vma->node))
  641. continue;
  642. ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);
  643. if (ret)
  644. goto err;
  645. }
  646. err:
  647. if (ret != -ENOSPC || retry++)
  648. return ret;
  649. /* Decrement pin count for bound objects */
  650. list_for_each_entry(vma, vmas, exec_list)
  651. i915_gem_execbuffer_unreserve_vma(vma);
  652. ret = i915_gem_evict_vm(vm, true);
  653. if (ret)
  654. return ret;
  655. } while (1);
  656. }
  657. static int
  658. i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
  659. struct drm_i915_gem_execbuffer2 *args,
  660. struct drm_file *file,
  661. struct intel_engine_cs *ring,
  662. struct eb_vmas *eb,
  663. struct drm_i915_gem_exec_object2 *exec,
  664. struct intel_context *ctx)
  665. {
  666. struct drm_i915_gem_relocation_entry *reloc;
  667. struct i915_address_space *vm;
  668. struct i915_vma *vma;
  669. bool need_relocs;
  670. int *reloc_offset;
  671. int i, total, ret;
  672. unsigned count = args->buffer_count;
  673. vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
  674. /* We may process another execbuffer during the unlock... */
  675. while (!list_empty(&eb->vmas)) {
  676. vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
  677. list_del_init(&vma->exec_list);
  678. i915_gem_execbuffer_unreserve_vma(vma);
  679. drm_gem_object_unreference(&vma->obj->base);
  680. }
  681. mutex_unlock(&dev->struct_mutex);
  682. total = 0;
  683. for (i = 0; i < count; i++)
  684. total += exec[i].relocation_count;
  685. reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
  686. reloc = drm_malloc_ab(total, sizeof(*reloc));
  687. if (reloc == NULL || reloc_offset == NULL) {
  688. drm_free_large(reloc);
  689. drm_free_large(reloc_offset);
  690. mutex_lock(&dev->struct_mutex);
  691. return -ENOMEM;
  692. }
  693. total = 0;
  694. for (i = 0; i < count; i++) {
  695. struct drm_i915_gem_relocation_entry __user *user_relocs;
  696. u64 invalid_offset = (u64)-1;
  697. int j;
  698. user_relocs = to_user_ptr(exec[i].relocs_ptr);
  699. if (copy_from_user(reloc+total, user_relocs,
  700. exec[i].relocation_count * sizeof(*reloc))) {
  701. ret = -EFAULT;
  702. mutex_lock(&dev->struct_mutex);
  703. goto err;
  704. }
  705. /* As we do not update the known relocation offsets after
  706. * relocating (due to the complexities in lock handling),
  707. * we need to mark them as invalid now so that we force the
  708. * relocation processing next time. Just in case the target
  709. * object is evicted and then rebound into its old
  710. * presumed_offset before the next execbuffer - if that
  711. * happened we would make the mistake of assuming that the
  712. * relocations were valid.
  713. */
  714. for (j = 0; j < exec[i].relocation_count; j++) {
  715. if (__copy_to_user(&user_relocs[j].presumed_offset,
  716. &invalid_offset,
  717. sizeof(invalid_offset))) {
  718. ret = -EFAULT;
  719. mutex_lock(&dev->struct_mutex);
  720. goto err;
  721. }
  722. }
  723. reloc_offset[i] = total;
  724. total += exec[i].relocation_count;
  725. }
  726. ret = i915_mutex_lock_interruptible(dev);
  727. if (ret) {
  728. mutex_lock(&dev->struct_mutex);
  729. goto err;
  730. }
  731. /* reacquire the objects */
  732. eb_reset(eb);
  733. ret = eb_lookup_vmas(eb, exec, args, vm, file);
  734. if (ret)
  735. goto err;
  736. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  737. ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
  738. if (ret)
  739. goto err;
  740. list_for_each_entry(vma, &eb->vmas, exec_list) {
  741. int offset = vma->exec_entry - exec;
  742. ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
  743. reloc + reloc_offset[offset]);
  744. if (ret)
  745. goto err;
  746. }
  747. /* Leave the user relocations as are, this is the painfully slow path,
  748. * and we want to avoid the complication of dropping the lock whilst
  749. * having buffers reserved in the aperture and so causing spurious
  750. * ENOSPC for random operations.
  751. */
  752. err:
  753. drm_free_large(reloc);
  754. drm_free_large(reloc_offset);
  755. return ret;
  756. }
  757. static int
  758. i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
  759. struct list_head *vmas)
  760. {
  761. const unsigned other_rings = ~intel_ring_flag(req->ring);
  762. struct i915_vma *vma;
  763. uint32_t flush_domains = 0;
  764. bool flush_chipset = false;
  765. int ret;
  766. list_for_each_entry(vma, vmas, exec_list) {
  767. struct drm_i915_gem_object *obj = vma->obj;
  768. if (obj->active & other_rings) {
  769. ret = i915_gem_object_sync(obj, req->ring, &req);
  770. if (ret)
  771. return ret;
  772. }
  773. if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
  774. flush_chipset |= i915_gem_clflush_object(obj, false);
  775. flush_domains |= obj->base.write_domain;
  776. }
  777. if (flush_chipset)
  778. i915_gem_chipset_flush(req->ring->dev);
  779. if (flush_domains & I915_GEM_DOMAIN_GTT)
  780. wmb();
  781. /* Unconditionally invalidate gpu caches and ensure that we do flush
  782. * any residual writes from the previous batch.
  783. */
  784. return intel_ring_invalidate_all_caches(req);
  785. }
  786. static bool
  787. i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
  788. {
  789. if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
  790. return false;
  791. /* Kernel clipping was a DRI1 misfeature */
  792. if (exec->num_cliprects || exec->cliprects_ptr)
  793. return false;
  794. if (exec->DR4 == 0xffffffff) {
  795. DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
  796. exec->DR4 = 0;
  797. }
  798. if (exec->DR1 || exec->DR4)
  799. return false;
  800. if ((exec->batch_start_offset | exec->batch_len) & 0x7)
  801. return false;
  802. return true;
  803. }
  804. static int
  805. validate_exec_list(struct drm_device *dev,
  806. struct drm_i915_gem_exec_object2 *exec,
  807. int count)
  808. {
  809. unsigned relocs_total = 0;
  810. unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
  811. unsigned invalid_flags;
  812. int i;
  813. invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
  814. if (USES_FULL_PPGTT(dev))
  815. invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
  816. for (i = 0; i < count; i++) {
  817. char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
  818. int length; /* limited by fault_in_pages_readable() */
  819. if (exec[i].flags & invalid_flags)
  820. return -EINVAL;
  821. if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
  822. return -EINVAL;
  823. /* First check for malicious input causing overflow in
  824. * the worst case where we need to allocate the entire
  825. * relocation tree as a single array.
  826. */
  827. if (exec[i].relocation_count > relocs_max - relocs_total)
  828. return -EINVAL;
  829. relocs_total += exec[i].relocation_count;
  830. length = exec[i].relocation_count *
  831. sizeof(struct drm_i915_gem_relocation_entry);
  832. /*
  833. * We must check that the entire relocation array is safe
  834. * to read, but since we may need to update the presumed
  835. * offsets during execution, check for full write access.
  836. */
  837. if (!access_ok(VERIFY_WRITE, ptr, length))
  838. return -EFAULT;
  839. if (likely(!i915.prefault_disable)) {
  840. if (fault_in_multipages_readable(ptr, length))
  841. return -EFAULT;
  842. }
  843. }
  844. return 0;
  845. }
  846. static struct intel_context *
  847. i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
  848. struct intel_engine_cs *ring, const u32 ctx_id)
  849. {
  850. struct intel_context *ctx = NULL;
  851. struct i915_ctx_hang_stats *hs;
  852. if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
  853. return ERR_PTR(-EINVAL);
  854. ctx = i915_gem_context_get(file->driver_priv, ctx_id);
  855. if (IS_ERR(ctx))
  856. return ctx;
  857. hs = &ctx->hang_stats;
  858. if (hs->banned) {
  859. DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
  860. return ERR_PTR(-EIO);
  861. }
  862. if (i915.enable_execlists && !ctx->engine[ring->id].state) {
  863. int ret = intel_lr_context_deferred_alloc(ctx, ring);
  864. if (ret) {
  865. DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret);
  866. return ERR_PTR(ret);
  867. }
  868. }
  869. return ctx;
  870. }
  871. void
  872. i915_gem_execbuffer_move_to_active(struct list_head *vmas,
  873. struct drm_i915_gem_request *req)
  874. {
  875. struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
  876. struct i915_vma *vma;
  877. list_for_each_entry(vma, vmas, exec_list) {
  878. struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
  879. struct drm_i915_gem_object *obj = vma->obj;
  880. u32 old_read = obj->base.read_domains;
  881. u32 old_write = obj->base.write_domain;
  882. obj->dirty = 1; /* be paranoid */
  883. obj->base.write_domain = obj->base.pending_write_domain;
  884. if (obj->base.write_domain == 0)
  885. obj->base.pending_read_domains |= obj->base.read_domains;
  886. obj->base.read_domains = obj->base.pending_read_domains;
  887. i915_vma_move_to_active(vma, req);
  888. if (obj->base.write_domain) {
  889. i915_gem_request_assign(&obj->last_write_req, req);
  890. intel_fb_obj_invalidate(obj, ORIGIN_CS);
  891. /* update for the implicit flush after a batch */
  892. obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
  893. }
  894. if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
  895. i915_gem_request_assign(&obj->last_fenced_req, req);
  896. if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
  897. struct drm_i915_private *dev_priv = to_i915(ring->dev);
  898. list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
  899. &dev_priv->mm.fence_list);
  900. }
  901. }
  902. trace_i915_gem_object_change_domain(obj, old_read, old_write);
  903. }
  904. }
  905. void
  906. i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
  907. {
  908. /* Unconditionally force add_request to emit a full flush. */
  909. params->ring->gpu_caches_dirty = true;
  910. /* Add a breadcrumb for the completion of the batch buffer */
  911. __i915_add_request(params->request, params->batch_obj, true);
  912. }
  913. static int
  914. i915_reset_gen7_sol_offsets(struct drm_device *dev,
  915. struct drm_i915_gem_request *req)
  916. {
  917. struct intel_engine_cs *ring = req->ring;
  918. struct drm_i915_private *dev_priv = dev->dev_private;
  919. int ret, i;
  920. if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
  921. DRM_DEBUG("sol reset is gen7/rcs only\n");
  922. return -EINVAL;
  923. }
  924. ret = intel_ring_begin(req, 4 * 3);
  925. if (ret)
  926. return ret;
  927. for (i = 0; i < 4; i++) {
  928. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  929. intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
  930. intel_ring_emit(ring, 0);
  931. }
  932. intel_ring_advance(ring);
  933. return 0;
  934. }
  935. static struct drm_i915_gem_object*
  936. i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
  937. struct drm_i915_gem_exec_object2 *shadow_exec_entry,
  938. struct eb_vmas *eb,
  939. struct drm_i915_gem_object *batch_obj,
  940. u32 batch_start_offset,
  941. u32 batch_len,
  942. bool is_master)
  943. {
  944. struct drm_i915_gem_object *shadow_batch_obj;
  945. struct i915_vma *vma;
  946. int ret;
  947. shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool,
  948. PAGE_ALIGN(batch_len));
  949. if (IS_ERR(shadow_batch_obj))
  950. return shadow_batch_obj;
  951. ret = i915_parse_cmds(ring,
  952. batch_obj,
  953. shadow_batch_obj,
  954. batch_start_offset,
  955. batch_len,
  956. is_master);
  957. if (ret)
  958. goto err;
  959. ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
  960. if (ret)
  961. goto err;
  962. i915_gem_object_unpin_pages(shadow_batch_obj);
  963. memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
  964. vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
  965. vma->exec_entry = shadow_exec_entry;
  966. vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
  967. drm_gem_object_reference(&shadow_batch_obj->base);
  968. list_add_tail(&vma->exec_list, &eb->vmas);
  969. shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
  970. return shadow_batch_obj;
  971. err:
  972. i915_gem_object_unpin_pages(shadow_batch_obj);
  973. if (ret == -EACCES) /* unhandled chained batch */
  974. return batch_obj;
  975. else
  976. return ERR_PTR(ret);
  977. }
  978. int
  979. i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
  980. struct drm_i915_gem_execbuffer2 *args,
  981. struct list_head *vmas)
  982. {
  983. struct drm_device *dev = params->dev;
  984. struct intel_engine_cs *ring = params->ring;
  985. struct drm_i915_private *dev_priv = dev->dev_private;
  986. u64 exec_start, exec_len;
  987. int instp_mode;
  988. u32 instp_mask;
  989. int ret;
  990. ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
  991. if (ret)
  992. return ret;
  993. ret = i915_switch_context(params->request);
  994. if (ret)
  995. return ret;
  996. WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
  997. "%s didn't clear reload\n", ring->name);
  998. instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
  999. instp_mask = I915_EXEC_CONSTANTS_MASK;
  1000. switch (instp_mode) {
  1001. case I915_EXEC_CONSTANTS_REL_GENERAL:
  1002. case I915_EXEC_CONSTANTS_ABSOLUTE:
  1003. case I915_EXEC_CONSTANTS_REL_SURFACE:
  1004. if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
  1005. DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
  1006. return -EINVAL;
  1007. }
  1008. if (instp_mode != dev_priv->relative_constants_mode) {
  1009. if (INTEL_INFO(dev)->gen < 4) {
  1010. DRM_DEBUG("no rel constants on pre-gen4\n");
  1011. return -EINVAL;
  1012. }
  1013. if (INTEL_INFO(dev)->gen > 5 &&
  1014. instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
  1015. DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
  1016. return -EINVAL;
  1017. }
  1018. /* The HW changed the meaning on this bit on gen6 */
  1019. if (INTEL_INFO(dev)->gen >= 6)
  1020. instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
  1021. }
  1022. break;
  1023. default:
  1024. DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
  1025. return -EINVAL;
  1026. }
  1027. if (ring == &dev_priv->ring[RCS] &&
  1028. instp_mode != dev_priv->relative_constants_mode) {
  1029. ret = intel_ring_begin(params->request, 4);
  1030. if (ret)
  1031. return ret;
  1032. intel_ring_emit(ring, MI_NOOP);
  1033. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  1034. intel_ring_emit(ring, INSTPM);
  1035. intel_ring_emit(ring, instp_mask << 16 | instp_mode);
  1036. intel_ring_advance(ring);
  1037. dev_priv->relative_constants_mode = instp_mode;
  1038. }
  1039. if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
  1040. ret = i915_reset_gen7_sol_offsets(dev, params->request);
  1041. if (ret)
  1042. return ret;
  1043. }
  1044. exec_len = args->batch_len;
  1045. exec_start = params->batch_obj_vm_offset +
  1046. params->args_batch_start_offset;
  1047. ret = ring->dispatch_execbuffer(params->request,
  1048. exec_start, exec_len,
  1049. params->dispatch_flags);
  1050. if (ret)
  1051. return ret;
  1052. trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
  1053. i915_gem_execbuffer_move_to_active(vmas, params->request);
  1054. i915_gem_execbuffer_retire_commands(params);
  1055. return 0;
  1056. }
  1057. /**
  1058. * Find one BSD ring to dispatch the corresponding BSD command.
  1059. * The Ring ID is returned.
  1060. */
  1061. static int gen8_dispatch_bsd_ring(struct drm_device *dev,
  1062. struct drm_file *file)
  1063. {
  1064. struct drm_i915_private *dev_priv = dev->dev_private;
  1065. struct drm_i915_file_private *file_priv = file->driver_priv;
  1066. /* Check whether the file_priv is using one ring */
  1067. if (file_priv->bsd_ring)
  1068. return file_priv->bsd_ring->id;
  1069. else {
  1070. /* If no, use the ping-pong mechanism to select one ring */
  1071. int ring_id;
  1072. mutex_lock(&dev->struct_mutex);
  1073. if (dev_priv->mm.bsd_ring_dispatch_index == 0) {
  1074. ring_id = VCS;
  1075. dev_priv->mm.bsd_ring_dispatch_index = 1;
  1076. } else {
  1077. ring_id = VCS2;
  1078. dev_priv->mm.bsd_ring_dispatch_index = 0;
  1079. }
  1080. file_priv->bsd_ring = &dev_priv->ring[ring_id];
  1081. mutex_unlock(&dev->struct_mutex);
  1082. return ring_id;
  1083. }
  1084. }
  1085. static struct drm_i915_gem_object *
  1086. eb_get_batch(struct eb_vmas *eb)
  1087. {
  1088. struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
  1089. /*
  1090. * SNA is doing fancy tricks with compressing batch buffers, which leads
  1091. * to negative relocation deltas. Usually that works out ok since the
  1092. * relocate address is still positive, except when the batch is placed
  1093. * very low in the GTT. Ensure this doesn't happen.
  1094. *
  1095. * Note that actual hangs have only been observed on gen7, but for
  1096. * paranoia do it everywhere.
  1097. */
  1098. vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
  1099. return vma->obj;
  1100. }
  1101. static int
  1102. i915_gem_do_execbuffer(struct drm_device *dev, void *data,
  1103. struct drm_file *file,
  1104. struct drm_i915_gem_execbuffer2 *args,
  1105. struct drm_i915_gem_exec_object2 *exec)
  1106. {
  1107. struct drm_i915_private *dev_priv = dev->dev_private;
  1108. struct eb_vmas *eb;
  1109. struct drm_i915_gem_object *batch_obj;
  1110. struct drm_i915_gem_exec_object2 shadow_exec_entry;
  1111. struct intel_engine_cs *ring;
  1112. struct intel_context *ctx;
  1113. struct i915_address_space *vm;
  1114. struct i915_execbuffer_params params_master; /* XXX: will be removed later */
  1115. struct i915_execbuffer_params *params = &params_master;
  1116. const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
  1117. u32 dispatch_flags;
  1118. int ret;
  1119. bool need_relocs;
  1120. if (!i915_gem_check_execbuffer(args))
  1121. return -EINVAL;
  1122. ret = validate_exec_list(dev, exec, args->buffer_count);
  1123. if (ret)
  1124. return ret;
  1125. dispatch_flags = 0;
  1126. if (args->flags & I915_EXEC_SECURE) {
  1127. if (!file->is_master || !capable(CAP_SYS_ADMIN))
  1128. return -EPERM;
  1129. dispatch_flags |= I915_DISPATCH_SECURE;
  1130. }
  1131. if (args->flags & I915_EXEC_IS_PINNED)
  1132. dispatch_flags |= I915_DISPATCH_PINNED;
  1133. if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
  1134. DRM_DEBUG("execbuf with unknown ring: %d\n",
  1135. (int)(args->flags & I915_EXEC_RING_MASK));
  1136. return -EINVAL;
  1137. }
  1138. if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
  1139. ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
  1140. DRM_DEBUG("execbuf with non bsd ring but with invalid "
  1141. "bsd dispatch flags: %d\n", (int)(args->flags));
  1142. return -EINVAL;
  1143. }
  1144. if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
  1145. ring = &dev_priv->ring[RCS];
  1146. else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
  1147. if (HAS_BSD2(dev)) {
  1148. int ring_id;
  1149. switch (args->flags & I915_EXEC_BSD_MASK) {
  1150. case I915_EXEC_BSD_DEFAULT:
  1151. ring_id = gen8_dispatch_bsd_ring(dev, file);
  1152. ring = &dev_priv->ring[ring_id];
  1153. break;
  1154. case I915_EXEC_BSD_RING1:
  1155. ring = &dev_priv->ring[VCS];
  1156. break;
  1157. case I915_EXEC_BSD_RING2:
  1158. ring = &dev_priv->ring[VCS2];
  1159. break;
  1160. default:
  1161. DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
  1162. (int)(args->flags & I915_EXEC_BSD_MASK));
  1163. return -EINVAL;
  1164. }
  1165. } else
  1166. ring = &dev_priv->ring[VCS];
  1167. } else
  1168. ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];
  1169. if (!intel_ring_initialized(ring)) {
  1170. DRM_DEBUG("execbuf with invalid ring: %d\n",
  1171. (int)(args->flags & I915_EXEC_RING_MASK));
  1172. return -EINVAL;
  1173. }
  1174. if (args->buffer_count < 1) {
  1175. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  1176. return -EINVAL;
  1177. }
  1178. if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
  1179. if (!HAS_RESOURCE_STREAMER(dev)) {
  1180. DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
  1181. return -EINVAL;
  1182. }
  1183. if (ring->id != RCS) {
  1184. DRM_DEBUG("RS is not available on %s\n",
  1185. ring->name);
  1186. return -EINVAL;
  1187. }
  1188. dispatch_flags |= I915_DISPATCH_RS;
  1189. }
  1190. intel_runtime_pm_get(dev_priv);
  1191. ret = i915_mutex_lock_interruptible(dev);
  1192. if (ret)
  1193. goto pre_mutex_err;
  1194. ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
  1195. if (IS_ERR(ctx)) {
  1196. mutex_unlock(&dev->struct_mutex);
  1197. ret = PTR_ERR(ctx);
  1198. goto pre_mutex_err;
  1199. }
  1200. i915_gem_context_reference(ctx);
  1201. if (ctx->ppgtt)
  1202. vm = &ctx->ppgtt->base;
  1203. else
  1204. vm = &dev_priv->gtt.base;
  1205. memset(&params_master, 0x00, sizeof(params_master));
  1206. eb = eb_create(args);
  1207. if (eb == NULL) {
  1208. i915_gem_context_unreference(ctx);
  1209. mutex_unlock(&dev->struct_mutex);
  1210. ret = -ENOMEM;
  1211. goto pre_mutex_err;
  1212. }
  1213. /* Look up object handles */
  1214. ret = eb_lookup_vmas(eb, exec, args, vm, file);
  1215. if (ret)
  1216. goto err;
  1217. /* take note of the batch buffer before we might reorder the lists */
  1218. batch_obj = eb_get_batch(eb);
  1219. /* Move the objects en-masse into the GTT, evicting if necessary. */
  1220. need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
  1221. ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs);
  1222. if (ret)
  1223. goto err;
  1224. /* The objects are in their final locations, apply the relocations. */
  1225. if (need_relocs)
  1226. ret = i915_gem_execbuffer_relocate(eb);
  1227. if (ret) {
  1228. if (ret == -EFAULT) {
  1229. ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
  1230. eb, exec, ctx);
  1231. BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  1232. }
  1233. if (ret)
  1234. goto err;
  1235. }
  1236. /* Set the pending read domains for the batch buffer to COMMAND */
  1237. if (batch_obj->base.pending_write_domain) {
  1238. DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
  1239. ret = -EINVAL;
  1240. goto err;
  1241. }
  1242. params->args_batch_start_offset = args->batch_start_offset;
  1243. if (i915_needs_cmd_parser(ring) && args->batch_len) {
  1244. struct drm_i915_gem_object *parsed_batch_obj;
  1245. parsed_batch_obj = i915_gem_execbuffer_parse(ring,
  1246. &shadow_exec_entry,
  1247. eb,
  1248. batch_obj,
  1249. args->batch_start_offset,
  1250. args->batch_len,
  1251. file->is_master);
  1252. if (IS_ERR(parsed_batch_obj)) {
  1253. ret = PTR_ERR(parsed_batch_obj);
  1254. goto err;
  1255. }
  1256. /*
  1257. * parsed_batch_obj == batch_obj means batch not fully parsed:
  1258. * Accept, but don't promote to secure.
  1259. */
  1260. if (parsed_batch_obj != batch_obj) {
  1261. /*
  1262. * Batch parsed and accepted:
  1263. *
  1264. * Set the DISPATCH_SECURE bit to remove the NON_SECURE
  1265. * bit from MI_BATCH_BUFFER_START commands issued in
  1266. * the dispatch_execbuffer implementations. We
  1267. * specifically don't want that set on batches the
  1268. * command parser has accepted.
  1269. */
  1270. dispatch_flags |= I915_DISPATCH_SECURE;
  1271. params->args_batch_start_offset = 0;
  1272. batch_obj = parsed_batch_obj;
  1273. }
  1274. }
  1275. batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
  1276. /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
  1277. * batch" bit. Hence we need to pin secure batches into the global gtt.
  1278. * hsw should have this fixed, but bdw mucks it up again. */
  1279. if (dispatch_flags & I915_DISPATCH_SECURE) {
  1280. /*
  1281. * So on first glance it looks freaky that we pin the batch here
  1282. * outside of the reservation loop. But:
  1283. * - The batch is already pinned into the relevant ppgtt, so we
  1284. * already have the backing storage fully allocated.
  1285. * - No other BO uses the global gtt (well contexts, but meh),
  1286. * so we don't really have issues with multiple objects not
  1287. * fitting due to fragmentation.
  1288. * So this is actually safe.
  1289. */
  1290. ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
  1291. if (ret)
  1292. goto err;
  1293. params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
  1294. } else
  1295. params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
  1296. /* Allocate a request for this batch buffer nice and early. */
  1297. ret = i915_gem_request_alloc(ring, ctx, &params->request);
  1298. if (ret)
  1299. goto err_batch_unpin;
  1300. ret = i915_gem_request_add_to_client(params->request, file);
  1301. if (ret)
  1302. goto err_batch_unpin;
  1303. /*
  1304. * Save assorted stuff away to pass through to *_submission().
  1305. * NB: This data should be 'persistent' and not local as it will
  1306. * kept around beyond the duration of the IOCTL once the GPU
  1307. * scheduler arrives.
  1308. */
  1309. params->dev = dev;
  1310. params->file = file;
  1311. params->ring = ring;
  1312. params->dispatch_flags = dispatch_flags;
  1313. params->batch_obj = batch_obj;
  1314. params->ctx = ctx;
  1315. ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
  1316. err_batch_unpin:
  1317. /*
  1318. * FIXME: We crucially rely upon the active tracking for the (ppgtt)
  1319. * batch vma for correctness. For less ugly and less fragility this
  1320. * needs to be adjusted to also track the ggtt batch vma properly as
  1321. * active.
  1322. */
  1323. if (dispatch_flags & I915_DISPATCH_SECURE)
  1324. i915_gem_object_ggtt_unpin(batch_obj);
  1325. err:
  1326. /* the request owns the ref now */
  1327. i915_gem_context_unreference(ctx);
  1328. eb_destroy(eb);
  1329. /*
  1330. * If the request was created but not successfully submitted then it
  1331. * must be freed again. If it was submitted then it is being tracked
  1332. * on the active request list and no clean up is required here.
  1333. */
  1334. if (ret && params->request)
  1335. i915_gem_request_cancel(params->request);
  1336. mutex_unlock(&dev->struct_mutex);
  1337. pre_mutex_err:
  1338. /* intel_gpu_busy should also get a ref, so it will free when the device
  1339. * is really idle. */
  1340. intel_runtime_pm_put(dev_priv);
  1341. return ret;
  1342. }
  1343. /*
  1344. * Legacy execbuffer just creates an exec2 list from the original exec object
  1345. * list array and passes it to the real function.
  1346. */
  1347. int
  1348. i915_gem_execbuffer(struct drm_device *dev, void *data,
  1349. struct drm_file *file)
  1350. {
  1351. struct drm_i915_gem_execbuffer *args = data;
  1352. struct drm_i915_gem_execbuffer2 exec2;
  1353. struct drm_i915_gem_exec_object *exec_list = NULL;
  1354. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  1355. int ret, i;
  1356. if (args->buffer_count < 1) {
  1357. DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
  1358. return -EINVAL;
  1359. }
  1360. /* Copy in the exec list from userland */
  1361. exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
  1362. exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
  1363. if (exec_list == NULL || exec2_list == NULL) {
  1364. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  1365. args->buffer_count);
  1366. drm_free_large(exec_list);
  1367. drm_free_large(exec2_list);
  1368. return -ENOMEM;
  1369. }
  1370. ret = copy_from_user(exec_list,
  1371. to_user_ptr(args->buffers_ptr),
  1372. sizeof(*exec_list) * args->buffer_count);
  1373. if (ret != 0) {
  1374. DRM_DEBUG("copy %d exec entries failed %d\n",
  1375. args->buffer_count, ret);
  1376. drm_free_large(exec_list);
  1377. drm_free_large(exec2_list);
  1378. return -EFAULT;
  1379. }
  1380. for (i = 0; i < args->buffer_count; i++) {
  1381. exec2_list[i].handle = exec_list[i].handle;
  1382. exec2_list[i].relocation_count = exec_list[i].relocation_count;
  1383. exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
  1384. exec2_list[i].alignment = exec_list[i].alignment;
  1385. exec2_list[i].offset = exec_list[i].offset;
  1386. if (INTEL_INFO(dev)->gen < 4)
  1387. exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
  1388. else
  1389. exec2_list[i].flags = 0;
  1390. }
  1391. exec2.buffers_ptr = args->buffers_ptr;
  1392. exec2.buffer_count = args->buffer_count;
  1393. exec2.batch_start_offset = args->batch_start_offset;
  1394. exec2.batch_len = args->batch_len;
  1395. exec2.DR1 = args->DR1;
  1396. exec2.DR4 = args->DR4;
  1397. exec2.num_cliprects = args->num_cliprects;
  1398. exec2.cliprects_ptr = args->cliprects_ptr;
  1399. exec2.flags = I915_EXEC_RENDER;
  1400. i915_execbuffer2_set_context_id(exec2, 0);
  1401. ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
  1402. if (!ret) {
  1403. struct drm_i915_gem_exec_object __user *user_exec_list =
  1404. to_user_ptr(args->buffers_ptr);
  1405. /* Copy the new buffer offsets back to the user's exec list. */
  1406. for (i = 0; i < args->buffer_count; i++) {
  1407. ret = __copy_to_user(&user_exec_list[i].offset,
  1408. &exec2_list[i].offset,
  1409. sizeof(user_exec_list[i].offset));
  1410. if (ret) {
  1411. ret = -EFAULT;
  1412. DRM_DEBUG("failed to copy %d exec entries "
  1413. "back to user (%d)\n",
  1414. args->buffer_count, ret);
  1415. break;
  1416. }
  1417. }
  1418. }
  1419. drm_free_large(exec_list);
  1420. drm_free_large(exec2_list);
  1421. return ret;
  1422. }
  1423. int
  1424. i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1425. struct drm_file *file)
  1426. {
  1427. struct drm_i915_gem_execbuffer2 *args = data;
  1428. struct drm_i915_gem_exec_object2 *exec2_list = NULL;
  1429. int ret;
  1430. if (args->buffer_count < 1 ||
  1431. args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
  1432. DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
  1433. return -EINVAL;
  1434. }
  1435. if (args->rsvd2 != 0) {
  1436. DRM_DEBUG("dirty rvsd2 field\n");
  1437. return -EINVAL;
  1438. }
  1439. exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
  1440. GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  1441. if (exec2_list == NULL)
  1442. exec2_list = drm_malloc_ab(sizeof(*exec2_list),
  1443. args->buffer_count);
  1444. if (exec2_list == NULL) {
  1445. DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
  1446. args->buffer_count);
  1447. return -ENOMEM;
  1448. }
  1449. ret = copy_from_user(exec2_list,
  1450. to_user_ptr(args->buffers_ptr),
  1451. sizeof(*exec2_list) * args->buffer_count);
  1452. if (ret != 0) {
  1453. DRM_DEBUG("copy %d exec entries failed %d\n",
  1454. args->buffer_count, ret);
  1455. drm_free_large(exec2_list);
  1456. return -EFAULT;
  1457. }
  1458. ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
  1459. if (!ret) {
  1460. /* Copy the new buffer offsets back to the user's exec list. */
  1461. struct drm_i915_gem_exec_object2 __user *user_exec_list =
  1462. to_user_ptr(args->buffers_ptr);
  1463. int i;
  1464. for (i = 0; i < args->buffer_count; i++) {
  1465. ret = __copy_to_user(&user_exec_list[i].offset,
  1466. &exec2_list[i].offset,
  1467. sizeof(user_exec_list[i].offset));
  1468. if (ret) {
  1469. ret = -EFAULT;
  1470. DRM_DEBUG("failed to copy %d exec entries "
  1471. "back to user\n",
  1472. args->buffer_count);
  1473. break;
  1474. }
  1475. }
  1476. }
  1477. drm_free_large(exec2_list);
  1478. return ret;
  1479. }