i915_gem_gtt.c 91 KB

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  1. /*
  2. * Copyright © 2010 Daniel Vetter
  3. * Copyright © 2011-2014 Intel Corporation
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22. * IN THE SOFTWARE.
  23. *
  24. */
  25. #include <linux/seq_file.h>
  26. #include <drm/drmP.h>
  27. #include <drm/i915_drm.h>
  28. #include "i915_drv.h"
  29. #include "i915_vgpu.h"
  30. #include "i915_trace.h"
  31. #include "intel_drv.h"
  32. /**
  33. * DOC: Global GTT views
  34. *
  35. * Background and previous state
  36. *
  37. * Historically objects could exists (be bound) in global GTT space only as
  38. * singular instances with a view representing all of the object's backing pages
  39. * in a linear fashion. This view will be called a normal view.
  40. *
  41. * To support multiple views of the same object, where the number of mapped
  42. * pages is not equal to the backing store, or where the layout of the pages
  43. * is not linear, concept of a GGTT view was added.
  44. *
  45. * One example of an alternative view is a stereo display driven by a single
  46. * image. In this case we would have a framebuffer looking like this
  47. * (2x2 pages):
  48. *
  49. * 12
  50. * 34
  51. *
  52. * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  53. * rendering. In contrast, fed to the display engine would be an alternative
  54. * view which could look something like this:
  55. *
  56. * 1212
  57. * 3434
  58. *
  59. * In this example both the size and layout of pages in the alternative view is
  60. * different from the normal view.
  61. *
  62. * Implementation and usage
  63. *
  64. * GGTT views are implemented using VMAs and are distinguished via enum
  65. * i915_ggtt_view_type and struct i915_ggtt_view.
  66. *
  67. * A new flavour of core GEM functions which work with GGTT bound objects were
  68. * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  69. * renaming in large amounts of code. They take the struct i915_ggtt_view
  70. * parameter encapsulating all metadata required to implement a view.
  71. *
  72. * As a helper for callers which are only interested in the normal view,
  73. * globally const i915_ggtt_view_normal singleton instance exists. All old core
  74. * GEM API functions, the ones not taking the view parameter, are operating on,
  75. * or with the normal GGTT view.
  76. *
  77. * Code wanting to add or use a new GGTT view needs to:
  78. *
  79. * 1. Add a new enum with a suitable name.
  80. * 2. Extend the metadata in the i915_ggtt_view structure if required.
  81. * 3. Add support to i915_get_vma_pages().
  82. *
  83. * New views are required to build a scatter-gather table from within the
  84. * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  85. * exists for the lifetime of an VMA.
  86. *
  87. * Core API is designed to have copy semantics which means that passed in
  88. * struct i915_ggtt_view does not need to be persistent (left around after
  89. * calling the core API functions).
  90. *
  91. */
  92. static int
  93. i915_get_ggtt_vma_pages(struct i915_vma *vma);
  94. const struct i915_ggtt_view i915_ggtt_view_normal;
  95. const struct i915_ggtt_view i915_ggtt_view_rotated = {
  96. .type = I915_GGTT_VIEW_ROTATED
  97. };
  98. static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
  99. {
  100. bool has_aliasing_ppgtt;
  101. bool has_full_ppgtt;
  102. has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
  103. has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
  104. if (intel_vgpu_active(dev))
  105. has_full_ppgtt = false; /* emulation is too hard */
  106. /*
  107. * We don't allow disabling PPGTT for gen9+ as it's a requirement for
  108. * execlists, the sole mechanism available to submit work.
  109. */
  110. if (INTEL_INFO(dev)->gen < 9 &&
  111. (enable_ppgtt == 0 || !has_aliasing_ppgtt))
  112. return 0;
  113. if (enable_ppgtt == 1)
  114. return 1;
  115. if (enable_ppgtt == 2 && has_full_ppgtt)
  116. return 2;
  117. #ifdef CONFIG_INTEL_IOMMU
  118. /* Disable ppgtt on SNB if VT-d is on. */
  119. if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
  120. DRM_INFO("Disabling PPGTT because VT-d is on\n");
  121. return 0;
  122. }
  123. #endif
  124. /* Early VLV doesn't have this */
  125. if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
  126. dev->pdev->revision < 0xb) {
  127. DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
  128. return 0;
  129. }
  130. if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
  131. return 2;
  132. else
  133. return has_aliasing_ppgtt ? 1 : 0;
  134. }
  135. static int ppgtt_bind_vma(struct i915_vma *vma,
  136. enum i915_cache_level cache_level,
  137. u32 unused)
  138. {
  139. u32 pte_flags = 0;
  140. /* Currently applicable only to VLV */
  141. if (vma->obj->gt_ro)
  142. pte_flags |= PTE_READ_ONLY;
  143. vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
  144. cache_level, pte_flags);
  145. return 0;
  146. }
  147. static void ppgtt_unbind_vma(struct i915_vma *vma)
  148. {
  149. vma->vm->clear_range(vma->vm,
  150. vma->node.start,
  151. vma->obj->base.size,
  152. true);
  153. }
  154. static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
  155. enum i915_cache_level level,
  156. bool valid)
  157. {
  158. gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  159. pte |= addr;
  160. switch (level) {
  161. case I915_CACHE_NONE:
  162. pte |= PPAT_UNCACHED_INDEX;
  163. break;
  164. case I915_CACHE_WT:
  165. pte |= PPAT_DISPLAY_ELLC_INDEX;
  166. break;
  167. default:
  168. pte |= PPAT_CACHED_INDEX;
  169. break;
  170. }
  171. return pte;
  172. }
  173. static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
  174. const enum i915_cache_level level)
  175. {
  176. gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
  177. pde |= addr;
  178. if (level != I915_CACHE_NONE)
  179. pde |= PPAT_CACHED_PDE_INDEX;
  180. else
  181. pde |= PPAT_UNCACHED_INDEX;
  182. return pde;
  183. }
  184. #define gen8_pdpe_encode gen8_pde_encode
  185. #define gen8_pml4e_encode gen8_pde_encode
  186. static gen6_pte_t snb_pte_encode(dma_addr_t addr,
  187. enum i915_cache_level level,
  188. bool valid, u32 unused)
  189. {
  190. gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  191. pte |= GEN6_PTE_ADDR_ENCODE(addr);
  192. switch (level) {
  193. case I915_CACHE_L3_LLC:
  194. case I915_CACHE_LLC:
  195. pte |= GEN6_PTE_CACHE_LLC;
  196. break;
  197. case I915_CACHE_NONE:
  198. pte |= GEN6_PTE_UNCACHED;
  199. break;
  200. default:
  201. MISSING_CASE(level);
  202. }
  203. return pte;
  204. }
  205. static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
  206. enum i915_cache_level level,
  207. bool valid, u32 unused)
  208. {
  209. gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  210. pte |= GEN6_PTE_ADDR_ENCODE(addr);
  211. switch (level) {
  212. case I915_CACHE_L3_LLC:
  213. pte |= GEN7_PTE_CACHE_L3_LLC;
  214. break;
  215. case I915_CACHE_LLC:
  216. pte |= GEN6_PTE_CACHE_LLC;
  217. break;
  218. case I915_CACHE_NONE:
  219. pte |= GEN6_PTE_UNCACHED;
  220. break;
  221. default:
  222. MISSING_CASE(level);
  223. }
  224. return pte;
  225. }
  226. static gen6_pte_t byt_pte_encode(dma_addr_t addr,
  227. enum i915_cache_level level,
  228. bool valid, u32 flags)
  229. {
  230. gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  231. pte |= GEN6_PTE_ADDR_ENCODE(addr);
  232. if (!(flags & PTE_READ_ONLY))
  233. pte |= BYT_PTE_WRITEABLE;
  234. if (level != I915_CACHE_NONE)
  235. pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
  236. return pte;
  237. }
  238. static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
  239. enum i915_cache_level level,
  240. bool valid, u32 unused)
  241. {
  242. gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  243. pte |= HSW_PTE_ADDR_ENCODE(addr);
  244. if (level != I915_CACHE_NONE)
  245. pte |= HSW_WB_LLC_AGE3;
  246. return pte;
  247. }
  248. static gen6_pte_t iris_pte_encode(dma_addr_t addr,
  249. enum i915_cache_level level,
  250. bool valid, u32 unused)
  251. {
  252. gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
  253. pte |= HSW_PTE_ADDR_ENCODE(addr);
  254. switch (level) {
  255. case I915_CACHE_NONE:
  256. break;
  257. case I915_CACHE_WT:
  258. pte |= HSW_WT_ELLC_LLC_AGE3;
  259. break;
  260. default:
  261. pte |= HSW_WB_ELLC_LLC_AGE3;
  262. break;
  263. }
  264. return pte;
  265. }
  266. static int __setup_page_dma(struct drm_device *dev,
  267. struct i915_page_dma *p, gfp_t flags)
  268. {
  269. struct device *device = &dev->pdev->dev;
  270. p->page = alloc_page(flags);
  271. if (!p->page)
  272. return -ENOMEM;
  273. p->daddr = dma_map_page(device,
  274. p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
  275. if (dma_mapping_error(device, p->daddr)) {
  276. __free_page(p->page);
  277. return -EINVAL;
  278. }
  279. return 0;
  280. }
  281. static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
  282. {
  283. return __setup_page_dma(dev, p, GFP_KERNEL);
  284. }
  285. static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
  286. {
  287. if (WARN_ON(!p->page))
  288. return;
  289. dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
  290. __free_page(p->page);
  291. memset(p, 0, sizeof(*p));
  292. }
  293. static void *kmap_page_dma(struct i915_page_dma *p)
  294. {
  295. return kmap_atomic(p->page);
  296. }
  297. /* We use the flushing unmap only with ppgtt structures:
  298. * page directories, page tables and scratch pages.
  299. */
  300. static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
  301. {
  302. /* There are only few exceptions for gen >=6. chv and bxt.
  303. * And we are not sure about the latter so play safe for now.
  304. */
  305. if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
  306. drm_clflush_virt_range(vaddr, PAGE_SIZE);
  307. kunmap_atomic(vaddr);
  308. }
  309. #define kmap_px(px) kmap_page_dma(px_base(px))
  310. #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
  311. #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
  312. #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
  313. #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
  314. #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
  315. static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
  316. const uint64_t val)
  317. {
  318. int i;
  319. uint64_t * const vaddr = kmap_page_dma(p);
  320. for (i = 0; i < 512; i++)
  321. vaddr[i] = val;
  322. kunmap_page_dma(dev, vaddr);
  323. }
  324. static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
  325. const uint32_t val32)
  326. {
  327. uint64_t v = val32;
  328. v = v << 32 | val32;
  329. fill_page_dma(dev, p, v);
  330. }
  331. static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
  332. {
  333. struct i915_page_scratch *sp;
  334. int ret;
  335. sp = kzalloc(sizeof(*sp), GFP_KERNEL);
  336. if (sp == NULL)
  337. return ERR_PTR(-ENOMEM);
  338. ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
  339. if (ret) {
  340. kfree(sp);
  341. return ERR_PTR(ret);
  342. }
  343. set_pages_uc(px_page(sp), 1);
  344. return sp;
  345. }
  346. static void free_scratch_page(struct drm_device *dev,
  347. struct i915_page_scratch *sp)
  348. {
  349. set_pages_wb(px_page(sp), 1);
  350. cleanup_px(dev, sp);
  351. kfree(sp);
  352. }
  353. static struct i915_page_table *alloc_pt(struct drm_device *dev)
  354. {
  355. struct i915_page_table *pt;
  356. const size_t count = INTEL_INFO(dev)->gen >= 8 ?
  357. GEN8_PTES : GEN6_PTES;
  358. int ret = -ENOMEM;
  359. pt = kzalloc(sizeof(*pt), GFP_KERNEL);
  360. if (!pt)
  361. return ERR_PTR(-ENOMEM);
  362. pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
  363. GFP_KERNEL);
  364. if (!pt->used_ptes)
  365. goto fail_bitmap;
  366. ret = setup_px(dev, pt);
  367. if (ret)
  368. goto fail_page_m;
  369. return pt;
  370. fail_page_m:
  371. kfree(pt->used_ptes);
  372. fail_bitmap:
  373. kfree(pt);
  374. return ERR_PTR(ret);
  375. }
  376. static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
  377. {
  378. cleanup_px(dev, pt);
  379. kfree(pt->used_ptes);
  380. kfree(pt);
  381. }
  382. static void gen8_initialize_pt(struct i915_address_space *vm,
  383. struct i915_page_table *pt)
  384. {
  385. gen8_pte_t scratch_pte;
  386. scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
  387. I915_CACHE_LLC, true);
  388. fill_px(vm->dev, pt, scratch_pte);
  389. }
  390. static void gen6_initialize_pt(struct i915_address_space *vm,
  391. struct i915_page_table *pt)
  392. {
  393. gen6_pte_t scratch_pte;
  394. WARN_ON(px_dma(vm->scratch_page) == 0);
  395. scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
  396. I915_CACHE_LLC, true, 0);
  397. fill32_px(vm->dev, pt, scratch_pte);
  398. }
  399. static struct i915_page_directory *alloc_pd(struct drm_device *dev)
  400. {
  401. struct i915_page_directory *pd;
  402. int ret = -ENOMEM;
  403. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  404. if (!pd)
  405. return ERR_PTR(-ENOMEM);
  406. pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
  407. sizeof(*pd->used_pdes), GFP_KERNEL);
  408. if (!pd->used_pdes)
  409. goto fail_bitmap;
  410. ret = setup_px(dev, pd);
  411. if (ret)
  412. goto fail_page_m;
  413. return pd;
  414. fail_page_m:
  415. kfree(pd->used_pdes);
  416. fail_bitmap:
  417. kfree(pd);
  418. return ERR_PTR(ret);
  419. }
  420. static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
  421. {
  422. if (px_page(pd)) {
  423. cleanup_px(dev, pd);
  424. kfree(pd->used_pdes);
  425. kfree(pd);
  426. }
  427. }
  428. static void gen8_initialize_pd(struct i915_address_space *vm,
  429. struct i915_page_directory *pd)
  430. {
  431. gen8_pde_t scratch_pde;
  432. scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
  433. fill_px(vm->dev, pd, scratch_pde);
  434. }
  435. static int __pdp_init(struct drm_device *dev,
  436. struct i915_page_directory_pointer *pdp)
  437. {
  438. size_t pdpes = I915_PDPES_PER_PDP(dev);
  439. pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
  440. sizeof(unsigned long),
  441. GFP_KERNEL);
  442. if (!pdp->used_pdpes)
  443. return -ENOMEM;
  444. pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
  445. GFP_KERNEL);
  446. if (!pdp->page_directory) {
  447. kfree(pdp->used_pdpes);
  448. /* the PDP might be the statically allocated top level. Keep it
  449. * as clean as possible */
  450. pdp->used_pdpes = NULL;
  451. return -ENOMEM;
  452. }
  453. return 0;
  454. }
  455. static void __pdp_fini(struct i915_page_directory_pointer *pdp)
  456. {
  457. kfree(pdp->used_pdpes);
  458. kfree(pdp->page_directory);
  459. pdp->page_directory = NULL;
  460. }
  461. static struct
  462. i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
  463. {
  464. struct i915_page_directory_pointer *pdp;
  465. int ret = -ENOMEM;
  466. WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
  467. pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
  468. if (!pdp)
  469. return ERR_PTR(-ENOMEM);
  470. ret = __pdp_init(dev, pdp);
  471. if (ret)
  472. goto fail_bitmap;
  473. ret = setup_px(dev, pdp);
  474. if (ret)
  475. goto fail_page_m;
  476. return pdp;
  477. fail_page_m:
  478. __pdp_fini(pdp);
  479. fail_bitmap:
  480. kfree(pdp);
  481. return ERR_PTR(ret);
  482. }
  483. static void free_pdp(struct drm_device *dev,
  484. struct i915_page_directory_pointer *pdp)
  485. {
  486. __pdp_fini(pdp);
  487. if (USES_FULL_48BIT_PPGTT(dev)) {
  488. cleanup_px(dev, pdp);
  489. kfree(pdp);
  490. }
  491. }
  492. static void gen8_initialize_pdp(struct i915_address_space *vm,
  493. struct i915_page_directory_pointer *pdp)
  494. {
  495. gen8_ppgtt_pdpe_t scratch_pdpe;
  496. scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
  497. fill_px(vm->dev, pdp, scratch_pdpe);
  498. }
  499. static void gen8_initialize_pml4(struct i915_address_space *vm,
  500. struct i915_pml4 *pml4)
  501. {
  502. gen8_ppgtt_pml4e_t scratch_pml4e;
  503. scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
  504. I915_CACHE_LLC);
  505. fill_px(vm->dev, pml4, scratch_pml4e);
  506. }
  507. static void
  508. gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
  509. struct i915_page_directory_pointer *pdp,
  510. struct i915_page_directory *pd,
  511. int index)
  512. {
  513. gen8_ppgtt_pdpe_t *page_directorypo;
  514. if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
  515. return;
  516. page_directorypo = kmap_px(pdp);
  517. page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
  518. kunmap_px(ppgtt, page_directorypo);
  519. }
  520. static void
  521. gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
  522. struct i915_pml4 *pml4,
  523. struct i915_page_directory_pointer *pdp,
  524. int index)
  525. {
  526. gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
  527. WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
  528. pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
  529. kunmap_px(ppgtt, pagemap);
  530. }
  531. /* Broadwell Page Directory Pointer Descriptors */
  532. static int gen8_write_pdp(struct drm_i915_gem_request *req,
  533. unsigned entry,
  534. dma_addr_t addr)
  535. {
  536. struct intel_engine_cs *ring = req->ring;
  537. int ret;
  538. BUG_ON(entry >= 4);
  539. ret = intel_ring_begin(req, 6);
  540. if (ret)
  541. return ret;
  542. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  543. intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
  544. intel_ring_emit(ring, upper_32_bits(addr));
  545. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  546. intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
  547. intel_ring_emit(ring, lower_32_bits(addr));
  548. intel_ring_advance(ring);
  549. return 0;
  550. }
  551. static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
  552. struct drm_i915_gem_request *req)
  553. {
  554. int i, ret;
  555. for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
  556. const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
  557. ret = gen8_write_pdp(req, i, pd_daddr);
  558. if (ret)
  559. return ret;
  560. }
  561. return 0;
  562. }
  563. static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
  564. struct drm_i915_gem_request *req)
  565. {
  566. return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
  567. }
  568. static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
  569. struct i915_page_directory_pointer *pdp,
  570. uint64_t start,
  571. uint64_t length,
  572. gen8_pte_t scratch_pte)
  573. {
  574. struct i915_hw_ppgtt *ppgtt =
  575. container_of(vm, struct i915_hw_ppgtt, base);
  576. gen8_pte_t *pt_vaddr;
  577. unsigned pdpe = gen8_pdpe_index(start);
  578. unsigned pde = gen8_pde_index(start);
  579. unsigned pte = gen8_pte_index(start);
  580. unsigned num_entries = length >> PAGE_SHIFT;
  581. unsigned last_pte, i;
  582. if (WARN_ON(!pdp))
  583. return;
  584. while (num_entries) {
  585. struct i915_page_directory *pd;
  586. struct i915_page_table *pt;
  587. if (WARN_ON(!pdp->page_directory[pdpe]))
  588. break;
  589. pd = pdp->page_directory[pdpe];
  590. if (WARN_ON(!pd->page_table[pde]))
  591. break;
  592. pt = pd->page_table[pde];
  593. if (WARN_ON(!px_page(pt)))
  594. break;
  595. last_pte = pte + num_entries;
  596. if (last_pte > GEN8_PTES)
  597. last_pte = GEN8_PTES;
  598. pt_vaddr = kmap_px(pt);
  599. for (i = pte; i < last_pte; i++) {
  600. pt_vaddr[i] = scratch_pte;
  601. num_entries--;
  602. }
  603. kunmap_px(ppgtt, pt);
  604. pte = 0;
  605. if (++pde == I915_PDES) {
  606. if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
  607. break;
  608. pde = 0;
  609. }
  610. }
  611. }
  612. static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
  613. uint64_t start,
  614. uint64_t length,
  615. bool use_scratch)
  616. {
  617. struct i915_hw_ppgtt *ppgtt =
  618. container_of(vm, struct i915_hw_ppgtt, base);
  619. gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
  620. I915_CACHE_LLC, use_scratch);
  621. if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
  622. gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
  623. scratch_pte);
  624. } else {
  625. uint64_t templ4, pml4e;
  626. struct i915_page_directory_pointer *pdp;
  627. gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
  628. gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
  629. scratch_pte);
  630. }
  631. }
  632. }
  633. static void
  634. gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
  635. struct i915_page_directory_pointer *pdp,
  636. struct sg_page_iter *sg_iter,
  637. uint64_t start,
  638. enum i915_cache_level cache_level)
  639. {
  640. struct i915_hw_ppgtt *ppgtt =
  641. container_of(vm, struct i915_hw_ppgtt, base);
  642. gen8_pte_t *pt_vaddr;
  643. unsigned pdpe = gen8_pdpe_index(start);
  644. unsigned pde = gen8_pde_index(start);
  645. unsigned pte = gen8_pte_index(start);
  646. pt_vaddr = NULL;
  647. while (__sg_page_iter_next(sg_iter)) {
  648. if (pt_vaddr == NULL) {
  649. struct i915_page_directory *pd = pdp->page_directory[pdpe];
  650. struct i915_page_table *pt = pd->page_table[pde];
  651. pt_vaddr = kmap_px(pt);
  652. }
  653. pt_vaddr[pte] =
  654. gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
  655. cache_level, true);
  656. if (++pte == GEN8_PTES) {
  657. kunmap_px(ppgtt, pt_vaddr);
  658. pt_vaddr = NULL;
  659. if (++pde == I915_PDES) {
  660. if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
  661. break;
  662. pde = 0;
  663. }
  664. pte = 0;
  665. }
  666. }
  667. if (pt_vaddr)
  668. kunmap_px(ppgtt, pt_vaddr);
  669. }
  670. static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
  671. struct sg_table *pages,
  672. uint64_t start,
  673. enum i915_cache_level cache_level,
  674. u32 unused)
  675. {
  676. struct i915_hw_ppgtt *ppgtt =
  677. container_of(vm, struct i915_hw_ppgtt, base);
  678. struct sg_page_iter sg_iter;
  679. __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
  680. if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
  681. gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
  682. cache_level);
  683. } else {
  684. struct i915_page_directory_pointer *pdp;
  685. uint64_t templ4, pml4e;
  686. uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
  687. gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
  688. gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
  689. start, cache_level);
  690. }
  691. }
  692. }
  693. static void gen8_free_page_tables(struct drm_device *dev,
  694. struct i915_page_directory *pd)
  695. {
  696. int i;
  697. if (!px_page(pd))
  698. return;
  699. for_each_set_bit(i, pd->used_pdes, I915_PDES) {
  700. if (WARN_ON(!pd->page_table[i]))
  701. continue;
  702. free_pt(dev, pd->page_table[i]);
  703. pd->page_table[i] = NULL;
  704. }
  705. }
  706. static int gen8_init_scratch(struct i915_address_space *vm)
  707. {
  708. struct drm_device *dev = vm->dev;
  709. vm->scratch_page = alloc_scratch_page(dev);
  710. if (IS_ERR(vm->scratch_page))
  711. return PTR_ERR(vm->scratch_page);
  712. vm->scratch_pt = alloc_pt(dev);
  713. if (IS_ERR(vm->scratch_pt)) {
  714. free_scratch_page(dev, vm->scratch_page);
  715. return PTR_ERR(vm->scratch_pt);
  716. }
  717. vm->scratch_pd = alloc_pd(dev);
  718. if (IS_ERR(vm->scratch_pd)) {
  719. free_pt(dev, vm->scratch_pt);
  720. free_scratch_page(dev, vm->scratch_page);
  721. return PTR_ERR(vm->scratch_pd);
  722. }
  723. if (USES_FULL_48BIT_PPGTT(dev)) {
  724. vm->scratch_pdp = alloc_pdp(dev);
  725. if (IS_ERR(vm->scratch_pdp)) {
  726. free_pd(dev, vm->scratch_pd);
  727. free_pt(dev, vm->scratch_pt);
  728. free_scratch_page(dev, vm->scratch_page);
  729. return PTR_ERR(vm->scratch_pdp);
  730. }
  731. }
  732. gen8_initialize_pt(vm, vm->scratch_pt);
  733. gen8_initialize_pd(vm, vm->scratch_pd);
  734. if (USES_FULL_48BIT_PPGTT(dev))
  735. gen8_initialize_pdp(vm, vm->scratch_pdp);
  736. return 0;
  737. }
  738. static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
  739. {
  740. enum vgt_g2v_type msg;
  741. struct drm_device *dev = ppgtt->base.dev;
  742. struct drm_i915_private *dev_priv = dev->dev_private;
  743. unsigned int offset = vgtif_reg(pdp0_lo);
  744. int i;
  745. if (USES_FULL_48BIT_PPGTT(dev)) {
  746. u64 daddr = px_dma(&ppgtt->pml4);
  747. I915_WRITE(offset, lower_32_bits(daddr));
  748. I915_WRITE(offset + 4, upper_32_bits(daddr));
  749. msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
  750. VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
  751. } else {
  752. for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
  753. u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
  754. I915_WRITE(offset, lower_32_bits(daddr));
  755. I915_WRITE(offset + 4, upper_32_bits(daddr));
  756. offset += 8;
  757. }
  758. msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
  759. VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
  760. }
  761. I915_WRITE(vgtif_reg(g2v_notify), msg);
  762. return 0;
  763. }
  764. static void gen8_free_scratch(struct i915_address_space *vm)
  765. {
  766. struct drm_device *dev = vm->dev;
  767. if (USES_FULL_48BIT_PPGTT(dev))
  768. free_pdp(dev, vm->scratch_pdp);
  769. free_pd(dev, vm->scratch_pd);
  770. free_pt(dev, vm->scratch_pt);
  771. free_scratch_page(dev, vm->scratch_page);
  772. }
  773. static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
  774. struct i915_page_directory_pointer *pdp)
  775. {
  776. int i;
  777. for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
  778. if (WARN_ON(!pdp->page_directory[i]))
  779. continue;
  780. gen8_free_page_tables(dev, pdp->page_directory[i]);
  781. free_pd(dev, pdp->page_directory[i]);
  782. }
  783. free_pdp(dev, pdp);
  784. }
  785. static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
  786. {
  787. int i;
  788. for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
  789. if (WARN_ON(!ppgtt->pml4.pdps[i]))
  790. continue;
  791. gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
  792. }
  793. cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
  794. }
  795. static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
  796. {
  797. struct i915_hw_ppgtt *ppgtt =
  798. container_of(vm, struct i915_hw_ppgtt, base);
  799. if (intel_vgpu_active(vm->dev))
  800. gen8_ppgtt_notify_vgt(ppgtt, false);
  801. if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
  802. gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
  803. else
  804. gen8_ppgtt_cleanup_4lvl(ppgtt);
  805. gen8_free_scratch(vm);
  806. }
  807. /**
  808. * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
  809. * @vm: Master vm structure.
  810. * @pd: Page directory for this address range.
  811. * @start: Starting virtual address to begin allocations.
  812. * @length: Size of the allocations.
  813. * @new_pts: Bitmap set by function with new allocations. Likely used by the
  814. * caller to free on error.
  815. *
  816. * Allocate the required number of page tables. Extremely similar to
  817. * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
  818. * the page directory boundary (instead of the page directory pointer). That
  819. * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
  820. * possible, and likely that the caller will need to use multiple calls of this
  821. * function to achieve the appropriate allocation.
  822. *
  823. * Return: 0 if success; negative error code otherwise.
  824. */
  825. static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
  826. struct i915_page_directory *pd,
  827. uint64_t start,
  828. uint64_t length,
  829. unsigned long *new_pts)
  830. {
  831. struct drm_device *dev = vm->dev;
  832. struct i915_page_table *pt;
  833. uint64_t temp;
  834. uint32_t pde;
  835. gen8_for_each_pde(pt, pd, start, length, temp, pde) {
  836. /* Don't reallocate page tables */
  837. if (test_bit(pde, pd->used_pdes)) {
  838. /* Scratch is never allocated this way */
  839. WARN_ON(pt == vm->scratch_pt);
  840. continue;
  841. }
  842. pt = alloc_pt(dev);
  843. if (IS_ERR(pt))
  844. goto unwind_out;
  845. gen8_initialize_pt(vm, pt);
  846. pd->page_table[pde] = pt;
  847. __set_bit(pde, new_pts);
  848. trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
  849. }
  850. return 0;
  851. unwind_out:
  852. for_each_set_bit(pde, new_pts, I915_PDES)
  853. free_pt(dev, pd->page_table[pde]);
  854. return -ENOMEM;
  855. }
  856. /**
  857. * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
  858. * @vm: Master vm structure.
  859. * @pdp: Page directory pointer for this address range.
  860. * @start: Starting virtual address to begin allocations.
  861. * @length: Size of the allocations.
  862. * @new_pds: Bitmap set by function with new allocations. Likely used by the
  863. * caller to free on error.
  864. *
  865. * Allocate the required number of page directories starting at the pde index of
  866. * @start, and ending at the pde index @start + @length. This function will skip
  867. * over already allocated page directories within the range, and only allocate
  868. * new ones, setting the appropriate pointer within the pdp as well as the
  869. * correct position in the bitmap @new_pds.
  870. *
  871. * The function will only allocate the pages within the range for a give page
  872. * directory pointer. In other words, if @start + @length straddles a virtually
  873. * addressed PDP boundary (512GB for 4k pages), there will be more allocations
  874. * required by the caller, This is not currently possible, and the BUG in the
  875. * code will prevent it.
  876. *
  877. * Return: 0 if success; negative error code otherwise.
  878. */
  879. static int
  880. gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
  881. struct i915_page_directory_pointer *pdp,
  882. uint64_t start,
  883. uint64_t length,
  884. unsigned long *new_pds)
  885. {
  886. struct drm_device *dev = vm->dev;
  887. struct i915_page_directory *pd;
  888. uint64_t temp;
  889. uint32_t pdpe;
  890. uint32_t pdpes = I915_PDPES_PER_PDP(dev);
  891. WARN_ON(!bitmap_empty(new_pds, pdpes));
  892. gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
  893. if (test_bit(pdpe, pdp->used_pdpes))
  894. continue;
  895. pd = alloc_pd(dev);
  896. if (IS_ERR(pd))
  897. goto unwind_out;
  898. gen8_initialize_pd(vm, pd);
  899. pdp->page_directory[pdpe] = pd;
  900. __set_bit(pdpe, new_pds);
  901. trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
  902. }
  903. return 0;
  904. unwind_out:
  905. for_each_set_bit(pdpe, new_pds, pdpes)
  906. free_pd(dev, pdp->page_directory[pdpe]);
  907. return -ENOMEM;
  908. }
  909. /**
  910. * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
  911. * @vm: Master vm structure.
  912. * @pml4: Page map level 4 for this address range.
  913. * @start: Starting virtual address to begin allocations.
  914. * @length: Size of the allocations.
  915. * @new_pdps: Bitmap set by function with new allocations. Likely used by the
  916. * caller to free on error.
  917. *
  918. * Allocate the required number of page directory pointers. Extremely similar to
  919. * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
  920. * The main difference is here we are limited by the pml4 boundary (instead of
  921. * the page directory pointer).
  922. *
  923. * Return: 0 if success; negative error code otherwise.
  924. */
  925. static int
  926. gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
  927. struct i915_pml4 *pml4,
  928. uint64_t start,
  929. uint64_t length,
  930. unsigned long *new_pdps)
  931. {
  932. struct drm_device *dev = vm->dev;
  933. struct i915_page_directory_pointer *pdp;
  934. uint64_t temp;
  935. uint32_t pml4e;
  936. WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
  937. gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
  938. if (!test_bit(pml4e, pml4->used_pml4es)) {
  939. pdp = alloc_pdp(dev);
  940. if (IS_ERR(pdp))
  941. goto unwind_out;
  942. gen8_initialize_pdp(vm, pdp);
  943. pml4->pdps[pml4e] = pdp;
  944. __set_bit(pml4e, new_pdps);
  945. trace_i915_page_directory_pointer_entry_alloc(vm,
  946. pml4e,
  947. start,
  948. GEN8_PML4E_SHIFT);
  949. }
  950. }
  951. return 0;
  952. unwind_out:
  953. for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
  954. free_pdp(dev, pml4->pdps[pml4e]);
  955. return -ENOMEM;
  956. }
  957. static void
  958. free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
  959. {
  960. kfree(new_pts);
  961. kfree(new_pds);
  962. }
  963. /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
  964. * of these are based on the number of PDPEs in the system.
  965. */
  966. static
  967. int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
  968. unsigned long **new_pts,
  969. uint32_t pdpes)
  970. {
  971. unsigned long *pds;
  972. unsigned long *pts;
  973. pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
  974. if (!pds)
  975. return -ENOMEM;
  976. pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
  977. GFP_TEMPORARY);
  978. if (!pts)
  979. goto err_out;
  980. *new_pds = pds;
  981. *new_pts = pts;
  982. return 0;
  983. err_out:
  984. free_gen8_temp_bitmaps(pds, pts);
  985. return -ENOMEM;
  986. }
  987. /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
  988. * the page table structures, we mark them dirty so that
  989. * context switching/execlist queuing code takes extra steps
  990. * to ensure that tlbs are flushed.
  991. */
  992. static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
  993. {
  994. ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
  995. }
  996. static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
  997. struct i915_page_directory_pointer *pdp,
  998. uint64_t start,
  999. uint64_t length)
  1000. {
  1001. struct i915_hw_ppgtt *ppgtt =
  1002. container_of(vm, struct i915_hw_ppgtt, base);
  1003. unsigned long *new_page_dirs, *new_page_tables;
  1004. struct drm_device *dev = vm->dev;
  1005. struct i915_page_directory *pd;
  1006. const uint64_t orig_start = start;
  1007. const uint64_t orig_length = length;
  1008. uint64_t temp;
  1009. uint32_t pdpe;
  1010. uint32_t pdpes = I915_PDPES_PER_PDP(dev);
  1011. int ret;
  1012. /* Wrap is never okay since we can only represent 48b, and we don't
  1013. * actually use the other side of the canonical address space.
  1014. */
  1015. if (WARN_ON(start + length < start))
  1016. return -ENODEV;
  1017. if (WARN_ON(start + length > vm->total))
  1018. return -ENODEV;
  1019. ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
  1020. if (ret)
  1021. return ret;
  1022. /* Do the allocations first so we can easily bail out */
  1023. ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
  1024. new_page_dirs);
  1025. if (ret) {
  1026. free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
  1027. return ret;
  1028. }
  1029. /* For every page directory referenced, allocate page tables */
  1030. gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
  1031. ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
  1032. new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
  1033. if (ret)
  1034. goto err_out;
  1035. }
  1036. start = orig_start;
  1037. length = orig_length;
  1038. /* Allocations have completed successfully, so set the bitmaps, and do
  1039. * the mappings. */
  1040. gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
  1041. gen8_pde_t *const page_directory = kmap_px(pd);
  1042. struct i915_page_table *pt;
  1043. uint64_t pd_len = length;
  1044. uint64_t pd_start = start;
  1045. uint32_t pde;
  1046. /* Every pd should be allocated, we just did that above. */
  1047. WARN_ON(!pd);
  1048. gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
  1049. /* Same reasoning as pd */
  1050. WARN_ON(!pt);
  1051. WARN_ON(!pd_len);
  1052. WARN_ON(!gen8_pte_count(pd_start, pd_len));
  1053. /* Set our used ptes within the page table */
  1054. bitmap_set(pt->used_ptes,
  1055. gen8_pte_index(pd_start),
  1056. gen8_pte_count(pd_start, pd_len));
  1057. /* Our pde is now pointing to the pagetable, pt */
  1058. __set_bit(pde, pd->used_pdes);
  1059. /* Map the PDE to the page table */
  1060. page_directory[pde] = gen8_pde_encode(px_dma(pt),
  1061. I915_CACHE_LLC);
  1062. trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
  1063. gen8_pte_index(start),
  1064. gen8_pte_count(start, length),
  1065. GEN8_PTES);
  1066. /* NB: We haven't yet mapped ptes to pages. At this
  1067. * point we're still relying on insert_entries() */
  1068. }
  1069. kunmap_px(ppgtt, page_directory);
  1070. __set_bit(pdpe, pdp->used_pdpes);
  1071. gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
  1072. }
  1073. free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
  1074. mark_tlbs_dirty(ppgtt);
  1075. return 0;
  1076. err_out:
  1077. while (pdpe--) {
  1078. for_each_set_bit(temp, new_page_tables + pdpe *
  1079. BITS_TO_LONGS(I915_PDES), I915_PDES)
  1080. free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
  1081. }
  1082. for_each_set_bit(pdpe, new_page_dirs, pdpes)
  1083. free_pd(dev, pdp->page_directory[pdpe]);
  1084. free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
  1085. mark_tlbs_dirty(ppgtt);
  1086. return ret;
  1087. }
  1088. static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
  1089. struct i915_pml4 *pml4,
  1090. uint64_t start,
  1091. uint64_t length)
  1092. {
  1093. DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
  1094. struct i915_hw_ppgtt *ppgtt =
  1095. container_of(vm, struct i915_hw_ppgtt, base);
  1096. struct i915_page_directory_pointer *pdp;
  1097. uint64_t temp, pml4e;
  1098. int ret = 0;
  1099. /* Do the pml4 allocations first, so we don't need to track the newly
  1100. * allocated tables below the pdp */
  1101. bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
  1102. /* The pagedirectory and pagetable allocations are done in the shared 3
  1103. * and 4 level code. Just allocate the pdps.
  1104. */
  1105. ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
  1106. new_pdps);
  1107. if (ret)
  1108. return ret;
  1109. WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
  1110. "The allocation has spanned more than 512GB. "
  1111. "It is highly likely this is incorrect.");
  1112. gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
  1113. WARN_ON(!pdp);
  1114. ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
  1115. if (ret)
  1116. goto err_out;
  1117. gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
  1118. }
  1119. bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
  1120. GEN8_PML4ES_PER_PML4);
  1121. return 0;
  1122. err_out:
  1123. for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
  1124. gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
  1125. return ret;
  1126. }
  1127. static int gen8_alloc_va_range(struct i915_address_space *vm,
  1128. uint64_t start, uint64_t length)
  1129. {
  1130. struct i915_hw_ppgtt *ppgtt =
  1131. container_of(vm, struct i915_hw_ppgtt, base);
  1132. if (USES_FULL_48BIT_PPGTT(vm->dev))
  1133. return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
  1134. else
  1135. return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
  1136. }
  1137. static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
  1138. uint64_t start, uint64_t length,
  1139. gen8_pte_t scratch_pte,
  1140. struct seq_file *m)
  1141. {
  1142. struct i915_page_directory *pd;
  1143. uint64_t temp;
  1144. uint32_t pdpe;
  1145. gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
  1146. struct i915_page_table *pt;
  1147. uint64_t pd_len = length;
  1148. uint64_t pd_start = start;
  1149. uint32_t pde;
  1150. if (!test_bit(pdpe, pdp->used_pdpes))
  1151. continue;
  1152. seq_printf(m, "\tPDPE #%d\n", pdpe);
  1153. gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
  1154. uint32_t pte;
  1155. gen8_pte_t *pt_vaddr;
  1156. if (!test_bit(pde, pd->used_pdes))
  1157. continue;
  1158. pt_vaddr = kmap_px(pt);
  1159. for (pte = 0; pte < GEN8_PTES; pte += 4) {
  1160. uint64_t va =
  1161. (pdpe << GEN8_PDPE_SHIFT) |
  1162. (pde << GEN8_PDE_SHIFT) |
  1163. (pte << GEN8_PTE_SHIFT);
  1164. int i;
  1165. bool found = false;
  1166. for (i = 0; i < 4; i++)
  1167. if (pt_vaddr[pte + i] != scratch_pte)
  1168. found = true;
  1169. if (!found)
  1170. continue;
  1171. seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
  1172. for (i = 0; i < 4; i++) {
  1173. if (pt_vaddr[pte + i] != scratch_pte)
  1174. seq_printf(m, " %llx", pt_vaddr[pte + i]);
  1175. else
  1176. seq_puts(m, " SCRATCH ");
  1177. }
  1178. seq_puts(m, "\n");
  1179. }
  1180. /* don't use kunmap_px, it could trigger
  1181. * an unnecessary flush.
  1182. */
  1183. kunmap_atomic(pt_vaddr);
  1184. }
  1185. }
  1186. }
  1187. static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
  1188. {
  1189. struct i915_address_space *vm = &ppgtt->base;
  1190. uint64_t start = ppgtt->base.start;
  1191. uint64_t length = ppgtt->base.total;
  1192. gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
  1193. I915_CACHE_LLC, true);
  1194. if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
  1195. gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
  1196. } else {
  1197. uint64_t templ4, pml4e;
  1198. struct i915_pml4 *pml4 = &ppgtt->pml4;
  1199. struct i915_page_directory_pointer *pdp;
  1200. gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
  1201. if (!test_bit(pml4e, pml4->used_pml4es))
  1202. continue;
  1203. seq_printf(m, " PML4E #%llu\n", pml4e);
  1204. gen8_dump_pdp(pdp, start, length, scratch_pte, m);
  1205. }
  1206. }
  1207. }
  1208. static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
  1209. {
  1210. unsigned long *new_page_dirs, *new_page_tables;
  1211. uint32_t pdpes = I915_PDPES_PER_PDP(dev);
  1212. int ret;
  1213. /* We allocate temp bitmap for page tables for no gain
  1214. * but as this is for init only, lets keep the things simple
  1215. */
  1216. ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
  1217. if (ret)
  1218. return ret;
  1219. /* Allocate for all pdps regardless of how the ppgtt
  1220. * was defined.
  1221. */
  1222. ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
  1223. 0, 1ULL << 32,
  1224. new_page_dirs);
  1225. if (!ret)
  1226. *ppgtt->pdp.used_pdpes = *new_page_dirs;
  1227. free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
  1228. return ret;
  1229. }
  1230. /*
  1231. * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
  1232. * with a net effect resembling a 2-level page table in normal x86 terms. Each
  1233. * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
  1234. * space.
  1235. *
  1236. */
  1237. static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
  1238. {
  1239. int ret;
  1240. ret = gen8_init_scratch(&ppgtt->base);
  1241. if (ret)
  1242. return ret;
  1243. ppgtt->base.start = 0;
  1244. ppgtt->base.cleanup = gen8_ppgtt_cleanup;
  1245. ppgtt->base.allocate_va_range = gen8_alloc_va_range;
  1246. ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
  1247. ppgtt->base.clear_range = gen8_ppgtt_clear_range;
  1248. ppgtt->base.unbind_vma = ppgtt_unbind_vma;
  1249. ppgtt->base.bind_vma = ppgtt_bind_vma;
  1250. ppgtt->debug_dump = gen8_dump_ppgtt;
  1251. if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
  1252. ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
  1253. if (ret)
  1254. goto free_scratch;
  1255. gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
  1256. ppgtt->base.total = 1ULL << 48;
  1257. ppgtt->switch_mm = gen8_48b_mm_switch;
  1258. } else {
  1259. ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
  1260. if (ret)
  1261. goto free_scratch;
  1262. ppgtt->base.total = 1ULL << 32;
  1263. ppgtt->switch_mm = gen8_legacy_mm_switch;
  1264. trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
  1265. 0, 0,
  1266. GEN8_PML4E_SHIFT);
  1267. if (intel_vgpu_active(ppgtt->base.dev)) {
  1268. ret = gen8_preallocate_top_level_pdps(ppgtt);
  1269. if (ret)
  1270. goto free_scratch;
  1271. }
  1272. }
  1273. if (intel_vgpu_active(ppgtt->base.dev))
  1274. gen8_ppgtt_notify_vgt(ppgtt, true);
  1275. return 0;
  1276. free_scratch:
  1277. gen8_free_scratch(&ppgtt->base);
  1278. return ret;
  1279. }
  1280. static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
  1281. {
  1282. struct i915_address_space *vm = &ppgtt->base;
  1283. struct i915_page_table *unused;
  1284. gen6_pte_t scratch_pte;
  1285. uint32_t pd_entry;
  1286. uint32_t pte, pde, temp;
  1287. uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
  1288. scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
  1289. I915_CACHE_LLC, true, 0);
  1290. gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
  1291. u32 expected;
  1292. gen6_pte_t *pt_vaddr;
  1293. const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
  1294. pd_entry = readl(ppgtt->pd_addr + pde);
  1295. expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
  1296. if (pd_entry != expected)
  1297. seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
  1298. pde,
  1299. pd_entry,
  1300. expected);
  1301. seq_printf(m, "\tPDE: %x\n", pd_entry);
  1302. pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
  1303. for (pte = 0; pte < GEN6_PTES; pte+=4) {
  1304. unsigned long va =
  1305. (pde * PAGE_SIZE * GEN6_PTES) +
  1306. (pte * PAGE_SIZE);
  1307. int i;
  1308. bool found = false;
  1309. for (i = 0; i < 4; i++)
  1310. if (pt_vaddr[pte + i] != scratch_pte)
  1311. found = true;
  1312. if (!found)
  1313. continue;
  1314. seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
  1315. for (i = 0; i < 4; i++) {
  1316. if (pt_vaddr[pte + i] != scratch_pte)
  1317. seq_printf(m, " %08x", pt_vaddr[pte + i]);
  1318. else
  1319. seq_puts(m, " SCRATCH ");
  1320. }
  1321. seq_puts(m, "\n");
  1322. }
  1323. kunmap_px(ppgtt, pt_vaddr);
  1324. }
  1325. }
  1326. /* Write pde (index) from the page directory @pd to the page table @pt */
  1327. static void gen6_write_pde(struct i915_page_directory *pd,
  1328. const int pde, struct i915_page_table *pt)
  1329. {
  1330. /* Caller needs to make sure the write completes if necessary */
  1331. struct i915_hw_ppgtt *ppgtt =
  1332. container_of(pd, struct i915_hw_ppgtt, pd);
  1333. u32 pd_entry;
  1334. pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
  1335. pd_entry |= GEN6_PDE_VALID;
  1336. writel(pd_entry, ppgtt->pd_addr + pde);
  1337. }
  1338. /* Write all the page tables found in the ppgtt structure to incrementing page
  1339. * directories. */
  1340. static void gen6_write_page_range(struct drm_i915_private *dev_priv,
  1341. struct i915_page_directory *pd,
  1342. uint32_t start, uint32_t length)
  1343. {
  1344. struct i915_page_table *pt;
  1345. uint32_t pde, temp;
  1346. gen6_for_each_pde(pt, pd, start, length, temp, pde)
  1347. gen6_write_pde(pd, pde, pt);
  1348. /* Make sure write is complete before other code can use this page
  1349. * table. Also require for WC mapped PTEs */
  1350. readl(dev_priv->gtt.gsm);
  1351. }
  1352. static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
  1353. {
  1354. BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
  1355. return (ppgtt->pd.base.ggtt_offset / 64) << 16;
  1356. }
  1357. static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
  1358. struct drm_i915_gem_request *req)
  1359. {
  1360. struct intel_engine_cs *ring = req->ring;
  1361. int ret;
  1362. /* NB: TLBs must be flushed and invalidated before a switch */
  1363. ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
  1364. if (ret)
  1365. return ret;
  1366. ret = intel_ring_begin(req, 6);
  1367. if (ret)
  1368. return ret;
  1369. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
  1370. intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
  1371. intel_ring_emit(ring, PP_DIR_DCLV_2G);
  1372. intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
  1373. intel_ring_emit(ring, get_pd_offset(ppgtt));
  1374. intel_ring_emit(ring, MI_NOOP);
  1375. intel_ring_advance(ring);
  1376. return 0;
  1377. }
  1378. static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
  1379. struct drm_i915_gem_request *req)
  1380. {
  1381. struct intel_engine_cs *ring = req->ring;
  1382. struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
  1383. I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
  1384. I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
  1385. return 0;
  1386. }
  1387. static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
  1388. struct drm_i915_gem_request *req)
  1389. {
  1390. struct intel_engine_cs *ring = req->ring;
  1391. int ret;
  1392. /* NB: TLBs must be flushed and invalidated before a switch */
  1393. ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
  1394. if (ret)
  1395. return ret;
  1396. ret = intel_ring_begin(req, 6);
  1397. if (ret)
  1398. return ret;
  1399. intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
  1400. intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
  1401. intel_ring_emit(ring, PP_DIR_DCLV_2G);
  1402. intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
  1403. intel_ring_emit(ring, get_pd_offset(ppgtt));
  1404. intel_ring_emit(ring, MI_NOOP);
  1405. intel_ring_advance(ring);
  1406. /* XXX: RCS is the only one to auto invalidate the TLBs? */
  1407. if (ring->id != RCS) {
  1408. ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
  1409. if (ret)
  1410. return ret;
  1411. }
  1412. return 0;
  1413. }
  1414. static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
  1415. struct drm_i915_gem_request *req)
  1416. {
  1417. struct intel_engine_cs *ring = req->ring;
  1418. struct drm_device *dev = ppgtt->base.dev;
  1419. struct drm_i915_private *dev_priv = dev->dev_private;
  1420. I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
  1421. I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
  1422. POSTING_READ(RING_PP_DIR_DCLV(ring));
  1423. return 0;
  1424. }
  1425. static void gen8_ppgtt_enable(struct drm_device *dev)
  1426. {
  1427. struct drm_i915_private *dev_priv = dev->dev_private;
  1428. struct intel_engine_cs *ring;
  1429. int j;
  1430. for_each_ring(ring, dev_priv, j) {
  1431. u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
  1432. I915_WRITE(RING_MODE_GEN7(ring),
  1433. _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
  1434. }
  1435. }
  1436. static void gen7_ppgtt_enable(struct drm_device *dev)
  1437. {
  1438. struct drm_i915_private *dev_priv = dev->dev_private;
  1439. struct intel_engine_cs *ring;
  1440. uint32_t ecochk, ecobits;
  1441. int i;
  1442. ecobits = I915_READ(GAC_ECO_BITS);
  1443. I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
  1444. ecochk = I915_READ(GAM_ECOCHK);
  1445. if (IS_HASWELL(dev)) {
  1446. ecochk |= ECOCHK_PPGTT_WB_HSW;
  1447. } else {
  1448. ecochk |= ECOCHK_PPGTT_LLC_IVB;
  1449. ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
  1450. }
  1451. I915_WRITE(GAM_ECOCHK, ecochk);
  1452. for_each_ring(ring, dev_priv, i) {
  1453. /* GFX_MODE is per-ring on gen7+ */
  1454. I915_WRITE(RING_MODE_GEN7(ring),
  1455. _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
  1456. }
  1457. }
  1458. static void gen6_ppgtt_enable(struct drm_device *dev)
  1459. {
  1460. struct drm_i915_private *dev_priv = dev->dev_private;
  1461. uint32_t ecochk, gab_ctl, ecobits;
  1462. ecobits = I915_READ(GAC_ECO_BITS);
  1463. I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
  1464. ECOBITS_PPGTT_CACHE64B);
  1465. gab_ctl = I915_READ(GAB_CTL);
  1466. I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
  1467. ecochk = I915_READ(GAM_ECOCHK);
  1468. I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
  1469. I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
  1470. }
  1471. /* PPGTT support for Sandybdrige/Gen6 and later */
  1472. static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
  1473. uint64_t start,
  1474. uint64_t length,
  1475. bool use_scratch)
  1476. {
  1477. struct i915_hw_ppgtt *ppgtt =
  1478. container_of(vm, struct i915_hw_ppgtt, base);
  1479. gen6_pte_t *pt_vaddr, scratch_pte;
  1480. unsigned first_entry = start >> PAGE_SHIFT;
  1481. unsigned num_entries = length >> PAGE_SHIFT;
  1482. unsigned act_pt = first_entry / GEN6_PTES;
  1483. unsigned first_pte = first_entry % GEN6_PTES;
  1484. unsigned last_pte, i;
  1485. scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
  1486. I915_CACHE_LLC, true, 0);
  1487. while (num_entries) {
  1488. last_pte = first_pte + num_entries;
  1489. if (last_pte > GEN6_PTES)
  1490. last_pte = GEN6_PTES;
  1491. pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
  1492. for (i = first_pte; i < last_pte; i++)
  1493. pt_vaddr[i] = scratch_pte;
  1494. kunmap_px(ppgtt, pt_vaddr);
  1495. num_entries -= last_pte - first_pte;
  1496. first_pte = 0;
  1497. act_pt++;
  1498. }
  1499. }
  1500. static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
  1501. struct sg_table *pages,
  1502. uint64_t start,
  1503. enum i915_cache_level cache_level, u32 flags)
  1504. {
  1505. struct i915_hw_ppgtt *ppgtt =
  1506. container_of(vm, struct i915_hw_ppgtt, base);
  1507. gen6_pte_t *pt_vaddr;
  1508. unsigned first_entry = start >> PAGE_SHIFT;
  1509. unsigned act_pt = first_entry / GEN6_PTES;
  1510. unsigned act_pte = first_entry % GEN6_PTES;
  1511. struct sg_page_iter sg_iter;
  1512. pt_vaddr = NULL;
  1513. for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
  1514. if (pt_vaddr == NULL)
  1515. pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
  1516. pt_vaddr[act_pte] =
  1517. vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
  1518. cache_level, true, flags);
  1519. if (++act_pte == GEN6_PTES) {
  1520. kunmap_px(ppgtt, pt_vaddr);
  1521. pt_vaddr = NULL;
  1522. act_pt++;
  1523. act_pte = 0;
  1524. }
  1525. }
  1526. if (pt_vaddr)
  1527. kunmap_px(ppgtt, pt_vaddr);
  1528. }
  1529. static int gen6_alloc_va_range(struct i915_address_space *vm,
  1530. uint64_t start_in, uint64_t length_in)
  1531. {
  1532. DECLARE_BITMAP(new_page_tables, I915_PDES);
  1533. struct drm_device *dev = vm->dev;
  1534. struct drm_i915_private *dev_priv = dev->dev_private;
  1535. struct i915_hw_ppgtt *ppgtt =
  1536. container_of(vm, struct i915_hw_ppgtt, base);
  1537. struct i915_page_table *pt;
  1538. uint32_t start, length, start_save, length_save;
  1539. uint32_t pde, temp;
  1540. int ret;
  1541. if (WARN_ON(start_in + length_in > ppgtt->base.total))
  1542. return -ENODEV;
  1543. start = start_save = start_in;
  1544. length = length_save = length_in;
  1545. bitmap_zero(new_page_tables, I915_PDES);
  1546. /* The allocation is done in two stages so that we can bail out with
  1547. * minimal amount of pain. The first stage finds new page tables that
  1548. * need allocation. The second stage marks use ptes within the page
  1549. * tables.
  1550. */
  1551. gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
  1552. if (pt != vm->scratch_pt) {
  1553. WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
  1554. continue;
  1555. }
  1556. /* We've already allocated a page table */
  1557. WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
  1558. pt = alloc_pt(dev);
  1559. if (IS_ERR(pt)) {
  1560. ret = PTR_ERR(pt);
  1561. goto unwind_out;
  1562. }
  1563. gen6_initialize_pt(vm, pt);
  1564. ppgtt->pd.page_table[pde] = pt;
  1565. __set_bit(pde, new_page_tables);
  1566. trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
  1567. }
  1568. start = start_save;
  1569. length = length_save;
  1570. gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
  1571. DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
  1572. bitmap_zero(tmp_bitmap, GEN6_PTES);
  1573. bitmap_set(tmp_bitmap, gen6_pte_index(start),
  1574. gen6_pte_count(start, length));
  1575. if (__test_and_clear_bit(pde, new_page_tables))
  1576. gen6_write_pde(&ppgtt->pd, pde, pt);
  1577. trace_i915_page_table_entry_map(vm, pde, pt,
  1578. gen6_pte_index(start),
  1579. gen6_pte_count(start, length),
  1580. GEN6_PTES);
  1581. bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
  1582. GEN6_PTES);
  1583. }
  1584. WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
  1585. /* Make sure write is complete before other code can use this page
  1586. * table. Also require for WC mapped PTEs */
  1587. readl(dev_priv->gtt.gsm);
  1588. mark_tlbs_dirty(ppgtt);
  1589. return 0;
  1590. unwind_out:
  1591. for_each_set_bit(pde, new_page_tables, I915_PDES) {
  1592. struct i915_page_table *pt = ppgtt->pd.page_table[pde];
  1593. ppgtt->pd.page_table[pde] = vm->scratch_pt;
  1594. free_pt(vm->dev, pt);
  1595. }
  1596. mark_tlbs_dirty(ppgtt);
  1597. return ret;
  1598. }
  1599. static int gen6_init_scratch(struct i915_address_space *vm)
  1600. {
  1601. struct drm_device *dev = vm->dev;
  1602. vm->scratch_page = alloc_scratch_page(dev);
  1603. if (IS_ERR(vm->scratch_page))
  1604. return PTR_ERR(vm->scratch_page);
  1605. vm->scratch_pt = alloc_pt(dev);
  1606. if (IS_ERR(vm->scratch_pt)) {
  1607. free_scratch_page(dev, vm->scratch_page);
  1608. return PTR_ERR(vm->scratch_pt);
  1609. }
  1610. gen6_initialize_pt(vm, vm->scratch_pt);
  1611. return 0;
  1612. }
  1613. static void gen6_free_scratch(struct i915_address_space *vm)
  1614. {
  1615. struct drm_device *dev = vm->dev;
  1616. free_pt(dev, vm->scratch_pt);
  1617. free_scratch_page(dev, vm->scratch_page);
  1618. }
  1619. static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
  1620. {
  1621. struct i915_hw_ppgtt *ppgtt =
  1622. container_of(vm, struct i915_hw_ppgtt, base);
  1623. struct i915_page_table *pt;
  1624. uint32_t pde;
  1625. drm_mm_remove_node(&ppgtt->node);
  1626. gen6_for_all_pdes(pt, ppgtt, pde) {
  1627. if (pt != vm->scratch_pt)
  1628. free_pt(ppgtt->base.dev, pt);
  1629. }
  1630. gen6_free_scratch(vm);
  1631. }
  1632. static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
  1633. {
  1634. struct i915_address_space *vm = &ppgtt->base;
  1635. struct drm_device *dev = ppgtt->base.dev;
  1636. struct drm_i915_private *dev_priv = dev->dev_private;
  1637. bool retried = false;
  1638. int ret;
  1639. /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
  1640. * allocator works in address space sizes, so it's multiplied by page
  1641. * size. We allocate at the top of the GTT to avoid fragmentation.
  1642. */
  1643. BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
  1644. ret = gen6_init_scratch(vm);
  1645. if (ret)
  1646. return ret;
  1647. alloc:
  1648. ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
  1649. &ppgtt->node, GEN6_PD_SIZE,
  1650. GEN6_PD_ALIGN, 0,
  1651. 0, dev_priv->gtt.base.total,
  1652. DRM_MM_TOPDOWN);
  1653. if (ret == -ENOSPC && !retried) {
  1654. ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
  1655. GEN6_PD_SIZE, GEN6_PD_ALIGN,
  1656. I915_CACHE_NONE,
  1657. 0, dev_priv->gtt.base.total,
  1658. 0);
  1659. if (ret)
  1660. goto err_out;
  1661. retried = true;
  1662. goto alloc;
  1663. }
  1664. if (ret)
  1665. goto err_out;
  1666. if (ppgtt->node.start < dev_priv->gtt.mappable_end)
  1667. DRM_DEBUG("Forced to use aperture for PDEs\n");
  1668. return 0;
  1669. err_out:
  1670. gen6_free_scratch(vm);
  1671. return ret;
  1672. }
  1673. static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
  1674. {
  1675. return gen6_ppgtt_allocate_page_directories(ppgtt);
  1676. }
  1677. static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
  1678. uint64_t start, uint64_t length)
  1679. {
  1680. struct i915_page_table *unused;
  1681. uint32_t pde, temp;
  1682. gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
  1683. ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
  1684. }
  1685. static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
  1686. {
  1687. struct drm_device *dev = ppgtt->base.dev;
  1688. struct drm_i915_private *dev_priv = dev->dev_private;
  1689. int ret;
  1690. ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
  1691. if (IS_GEN6(dev)) {
  1692. ppgtt->switch_mm = gen6_mm_switch;
  1693. } else if (IS_HASWELL(dev)) {
  1694. ppgtt->switch_mm = hsw_mm_switch;
  1695. } else if (IS_GEN7(dev)) {
  1696. ppgtt->switch_mm = gen7_mm_switch;
  1697. } else
  1698. BUG();
  1699. if (intel_vgpu_active(dev))
  1700. ppgtt->switch_mm = vgpu_mm_switch;
  1701. ret = gen6_ppgtt_alloc(ppgtt);
  1702. if (ret)
  1703. return ret;
  1704. ppgtt->base.allocate_va_range = gen6_alloc_va_range;
  1705. ppgtt->base.clear_range = gen6_ppgtt_clear_range;
  1706. ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
  1707. ppgtt->base.unbind_vma = ppgtt_unbind_vma;
  1708. ppgtt->base.bind_vma = ppgtt_bind_vma;
  1709. ppgtt->base.cleanup = gen6_ppgtt_cleanup;
  1710. ppgtt->base.start = 0;
  1711. ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
  1712. ppgtt->debug_dump = gen6_dump_ppgtt;
  1713. ppgtt->pd.base.ggtt_offset =
  1714. ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
  1715. ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
  1716. ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
  1717. gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
  1718. gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
  1719. DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
  1720. ppgtt->node.size >> 20,
  1721. ppgtt->node.start / PAGE_SIZE);
  1722. DRM_DEBUG("Adding PPGTT at offset %x\n",
  1723. ppgtt->pd.base.ggtt_offset << 10);
  1724. return 0;
  1725. }
  1726. static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
  1727. {
  1728. ppgtt->base.dev = dev;
  1729. if (INTEL_INFO(dev)->gen < 8)
  1730. return gen6_ppgtt_init(ppgtt);
  1731. else
  1732. return gen8_ppgtt_init(ppgtt);
  1733. }
  1734. static void i915_address_space_init(struct i915_address_space *vm,
  1735. struct drm_i915_private *dev_priv)
  1736. {
  1737. drm_mm_init(&vm->mm, vm->start, vm->total);
  1738. vm->dev = dev_priv->dev;
  1739. INIT_LIST_HEAD(&vm->active_list);
  1740. INIT_LIST_HEAD(&vm->inactive_list);
  1741. list_add_tail(&vm->global_link, &dev_priv->vm_list);
  1742. }
  1743. int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
  1744. {
  1745. struct drm_i915_private *dev_priv = dev->dev_private;
  1746. int ret = 0;
  1747. ret = __hw_ppgtt_init(dev, ppgtt);
  1748. if (ret == 0) {
  1749. kref_init(&ppgtt->ref);
  1750. i915_address_space_init(&ppgtt->base, dev_priv);
  1751. }
  1752. return ret;
  1753. }
  1754. int i915_ppgtt_init_hw(struct drm_device *dev)
  1755. {
  1756. /* In the case of execlists, PPGTT is enabled by the context descriptor
  1757. * and the PDPs are contained within the context itself. We don't
  1758. * need to do anything here. */
  1759. if (i915.enable_execlists)
  1760. return 0;
  1761. if (!USES_PPGTT(dev))
  1762. return 0;
  1763. if (IS_GEN6(dev))
  1764. gen6_ppgtt_enable(dev);
  1765. else if (IS_GEN7(dev))
  1766. gen7_ppgtt_enable(dev);
  1767. else if (INTEL_INFO(dev)->gen >= 8)
  1768. gen8_ppgtt_enable(dev);
  1769. else
  1770. MISSING_CASE(INTEL_INFO(dev)->gen);
  1771. return 0;
  1772. }
  1773. int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
  1774. {
  1775. struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
  1776. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1777. if (i915.enable_execlists)
  1778. return 0;
  1779. if (!ppgtt)
  1780. return 0;
  1781. return ppgtt->switch_mm(ppgtt, req);
  1782. }
  1783. struct i915_hw_ppgtt *
  1784. i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
  1785. {
  1786. struct i915_hw_ppgtt *ppgtt;
  1787. int ret;
  1788. ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
  1789. if (!ppgtt)
  1790. return ERR_PTR(-ENOMEM);
  1791. ret = i915_ppgtt_init(dev, ppgtt);
  1792. if (ret) {
  1793. kfree(ppgtt);
  1794. return ERR_PTR(ret);
  1795. }
  1796. ppgtt->file_priv = fpriv;
  1797. trace_i915_ppgtt_create(&ppgtt->base);
  1798. return ppgtt;
  1799. }
  1800. void i915_ppgtt_release(struct kref *kref)
  1801. {
  1802. struct i915_hw_ppgtt *ppgtt =
  1803. container_of(kref, struct i915_hw_ppgtt, ref);
  1804. trace_i915_ppgtt_release(&ppgtt->base);
  1805. /* vmas should already be unbound */
  1806. WARN_ON(!list_empty(&ppgtt->base.active_list));
  1807. WARN_ON(!list_empty(&ppgtt->base.inactive_list));
  1808. list_del(&ppgtt->base.global_link);
  1809. drm_mm_takedown(&ppgtt->base.mm);
  1810. ppgtt->base.cleanup(&ppgtt->base);
  1811. kfree(ppgtt);
  1812. }
  1813. extern int intel_iommu_gfx_mapped;
  1814. /* Certain Gen5 chipsets require require idling the GPU before
  1815. * unmapping anything from the GTT when VT-d is enabled.
  1816. */
  1817. static bool needs_idle_maps(struct drm_device *dev)
  1818. {
  1819. #ifdef CONFIG_INTEL_IOMMU
  1820. /* Query intel_iommu to see if we need the workaround. Presumably that
  1821. * was loaded first.
  1822. */
  1823. if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
  1824. return true;
  1825. #endif
  1826. return false;
  1827. }
  1828. static bool do_idling(struct drm_i915_private *dev_priv)
  1829. {
  1830. bool ret = dev_priv->mm.interruptible;
  1831. if (unlikely(dev_priv->gtt.do_idle_maps)) {
  1832. dev_priv->mm.interruptible = false;
  1833. if (i915_gpu_idle(dev_priv->dev)) {
  1834. DRM_ERROR("Couldn't idle GPU\n");
  1835. /* Wait a bit, in hopes it avoids the hang */
  1836. udelay(10);
  1837. }
  1838. }
  1839. return ret;
  1840. }
  1841. static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
  1842. {
  1843. if (unlikely(dev_priv->gtt.do_idle_maps))
  1844. dev_priv->mm.interruptible = interruptible;
  1845. }
  1846. void i915_check_and_clear_faults(struct drm_device *dev)
  1847. {
  1848. struct drm_i915_private *dev_priv = dev->dev_private;
  1849. struct intel_engine_cs *ring;
  1850. int i;
  1851. if (INTEL_INFO(dev)->gen < 6)
  1852. return;
  1853. for_each_ring(ring, dev_priv, i) {
  1854. u32 fault_reg;
  1855. fault_reg = I915_READ(RING_FAULT_REG(ring));
  1856. if (fault_reg & RING_FAULT_VALID) {
  1857. DRM_DEBUG_DRIVER("Unexpected fault\n"
  1858. "\tAddr: 0x%08lx\n"
  1859. "\tAddress space: %s\n"
  1860. "\tSource ID: %d\n"
  1861. "\tType: %d\n",
  1862. fault_reg & PAGE_MASK,
  1863. fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
  1864. RING_FAULT_SRCID(fault_reg),
  1865. RING_FAULT_FAULT_TYPE(fault_reg));
  1866. I915_WRITE(RING_FAULT_REG(ring),
  1867. fault_reg & ~RING_FAULT_VALID);
  1868. }
  1869. }
  1870. POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
  1871. }
  1872. static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
  1873. {
  1874. if (INTEL_INFO(dev_priv->dev)->gen < 6) {
  1875. intel_gtt_chipset_flush();
  1876. } else {
  1877. I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
  1878. POSTING_READ(GFX_FLSH_CNTL_GEN6);
  1879. }
  1880. }
  1881. void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
  1882. {
  1883. struct drm_i915_private *dev_priv = dev->dev_private;
  1884. /* Don't bother messing with faults pre GEN6 as we have little
  1885. * documentation supporting that it's a good idea.
  1886. */
  1887. if (INTEL_INFO(dev)->gen < 6)
  1888. return;
  1889. i915_check_and_clear_faults(dev);
  1890. dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
  1891. dev_priv->gtt.base.start,
  1892. dev_priv->gtt.base.total,
  1893. true);
  1894. i915_ggtt_flush(dev_priv);
  1895. }
  1896. int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
  1897. {
  1898. if (!dma_map_sg(&obj->base.dev->pdev->dev,
  1899. obj->pages->sgl, obj->pages->nents,
  1900. PCI_DMA_BIDIRECTIONAL))
  1901. return -ENOSPC;
  1902. return 0;
  1903. }
  1904. static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
  1905. {
  1906. #ifdef writeq
  1907. writeq(pte, addr);
  1908. #else
  1909. iowrite32((u32)pte, addr);
  1910. iowrite32(pte >> 32, addr + 4);
  1911. #endif
  1912. }
  1913. static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
  1914. struct sg_table *st,
  1915. uint64_t start,
  1916. enum i915_cache_level level, u32 unused)
  1917. {
  1918. struct drm_i915_private *dev_priv = vm->dev->dev_private;
  1919. unsigned first_entry = start >> PAGE_SHIFT;
  1920. gen8_pte_t __iomem *gtt_entries =
  1921. (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
  1922. int i = 0;
  1923. struct sg_page_iter sg_iter;
  1924. dma_addr_t addr = 0; /* shut up gcc */
  1925. for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
  1926. addr = sg_dma_address(sg_iter.sg) +
  1927. (sg_iter.sg_pgoffset << PAGE_SHIFT);
  1928. gen8_set_pte(&gtt_entries[i],
  1929. gen8_pte_encode(addr, level, true));
  1930. i++;
  1931. }
  1932. /*
  1933. * XXX: This serves as a posting read to make sure that the PTE has
  1934. * actually been updated. There is some concern that even though
  1935. * registers and PTEs are within the same BAR that they are potentially
  1936. * of NUMA access patterns. Therefore, even with the way we assume
  1937. * hardware should work, we must keep this posting read for paranoia.
  1938. */
  1939. if (i != 0)
  1940. WARN_ON(readq(&gtt_entries[i-1])
  1941. != gen8_pte_encode(addr, level, true));
  1942. /* This next bit makes the above posting read even more important. We
  1943. * want to flush the TLBs only after we're certain all the PTE updates
  1944. * have finished.
  1945. */
  1946. I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
  1947. POSTING_READ(GFX_FLSH_CNTL_GEN6);
  1948. }
  1949. /*
  1950. * Binds an object into the global gtt with the specified cache level. The object
  1951. * will be accessible to the GPU via commands whose operands reference offsets
  1952. * within the global GTT as well as accessible by the GPU through the GMADR
  1953. * mapped BAR (dev_priv->mm.gtt->gtt).
  1954. */
  1955. static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
  1956. struct sg_table *st,
  1957. uint64_t start,
  1958. enum i915_cache_level level, u32 flags)
  1959. {
  1960. struct drm_i915_private *dev_priv = vm->dev->dev_private;
  1961. unsigned first_entry = start >> PAGE_SHIFT;
  1962. gen6_pte_t __iomem *gtt_entries =
  1963. (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
  1964. int i = 0;
  1965. struct sg_page_iter sg_iter;
  1966. dma_addr_t addr = 0;
  1967. for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
  1968. addr = sg_page_iter_dma_address(&sg_iter);
  1969. iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
  1970. i++;
  1971. }
  1972. /* XXX: This serves as a posting read to make sure that the PTE has
  1973. * actually been updated. There is some concern that even though
  1974. * registers and PTEs are within the same BAR that they are potentially
  1975. * of NUMA access patterns. Therefore, even with the way we assume
  1976. * hardware should work, we must keep this posting read for paranoia.
  1977. */
  1978. if (i != 0) {
  1979. unsigned long gtt = readl(&gtt_entries[i-1]);
  1980. WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
  1981. }
  1982. /* This next bit makes the above posting read even more important. We
  1983. * want to flush the TLBs only after we're certain all the PTE updates
  1984. * have finished.
  1985. */
  1986. I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
  1987. POSTING_READ(GFX_FLSH_CNTL_GEN6);
  1988. }
  1989. static void gen8_ggtt_clear_range(struct i915_address_space *vm,
  1990. uint64_t start,
  1991. uint64_t length,
  1992. bool use_scratch)
  1993. {
  1994. struct drm_i915_private *dev_priv = vm->dev->dev_private;
  1995. unsigned first_entry = start >> PAGE_SHIFT;
  1996. unsigned num_entries = length >> PAGE_SHIFT;
  1997. gen8_pte_t scratch_pte, __iomem *gtt_base =
  1998. (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
  1999. const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
  2000. int i;
  2001. if (WARN(num_entries > max_entries,
  2002. "First entry = %d; Num entries = %d (max=%d)\n",
  2003. first_entry, num_entries, max_entries))
  2004. num_entries = max_entries;
  2005. scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
  2006. I915_CACHE_LLC,
  2007. use_scratch);
  2008. for (i = 0; i < num_entries; i++)
  2009. gen8_set_pte(&gtt_base[i], scratch_pte);
  2010. readl(gtt_base);
  2011. }
  2012. static void gen6_ggtt_clear_range(struct i915_address_space *vm,
  2013. uint64_t start,
  2014. uint64_t length,
  2015. bool use_scratch)
  2016. {
  2017. struct drm_i915_private *dev_priv = vm->dev->dev_private;
  2018. unsigned first_entry = start >> PAGE_SHIFT;
  2019. unsigned num_entries = length >> PAGE_SHIFT;
  2020. gen6_pte_t scratch_pte, __iomem *gtt_base =
  2021. (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
  2022. const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
  2023. int i;
  2024. if (WARN(num_entries > max_entries,
  2025. "First entry = %d; Num entries = %d (max=%d)\n",
  2026. first_entry, num_entries, max_entries))
  2027. num_entries = max_entries;
  2028. scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
  2029. I915_CACHE_LLC, use_scratch, 0);
  2030. for (i = 0; i < num_entries; i++)
  2031. iowrite32(scratch_pte, &gtt_base[i]);
  2032. readl(gtt_base);
  2033. }
  2034. static void i915_ggtt_insert_entries(struct i915_address_space *vm,
  2035. struct sg_table *pages,
  2036. uint64_t start,
  2037. enum i915_cache_level cache_level, u32 unused)
  2038. {
  2039. unsigned int flags = (cache_level == I915_CACHE_NONE) ?
  2040. AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
  2041. intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
  2042. }
  2043. static void i915_ggtt_clear_range(struct i915_address_space *vm,
  2044. uint64_t start,
  2045. uint64_t length,
  2046. bool unused)
  2047. {
  2048. unsigned first_entry = start >> PAGE_SHIFT;
  2049. unsigned num_entries = length >> PAGE_SHIFT;
  2050. intel_gtt_clear_range(first_entry, num_entries);
  2051. }
  2052. static int ggtt_bind_vma(struct i915_vma *vma,
  2053. enum i915_cache_level cache_level,
  2054. u32 flags)
  2055. {
  2056. struct drm_i915_gem_object *obj = vma->obj;
  2057. u32 pte_flags = 0;
  2058. int ret;
  2059. ret = i915_get_ggtt_vma_pages(vma);
  2060. if (ret)
  2061. return ret;
  2062. /* Currently applicable only to VLV */
  2063. if (obj->gt_ro)
  2064. pte_flags |= PTE_READ_ONLY;
  2065. vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
  2066. vma->node.start,
  2067. cache_level, pte_flags);
  2068. /*
  2069. * Without aliasing PPGTT there's no difference between
  2070. * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
  2071. * upgrade to both bound if we bind either to avoid double-binding.
  2072. */
  2073. vma->bound |= GLOBAL_BIND | LOCAL_BIND;
  2074. return 0;
  2075. }
  2076. static int aliasing_gtt_bind_vma(struct i915_vma *vma,
  2077. enum i915_cache_level cache_level,
  2078. u32 flags)
  2079. {
  2080. struct drm_device *dev = vma->vm->dev;
  2081. struct drm_i915_private *dev_priv = dev->dev_private;
  2082. struct drm_i915_gem_object *obj = vma->obj;
  2083. struct sg_table *pages = obj->pages;
  2084. u32 pte_flags = 0;
  2085. int ret;
  2086. ret = i915_get_ggtt_vma_pages(vma);
  2087. if (ret)
  2088. return ret;
  2089. pages = vma->ggtt_view.pages;
  2090. /* Currently applicable only to VLV */
  2091. if (obj->gt_ro)
  2092. pte_flags |= PTE_READ_ONLY;
  2093. if (flags & GLOBAL_BIND) {
  2094. vma->vm->insert_entries(vma->vm, pages,
  2095. vma->node.start,
  2096. cache_level, pte_flags);
  2097. }
  2098. if (flags & LOCAL_BIND) {
  2099. struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
  2100. appgtt->base.insert_entries(&appgtt->base, pages,
  2101. vma->node.start,
  2102. cache_level, pte_flags);
  2103. }
  2104. return 0;
  2105. }
  2106. static void ggtt_unbind_vma(struct i915_vma *vma)
  2107. {
  2108. struct drm_device *dev = vma->vm->dev;
  2109. struct drm_i915_private *dev_priv = dev->dev_private;
  2110. struct drm_i915_gem_object *obj = vma->obj;
  2111. const uint64_t size = min_t(uint64_t,
  2112. obj->base.size,
  2113. vma->node.size);
  2114. if (vma->bound & GLOBAL_BIND) {
  2115. vma->vm->clear_range(vma->vm,
  2116. vma->node.start,
  2117. size,
  2118. true);
  2119. }
  2120. if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
  2121. struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
  2122. appgtt->base.clear_range(&appgtt->base,
  2123. vma->node.start,
  2124. size,
  2125. true);
  2126. }
  2127. }
  2128. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
  2129. {
  2130. struct drm_device *dev = obj->base.dev;
  2131. struct drm_i915_private *dev_priv = dev->dev_private;
  2132. bool interruptible;
  2133. interruptible = do_idling(dev_priv);
  2134. dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
  2135. PCI_DMA_BIDIRECTIONAL);
  2136. undo_idling(dev_priv, interruptible);
  2137. }
  2138. static void i915_gtt_color_adjust(struct drm_mm_node *node,
  2139. unsigned long color,
  2140. u64 *start,
  2141. u64 *end)
  2142. {
  2143. if (node->color != color)
  2144. *start += 4096;
  2145. if (!list_empty(&node->node_list)) {
  2146. node = list_entry(node->node_list.next,
  2147. struct drm_mm_node,
  2148. node_list);
  2149. if (node->allocated && node->color != color)
  2150. *end -= 4096;
  2151. }
  2152. }
  2153. static int i915_gem_setup_global_gtt(struct drm_device *dev,
  2154. u64 start,
  2155. u64 mappable_end,
  2156. u64 end)
  2157. {
  2158. /* Let GEM Manage all of the aperture.
  2159. *
  2160. * However, leave one page at the end still bound to the scratch page.
  2161. * There are a number of places where the hardware apparently prefetches
  2162. * past the end of the object, and we've seen multiple hangs with the
  2163. * GPU head pointer stuck in a batchbuffer bound at the last page of the
  2164. * aperture. One page should be enough to keep any prefetching inside
  2165. * of the aperture.
  2166. */
  2167. struct drm_i915_private *dev_priv = dev->dev_private;
  2168. struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
  2169. struct drm_mm_node *entry;
  2170. struct drm_i915_gem_object *obj;
  2171. unsigned long hole_start, hole_end;
  2172. int ret;
  2173. BUG_ON(mappable_end > end);
  2174. ggtt_vm->start = start;
  2175. /* Subtract the guard page before address space initialization to
  2176. * shrink the range used by drm_mm */
  2177. ggtt_vm->total = end - start - PAGE_SIZE;
  2178. i915_address_space_init(ggtt_vm, dev_priv);
  2179. ggtt_vm->total += PAGE_SIZE;
  2180. if (intel_vgpu_active(dev)) {
  2181. ret = intel_vgt_balloon(dev);
  2182. if (ret)
  2183. return ret;
  2184. }
  2185. if (!HAS_LLC(dev))
  2186. ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
  2187. /* Mark any preallocated objects as occupied */
  2188. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
  2189. struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
  2190. DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
  2191. i915_gem_obj_ggtt_offset(obj), obj->base.size);
  2192. WARN_ON(i915_gem_obj_ggtt_bound(obj));
  2193. ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
  2194. if (ret) {
  2195. DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
  2196. return ret;
  2197. }
  2198. vma->bound |= GLOBAL_BIND;
  2199. __i915_vma_set_map_and_fenceable(vma);
  2200. list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
  2201. }
  2202. /* Clear any non-preallocated blocks */
  2203. drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
  2204. DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
  2205. hole_start, hole_end);
  2206. ggtt_vm->clear_range(ggtt_vm, hole_start,
  2207. hole_end - hole_start, true);
  2208. }
  2209. /* And finally clear the reserved guard page */
  2210. ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
  2211. if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
  2212. struct i915_hw_ppgtt *ppgtt;
  2213. ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
  2214. if (!ppgtt)
  2215. return -ENOMEM;
  2216. ret = __hw_ppgtt_init(dev, ppgtt);
  2217. if (ret) {
  2218. ppgtt->base.cleanup(&ppgtt->base);
  2219. kfree(ppgtt);
  2220. return ret;
  2221. }
  2222. if (ppgtt->base.allocate_va_range)
  2223. ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
  2224. ppgtt->base.total);
  2225. if (ret) {
  2226. ppgtt->base.cleanup(&ppgtt->base);
  2227. kfree(ppgtt);
  2228. return ret;
  2229. }
  2230. ppgtt->base.clear_range(&ppgtt->base,
  2231. ppgtt->base.start,
  2232. ppgtt->base.total,
  2233. true);
  2234. dev_priv->mm.aliasing_ppgtt = ppgtt;
  2235. WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
  2236. dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
  2237. }
  2238. return 0;
  2239. }
  2240. void i915_gem_init_global_gtt(struct drm_device *dev)
  2241. {
  2242. struct drm_i915_private *dev_priv = dev->dev_private;
  2243. u64 gtt_size, mappable_size;
  2244. gtt_size = dev_priv->gtt.base.total;
  2245. mappable_size = dev_priv->gtt.mappable_end;
  2246. i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
  2247. }
  2248. void i915_global_gtt_cleanup(struct drm_device *dev)
  2249. {
  2250. struct drm_i915_private *dev_priv = dev->dev_private;
  2251. struct i915_address_space *vm = &dev_priv->gtt.base;
  2252. if (dev_priv->mm.aliasing_ppgtt) {
  2253. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  2254. ppgtt->base.cleanup(&ppgtt->base);
  2255. kfree(ppgtt);
  2256. }
  2257. if (drm_mm_initialized(&vm->mm)) {
  2258. if (intel_vgpu_active(dev))
  2259. intel_vgt_deballoon();
  2260. drm_mm_takedown(&vm->mm);
  2261. list_del(&vm->global_link);
  2262. }
  2263. vm->cleanup(vm);
  2264. }
  2265. static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
  2266. {
  2267. snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
  2268. snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
  2269. return snb_gmch_ctl << 20;
  2270. }
  2271. static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
  2272. {
  2273. bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
  2274. bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
  2275. if (bdw_gmch_ctl)
  2276. bdw_gmch_ctl = 1 << bdw_gmch_ctl;
  2277. #ifdef CONFIG_X86_32
  2278. /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
  2279. if (bdw_gmch_ctl > 4)
  2280. bdw_gmch_ctl = 4;
  2281. #endif
  2282. return bdw_gmch_ctl << 20;
  2283. }
  2284. static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
  2285. {
  2286. gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
  2287. gmch_ctrl &= SNB_GMCH_GGMS_MASK;
  2288. if (gmch_ctrl)
  2289. return 1 << (20 + gmch_ctrl);
  2290. return 0;
  2291. }
  2292. static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
  2293. {
  2294. snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
  2295. snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
  2296. return snb_gmch_ctl << 25; /* 32 MB units */
  2297. }
  2298. static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
  2299. {
  2300. bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
  2301. bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
  2302. return bdw_gmch_ctl << 25; /* 32 MB units */
  2303. }
  2304. static size_t chv_get_stolen_size(u16 gmch_ctrl)
  2305. {
  2306. gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
  2307. gmch_ctrl &= SNB_GMCH_GMS_MASK;
  2308. /*
  2309. * 0x0 to 0x10: 32MB increments starting at 0MB
  2310. * 0x11 to 0x16: 4MB increments starting at 8MB
  2311. * 0x17 to 0x1d: 4MB increments start at 36MB
  2312. */
  2313. if (gmch_ctrl < 0x11)
  2314. return gmch_ctrl << 25;
  2315. else if (gmch_ctrl < 0x17)
  2316. return (gmch_ctrl - 0x11 + 2) << 22;
  2317. else
  2318. return (gmch_ctrl - 0x17 + 9) << 22;
  2319. }
  2320. static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
  2321. {
  2322. gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
  2323. gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
  2324. if (gen9_gmch_ctl < 0xf0)
  2325. return gen9_gmch_ctl << 25; /* 32 MB units */
  2326. else
  2327. /* 4MB increments starting at 0xf0 for 4MB */
  2328. return (gen9_gmch_ctl - 0xf0 + 1) << 22;
  2329. }
  2330. static int ggtt_probe_common(struct drm_device *dev,
  2331. size_t gtt_size)
  2332. {
  2333. struct drm_i915_private *dev_priv = dev->dev_private;
  2334. struct i915_page_scratch *scratch_page;
  2335. phys_addr_t gtt_phys_addr;
  2336. /* For Modern GENs the PTEs and register space are split in the BAR */
  2337. gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
  2338. (pci_resource_len(dev->pdev, 0) / 2);
  2339. /*
  2340. * On BXT writes larger than 64 bit to the GTT pagetable range will be
  2341. * dropped. For WC mappings in general we have 64 byte burst writes
  2342. * when the WC buffer is flushed, so we can't use it, but have to
  2343. * resort to an uncached mapping. The WC issue is easily caught by the
  2344. * readback check when writing GTT PTE entries.
  2345. */
  2346. if (IS_BROXTON(dev))
  2347. dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
  2348. else
  2349. dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
  2350. if (!dev_priv->gtt.gsm) {
  2351. DRM_ERROR("Failed to map the gtt page table\n");
  2352. return -ENOMEM;
  2353. }
  2354. scratch_page = alloc_scratch_page(dev);
  2355. if (IS_ERR(scratch_page)) {
  2356. DRM_ERROR("Scratch setup failed\n");
  2357. /* iounmap will also get called at remove, but meh */
  2358. iounmap(dev_priv->gtt.gsm);
  2359. return PTR_ERR(scratch_page);
  2360. }
  2361. dev_priv->gtt.base.scratch_page = scratch_page;
  2362. return 0;
  2363. }
  2364. /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  2365. * bits. When using advanced contexts each context stores its own PAT, but
  2366. * writing this data shouldn't be harmful even in those cases. */
  2367. static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
  2368. {
  2369. uint64_t pat;
  2370. pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
  2371. GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
  2372. GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
  2373. GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
  2374. GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
  2375. GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
  2376. GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
  2377. GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
  2378. if (!USES_PPGTT(dev_priv->dev))
  2379. /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
  2380. * so RTL will always use the value corresponding to
  2381. * pat_sel = 000".
  2382. * So let's disable cache for GGTT to avoid screen corruptions.
  2383. * MOCS still can be used though.
  2384. * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
  2385. * before this patch, i.e. the same uncached + snooping access
  2386. * like on gen6/7 seems to be in effect.
  2387. * - So this just fixes blitter/render access. Again it looks
  2388. * like it's not just uncached access, but uncached + snooping.
  2389. * So we can still hold onto all our assumptions wrt cpu
  2390. * clflushing on LLC machines.
  2391. */
  2392. pat = GEN8_PPAT(0, GEN8_PPAT_UC);
  2393. /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
  2394. * write would work. */
  2395. I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
  2396. I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
  2397. }
  2398. static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
  2399. {
  2400. uint64_t pat;
  2401. /*
  2402. * Map WB on BDW to snooped on CHV.
  2403. *
  2404. * Only the snoop bit has meaning for CHV, the rest is
  2405. * ignored.
  2406. *
  2407. * The hardware will never snoop for certain types of accesses:
  2408. * - CPU GTT (GMADR->GGTT->no snoop->memory)
  2409. * - PPGTT page tables
  2410. * - some other special cycles
  2411. *
  2412. * As with BDW, we also need to consider the following for GT accesses:
  2413. * "For GGTT, there is NO pat_sel[2:0] from the entry,
  2414. * so RTL will always use the value corresponding to
  2415. * pat_sel = 000".
  2416. * Which means we must set the snoop bit in PAT entry 0
  2417. * in order to keep the global status page working.
  2418. */
  2419. pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
  2420. GEN8_PPAT(1, 0) |
  2421. GEN8_PPAT(2, 0) |
  2422. GEN8_PPAT(3, 0) |
  2423. GEN8_PPAT(4, CHV_PPAT_SNOOP) |
  2424. GEN8_PPAT(5, CHV_PPAT_SNOOP) |
  2425. GEN8_PPAT(6, CHV_PPAT_SNOOP) |
  2426. GEN8_PPAT(7, CHV_PPAT_SNOOP);
  2427. I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
  2428. I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
  2429. }
  2430. static int gen8_gmch_probe(struct drm_device *dev,
  2431. u64 *gtt_total,
  2432. size_t *stolen,
  2433. phys_addr_t *mappable_base,
  2434. u64 *mappable_end)
  2435. {
  2436. struct drm_i915_private *dev_priv = dev->dev_private;
  2437. u64 gtt_size;
  2438. u16 snb_gmch_ctl;
  2439. int ret;
  2440. /* TODO: We're not aware of mappable constraints on gen8 yet */
  2441. *mappable_base = pci_resource_start(dev->pdev, 2);
  2442. *mappable_end = pci_resource_len(dev->pdev, 2);
  2443. if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
  2444. pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
  2445. pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
  2446. if (INTEL_INFO(dev)->gen >= 9) {
  2447. *stolen = gen9_get_stolen_size(snb_gmch_ctl);
  2448. gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
  2449. } else if (IS_CHERRYVIEW(dev)) {
  2450. *stolen = chv_get_stolen_size(snb_gmch_ctl);
  2451. gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
  2452. } else {
  2453. *stolen = gen8_get_stolen_size(snb_gmch_ctl);
  2454. gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
  2455. }
  2456. *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
  2457. if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
  2458. chv_setup_private_ppat(dev_priv);
  2459. else
  2460. bdw_setup_private_ppat(dev_priv);
  2461. ret = ggtt_probe_common(dev, gtt_size);
  2462. dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
  2463. dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
  2464. dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
  2465. dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
  2466. return ret;
  2467. }
  2468. static int gen6_gmch_probe(struct drm_device *dev,
  2469. u64 *gtt_total,
  2470. size_t *stolen,
  2471. phys_addr_t *mappable_base,
  2472. u64 *mappable_end)
  2473. {
  2474. struct drm_i915_private *dev_priv = dev->dev_private;
  2475. unsigned int gtt_size;
  2476. u16 snb_gmch_ctl;
  2477. int ret;
  2478. *mappable_base = pci_resource_start(dev->pdev, 2);
  2479. *mappable_end = pci_resource_len(dev->pdev, 2);
  2480. /* 64/512MB is the current min/max we actually know of, but this is just
  2481. * a coarse sanity check.
  2482. */
  2483. if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
  2484. DRM_ERROR("Unknown GMADR size (%llx)\n",
  2485. dev_priv->gtt.mappable_end);
  2486. return -ENXIO;
  2487. }
  2488. if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
  2489. pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
  2490. pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
  2491. *stolen = gen6_get_stolen_size(snb_gmch_ctl);
  2492. gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
  2493. *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
  2494. ret = ggtt_probe_common(dev, gtt_size);
  2495. dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
  2496. dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
  2497. dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
  2498. dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
  2499. return ret;
  2500. }
  2501. static void gen6_gmch_remove(struct i915_address_space *vm)
  2502. {
  2503. struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
  2504. iounmap(gtt->gsm);
  2505. free_scratch_page(vm->dev, vm->scratch_page);
  2506. }
  2507. static int i915_gmch_probe(struct drm_device *dev,
  2508. u64 *gtt_total,
  2509. size_t *stolen,
  2510. phys_addr_t *mappable_base,
  2511. u64 *mappable_end)
  2512. {
  2513. struct drm_i915_private *dev_priv = dev->dev_private;
  2514. int ret;
  2515. ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
  2516. if (!ret) {
  2517. DRM_ERROR("failed to set up gmch\n");
  2518. return -EIO;
  2519. }
  2520. intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
  2521. dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
  2522. dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
  2523. dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
  2524. dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
  2525. dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
  2526. if (unlikely(dev_priv->gtt.do_idle_maps))
  2527. DRM_INFO("applying Ironlake quirks for intel_iommu\n");
  2528. return 0;
  2529. }
  2530. static void i915_gmch_remove(struct i915_address_space *vm)
  2531. {
  2532. intel_gmch_remove();
  2533. }
  2534. int i915_gem_gtt_init(struct drm_device *dev)
  2535. {
  2536. struct drm_i915_private *dev_priv = dev->dev_private;
  2537. struct i915_gtt *gtt = &dev_priv->gtt;
  2538. int ret;
  2539. if (INTEL_INFO(dev)->gen <= 5) {
  2540. gtt->gtt_probe = i915_gmch_probe;
  2541. gtt->base.cleanup = i915_gmch_remove;
  2542. } else if (INTEL_INFO(dev)->gen < 8) {
  2543. gtt->gtt_probe = gen6_gmch_probe;
  2544. gtt->base.cleanup = gen6_gmch_remove;
  2545. if (IS_HASWELL(dev) && dev_priv->ellc_size)
  2546. gtt->base.pte_encode = iris_pte_encode;
  2547. else if (IS_HASWELL(dev))
  2548. gtt->base.pte_encode = hsw_pte_encode;
  2549. else if (IS_VALLEYVIEW(dev))
  2550. gtt->base.pte_encode = byt_pte_encode;
  2551. else if (INTEL_INFO(dev)->gen >= 7)
  2552. gtt->base.pte_encode = ivb_pte_encode;
  2553. else
  2554. gtt->base.pte_encode = snb_pte_encode;
  2555. } else {
  2556. dev_priv->gtt.gtt_probe = gen8_gmch_probe;
  2557. dev_priv->gtt.base.cleanup = gen6_gmch_remove;
  2558. }
  2559. gtt->base.dev = dev;
  2560. ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
  2561. &gtt->mappable_base, &gtt->mappable_end);
  2562. if (ret)
  2563. return ret;
  2564. /* GMADR is the PCI mmio aperture into the global GTT. */
  2565. DRM_INFO("Memory usable by graphics device = %lluM\n",
  2566. gtt->base.total >> 20);
  2567. DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
  2568. DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
  2569. #ifdef CONFIG_INTEL_IOMMU
  2570. if (intel_iommu_gfx_mapped)
  2571. DRM_INFO("VT-d active for gfx access\n");
  2572. #endif
  2573. /*
  2574. * i915.enable_ppgtt is read-only, so do an early pass to validate the
  2575. * user's requested state against the hardware/driver capabilities. We
  2576. * do this now so that we can print out any log messages once rather
  2577. * than every time we check intel_enable_ppgtt().
  2578. */
  2579. i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
  2580. DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
  2581. return 0;
  2582. }
  2583. void i915_gem_restore_gtt_mappings(struct drm_device *dev)
  2584. {
  2585. struct drm_i915_private *dev_priv = dev->dev_private;
  2586. struct drm_i915_gem_object *obj;
  2587. struct i915_address_space *vm;
  2588. struct i915_vma *vma;
  2589. bool flush;
  2590. i915_check_and_clear_faults(dev);
  2591. /* First fill our portion of the GTT with scratch pages */
  2592. dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
  2593. dev_priv->gtt.base.start,
  2594. dev_priv->gtt.base.total,
  2595. true);
  2596. /* Cache flush objects bound into GGTT and rebind them. */
  2597. vm = &dev_priv->gtt.base;
  2598. list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
  2599. flush = false;
  2600. list_for_each_entry(vma, &obj->vma_list, vma_link) {
  2601. if (vma->vm != vm)
  2602. continue;
  2603. WARN_ON(i915_vma_bind(vma, obj->cache_level,
  2604. PIN_UPDATE));
  2605. flush = true;
  2606. }
  2607. if (flush)
  2608. i915_gem_clflush_object(obj, obj->pin_display);
  2609. }
  2610. if (INTEL_INFO(dev)->gen >= 8) {
  2611. if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
  2612. chv_setup_private_ppat(dev_priv);
  2613. else
  2614. bdw_setup_private_ppat(dev_priv);
  2615. return;
  2616. }
  2617. if (USES_PPGTT(dev)) {
  2618. list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
  2619. /* TODO: Perhaps it shouldn't be gen6 specific */
  2620. struct i915_hw_ppgtt *ppgtt =
  2621. container_of(vm, struct i915_hw_ppgtt,
  2622. base);
  2623. if (i915_is_ggtt(vm))
  2624. ppgtt = dev_priv->mm.aliasing_ppgtt;
  2625. gen6_write_page_range(dev_priv, &ppgtt->pd,
  2626. 0, ppgtt->base.total);
  2627. }
  2628. }
  2629. i915_ggtt_flush(dev_priv);
  2630. }
  2631. static struct i915_vma *
  2632. __i915_gem_vma_create(struct drm_i915_gem_object *obj,
  2633. struct i915_address_space *vm,
  2634. const struct i915_ggtt_view *ggtt_view)
  2635. {
  2636. struct i915_vma *vma;
  2637. if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
  2638. return ERR_PTR(-EINVAL);
  2639. vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
  2640. if (vma == NULL)
  2641. return ERR_PTR(-ENOMEM);
  2642. INIT_LIST_HEAD(&vma->vma_link);
  2643. INIT_LIST_HEAD(&vma->mm_list);
  2644. INIT_LIST_HEAD(&vma->exec_list);
  2645. vma->vm = vm;
  2646. vma->obj = obj;
  2647. if (i915_is_ggtt(vm))
  2648. vma->ggtt_view = *ggtt_view;
  2649. list_add_tail(&vma->vma_link, &obj->vma_list);
  2650. if (!i915_is_ggtt(vm))
  2651. i915_ppgtt_get(i915_vm_to_ppgtt(vm));
  2652. return vma;
  2653. }
  2654. struct i915_vma *
  2655. i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
  2656. struct i915_address_space *vm)
  2657. {
  2658. struct i915_vma *vma;
  2659. vma = i915_gem_obj_to_vma(obj, vm);
  2660. if (!vma)
  2661. vma = __i915_gem_vma_create(obj, vm,
  2662. i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
  2663. return vma;
  2664. }
  2665. struct i915_vma *
  2666. i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
  2667. const struct i915_ggtt_view *view)
  2668. {
  2669. struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
  2670. struct i915_vma *vma;
  2671. if (WARN_ON(!view))
  2672. return ERR_PTR(-EINVAL);
  2673. vma = i915_gem_obj_to_ggtt_view(obj, view);
  2674. if (IS_ERR(vma))
  2675. return vma;
  2676. if (!vma)
  2677. vma = __i915_gem_vma_create(obj, ggtt, view);
  2678. return vma;
  2679. }
  2680. static struct scatterlist *
  2681. rotate_pages(dma_addr_t *in, unsigned int offset,
  2682. unsigned int width, unsigned int height,
  2683. struct sg_table *st, struct scatterlist *sg)
  2684. {
  2685. unsigned int column, row;
  2686. unsigned int src_idx;
  2687. if (!sg) {
  2688. st->nents = 0;
  2689. sg = st->sgl;
  2690. }
  2691. for (column = 0; column < width; column++) {
  2692. src_idx = width * (height - 1) + column;
  2693. for (row = 0; row < height; row++) {
  2694. st->nents++;
  2695. /* We don't need the pages, but need to initialize
  2696. * the entries so the sg list can be happily traversed.
  2697. * The only thing we need are DMA addresses.
  2698. */
  2699. sg_set_page(sg, NULL, PAGE_SIZE, 0);
  2700. sg_dma_address(sg) = in[offset + src_idx];
  2701. sg_dma_len(sg) = PAGE_SIZE;
  2702. sg = sg_next(sg);
  2703. src_idx -= width;
  2704. }
  2705. }
  2706. return sg;
  2707. }
  2708. static struct sg_table *
  2709. intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
  2710. struct drm_i915_gem_object *obj)
  2711. {
  2712. struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
  2713. unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
  2714. unsigned int size_pages_uv;
  2715. struct sg_page_iter sg_iter;
  2716. unsigned long i;
  2717. dma_addr_t *page_addr_list;
  2718. struct sg_table *st;
  2719. unsigned int uv_start_page;
  2720. struct scatterlist *sg;
  2721. int ret = -ENOMEM;
  2722. /* Allocate a temporary list of source pages for random access. */
  2723. page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
  2724. sizeof(dma_addr_t));
  2725. if (!page_addr_list)
  2726. return ERR_PTR(ret);
  2727. /* Account for UV plane with NV12. */
  2728. if (rot_info->pixel_format == DRM_FORMAT_NV12)
  2729. size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
  2730. else
  2731. size_pages_uv = 0;
  2732. /* Allocate target SG list. */
  2733. st = kmalloc(sizeof(*st), GFP_KERNEL);
  2734. if (!st)
  2735. goto err_st_alloc;
  2736. ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
  2737. if (ret)
  2738. goto err_sg_alloc;
  2739. /* Populate source page list from the object. */
  2740. i = 0;
  2741. for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
  2742. page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
  2743. i++;
  2744. }
  2745. /* Rotate the pages. */
  2746. sg = rotate_pages(page_addr_list, 0,
  2747. rot_info->width_pages, rot_info->height_pages,
  2748. st, NULL);
  2749. /* Append the UV plane if NV12. */
  2750. if (rot_info->pixel_format == DRM_FORMAT_NV12) {
  2751. uv_start_page = size_pages;
  2752. /* Check for tile-row un-alignment. */
  2753. if (offset_in_page(rot_info->uv_offset))
  2754. uv_start_page--;
  2755. rot_info->uv_start_page = uv_start_page;
  2756. rotate_pages(page_addr_list, uv_start_page,
  2757. rot_info->width_pages_uv,
  2758. rot_info->height_pages_uv,
  2759. st, sg);
  2760. }
  2761. DRM_DEBUG_KMS(
  2762. "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
  2763. obj->base.size, rot_info->pitch, rot_info->height,
  2764. rot_info->pixel_format, rot_info->width_pages,
  2765. rot_info->height_pages, size_pages + size_pages_uv,
  2766. size_pages);
  2767. drm_free_large(page_addr_list);
  2768. return st;
  2769. err_sg_alloc:
  2770. kfree(st);
  2771. err_st_alloc:
  2772. drm_free_large(page_addr_list);
  2773. DRM_DEBUG_KMS(
  2774. "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
  2775. obj->base.size, ret, rot_info->pitch, rot_info->height,
  2776. rot_info->pixel_format, rot_info->width_pages,
  2777. rot_info->height_pages, size_pages + size_pages_uv,
  2778. size_pages);
  2779. return ERR_PTR(ret);
  2780. }
  2781. static struct sg_table *
  2782. intel_partial_pages(const struct i915_ggtt_view *view,
  2783. struct drm_i915_gem_object *obj)
  2784. {
  2785. struct sg_table *st;
  2786. struct scatterlist *sg;
  2787. struct sg_page_iter obj_sg_iter;
  2788. int ret = -ENOMEM;
  2789. st = kmalloc(sizeof(*st), GFP_KERNEL);
  2790. if (!st)
  2791. goto err_st_alloc;
  2792. ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
  2793. if (ret)
  2794. goto err_sg_alloc;
  2795. sg = st->sgl;
  2796. st->nents = 0;
  2797. for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
  2798. view->params.partial.offset)
  2799. {
  2800. if (st->nents >= view->params.partial.size)
  2801. break;
  2802. sg_set_page(sg, NULL, PAGE_SIZE, 0);
  2803. sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
  2804. sg_dma_len(sg) = PAGE_SIZE;
  2805. sg = sg_next(sg);
  2806. st->nents++;
  2807. }
  2808. return st;
  2809. err_sg_alloc:
  2810. kfree(st);
  2811. err_st_alloc:
  2812. return ERR_PTR(ret);
  2813. }
  2814. static int
  2815. i915_get_ggtt_vma_pages(struct i915_vma *vma)
  2816. {
  2817. int ret = 0;
  2818. if (vma->ggtt_view.pages)
  2819. return 0;
  2820. if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
  2821. vma->ggtt_view.pages = vma->obj->pages;
  2822. else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
  2823. vma->ggtt_view.pages =
  2824. intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
  2825. else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
  2826. vma->ggtt_view.pages =
  2827. intel_partial_pages(&vma->ggtt_view, vma->obj);
  2828. else
  2829. WARN_ONCE(1, "GGTT view %u not implemented!\n",
  2830. vma->ggtt_view.type);
  2831. if (!vma->ggtt_view.pages) {
  2832. DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
  2833. vma->ggtt_view.type);
  2834. ret = -EINVAL;
  2835. } else if (IS_ERR(vma->ggtt_view.pages)) {
  2836. ret = PTR_ERR(vma->ggtt_view.pages);
  2837. vma->ggtt_view.pages = NULL;
  2838. DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
  2839. vma->ggtt_view.type, ret);
  2840. }
  2841. return ret;
  2842. }
  2843. /**
  2844. * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
  2845. * @vma: VMA to map
  2846. * @cache_level: mapping cache level
  2847. * @flags: flags like global or local mapping
  2848. *
  2849. * DMA addresses are taken from the scatter-gather table of this object (or of
  2850. * this VMA in case of non-default GGTT views) and PTE entries set up.
  2851. * Note that DMA addresses are also the only part of the SG table we care about.
  2852. */
  2853. int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
  2854. u32 flags)
  2855. {
  2856. int ret;
  2857. u32 bind_flags;
  2858. if (WARN_ON(flags == 0))
  2859. return -EINVAL;
  2860. bind_flags = 0;
  2861. if (flags & PIN_GLOBAL)
  2862. bind_flags |= GLOBAL_BIND;
  2863. if (flags & PIN_USER)
  2864. bind_flags |= LOCAL_BIND;
  2865. if (flags & PIN_UPDATE)
  2866. bind_flags |= vma->bound;
  2867. else
  2868. bind_flags &= ~vma->bound;
  2869. if (bind_flags == 0)
  2870. return 0;
  2871. if (vma->bound == 0 && vma->vm->allocate_va_range) {
  2872. trace_i915_va_alloc(vma->vm,
  2873. vma->node.start,
  2874. vma->node.size,
  2875. VM_TO_TRACE_NAME(vma->vm));
  2876. /* XXX: i915_vma_pin() will fix this +- hack */
  2877. vma->pin_count++;
  2878. ret = vma->vm->allocate_va_range(vma->vm,
  2879. vma->node.start,
  2880. vma->node.size);
  2881. vma->pin_count--;
  2882. if (ret)
  2883. return ret;
  2884. }
  2885. ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
  2886. if (ret)
  2887. return ret;
  2888. vma->bound |= bind_flags;
  2889. return 0;
  2890. }
  2891. /**
  2892. * i915_ggtt_view_size - Get the size of a GGTT view.
  2893. * @obj: Object the view is of.
  2894. * @view: The view in question.
  2895. *
  2896. * @return The size of the GGTT view in bytes.
  2897. */
  2898. size_t
  2899. i915_ggtt_view_size(struct drm_i915_gem_object *obj,
  2900. const struct i915_ggtt_view *view)
  2901. {
  2902. if (view->type == I915_GGTT_VIEW_NORMAL) {
  2903. return obj->base.size;
  2904. } else if (view->type == I915_GGTT_VIEW_ROTATED) {
  2905. return view->rotation_info.size;
  2906. } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
  2907. return view->params.partial.size << PAGE_SHIFT;
  2908. } else {
  2909. WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
  2910. return obj->base.size;
  2911. }
  2912. }