intel_dsi_panel_vbt.c 20 KB

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  1. /*
  2. * Copyright © 2014 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24. *
  25. */
  26. #include <drm/drmP.h>
  27. #include <drm/drm_crtc.h>
  28. #include <drm/drm_edid.h>
  29. #include <drm/i915_drm.h>
  30. #include <drm/drm_panel.h>
  31. #include <linux/slab.h>
  32. #include <video/mipi_display.h>
  33. #include <asm/intel-mid.h>
  34. #include <video/mipi_display.h>
  35. #include "i915_drv.h"
  36. #include "intel_drv.h"
  37. #include "intel_dsi.h"
  38. struct vbt_panel {
  39. struct drm_panel panel;
  40. struct intel_dsi *intel_dsi;
  41. };
  42. static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
  43. {
  44. return container_of(panel, struct vbt_panel, panel);
  45. }
  46. #define MIPI_TRANSFER_MODE_SHIFT 0
  47. #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
  48. #define MIPI_PORT_SHIFT 3
  49. #define PREPARE_CNT_MAX 0x3F
  50. #define EXIT_ZERO_CNT_MAX 0x3F
  51. #define CLK_ZERO_CNT_MAX 0xFF
  52. #define TRAIL_CNT_MAX 0x1F
  53. #define NS_KHZ_RATIO 1000000
  54. #define GPI0_NC_0_HV_DDI0_HPD 0x4130
  55. #define GPIO_NC_0_HV_DDI0_PAD 0x4138
  56. #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
  57. #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
  58. #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
  59. #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
  60. #define GPIO_NC_3_PANEL0_VDDEN 0x4140
  61. #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
  62. #define GPIO_NC_4_PANEL0_BLKEN 0x4150
  63. #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
  64. #define GPIO_NC_5_PANEL0_BLKCTL 0x4160
  65. #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
  66. #define GPIO_NC_6_PCONF0 0x4180
  67. #define GPIO_NC_6_PAD 0x4188
  68. #define GPIO_NC_7_PCONF0 0x4190
  69. #define GPIO_NC_7_PAD 0x4198
  70. #define GPIO_NC_8_PCONF0 0x4170
  71. #define GPIO_NC_8_PAD 0x4178
  72. #define GPIO_NC_9_PCONF0 0x4100
  73. #define GPIO_NC_9_PAD 0x4108
  74. #define GPIO_NC_10_PCONF0 0x40E0
  75. #define GPIO_NC_10_PAD 0x40E8
  76. #define GPIO_NC_11_PCONF0 0x40F0
  77. #define GPIO_NC_11_PAD 0x40F8
  78. struct gpio_table {
  79. u16 function_reg;
  80. u16 pad_reg;
  81. u8 init;
  82. };
  83. static struct gpio_table gtable[] = {
  84. { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
  85. { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
  86. { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
  87. { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
  88. { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
  89. { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
  90. { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
  91. { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
  92. { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
  93. { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
  94. { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
  95. { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
  96. };
  97. static inline enum port intel_dsi_seq_port_to_port(u8 port)
  98. {
  99. return port ? PORT_C : PORT_A;
  100. }
  101. static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
  102. const u8 *data)
  103. {
  104. struct mipi_dsi_device *dsi_device;
  105. u8 type, flags, seq_port;
  106. u16 len;
  107. enum port port;
  108. flags = *data++;
  109. type = *data++;
  110. len = *((u16 *) data);
  111. data += 2;
  112. seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
  113. /* For DSI single link on Port A & C, the seq_port value which is
  114. * parsed from Sequence Block#53 of VBT has been set to 0
  115. * Now, read/write of packets for the DSI single link on Port A and
  116. * Port C will based on the DVO port from VBT block 2.
  117. */
  118. if (intel_dsi->ports == (1 << PORT_C))
  119. port = PORT_C;
  120. else
  121. port = intel_dsi_seq_port_to_port(seq_port);
  122. dsi_device = intel_dsi->dsi_hosts[port]->device;
  123. if (!dsi_device) {
  124. DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
  125. goto out;
  126. }
  127. if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
  128. dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
  129. else
  130. dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
  131. dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
  132. switch (type) {
  133. case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
  134. mipi_dsi_generic_write(dsi_device, NULL, 0);
  135. break;
  136. case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
  137. mipi_dsi_generic_write(dsi_device, data, 1);
  138. break;
  139. case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
  140. mipi_dsi_generic_write(dsi_device, data, 2);
  141. break;
  142. case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
  143. case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
  144. case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
  145. DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
  146. break;
  147. case MIPI_DSI_GENERIC_LONG_WRITE:
  148. mipi_dsi_generic_write(dsi_device, data, len);
  149. break;
  150. case MIPI_DSI_DCS_SHORT_WRITE:
  151. mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
  152. break;
  153. case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
  154. mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
  155. break;
  156. case MIPI_DSI_DCS_READ:
  157. DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
  158. break;
  159. case MIPI_DSI_DCS_LONG_WRITE:
  160. mipi_dsi_dcs_write_buffer(dsi_device, data, len);
  161. break;
  162. }
  163. out:
  164. data += len;
  165. return data;
  166. }
  167. static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
  168. {
  169. u32 delay = *((const u32 *) data);
  170. usleep_range(delay, delay + 10);
  171. data += 4;
  172. return data;
  173. }
  174. static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
  175. {
  176. u8 gpio, action;
  177. u16 function, pad;
  178. u32 val;
  179. struct drm_device *dev = intel_dsi->base.base.dev;
  180. struct drm_i915_private *dev_priv = dev->dev_private;
  181. gpio = *data++;
  182. /* pull up/down */
  183. action = *data++ & 1;
  184. if (gpio >= ARRAY_SIZE(gtable)) {
  185. DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
  186. goto out;
  187. }
  188. function = gtable[gpio].function_reg;
  189. pad = gtable[gpio].pad_reg;
  190. mutex_lock(&dev_priv->sb_lock);
  191. if (!gtable[gpio].init) {
  192. /* program the function */
  193. /* FIXME: remove constant below */
  194. vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
  195. gtable[gpio].init = 1;
  196. }
  197. val = 0x4 | action;
  198. /* pull up/down */
  199. vlv_gpio_nc_write(dev_priv, pad, val);
  200. mutex_unlock(&dev_priv->sb_lock);
  201. out:
  202. return data;
  203. }
  204. typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
  205. const u8 *data);
  206. static const fn_mipi_elem_exec exec_elem[] = {
  207. NULL, /* reserved */
  208. mipi_exec_send_packet,
  209. mipi_exec_delay,
  210. mipi_exec_gpio,
  211. NULL, /* status read; later */
  212. };
  213. /*
  214. * MIPI Sequence from VBT #53 parsing logic
  215. * We have already separated each seqence during bios parsing
  216. * Following is generic execution function for any sequence
  217. */
  218. static const char * const seq_name[] = {
  219. "UNDEFINED",
  220. "MIPI_SEQ_ASSERT_RESET",
  221. "MIPI_SEQ_INIT_OTP",
  222. "MIPI_SEQ_DISPLAY_ON",
  223. "MIPI_SEQ_DISPLAY_OFF",
  224. "MIPI_SEQ_DEASSERT_RESET"
  225. };
  226. static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
  227. {
  228. fn_mipi_elem_exec mipi_elem_exec;
  229. int index;
  230. if (!data)
  231. return;
  232. DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
  233. /* go to the first element of the sequence */
  234. data++;
  235. /* parse each byte till we reach end of sequence byte - 0x00 */
  236. while (1) {
  237. index = *data;
  238. mipi_elem_exec = exec_elem[index];
  239. if (!mipi_elem_exec) {
  240. DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
  241. return;
  242. }
  243. /* goto element payload */
  244. data++;
  245. /* execute the element specific rotines */
  246. data = mipi_elem_exec(intel_dsi, data);
  247. /*
  248. * After processing the element, data should point to
  249. * next element or end of sequence
  250. * check if have we reached end of sequence
  251. */
  252. if (*data == 0x00)
  253. break;
  254. }
  255. }
  256. static int vbt_panel_prepare(struct drm_panel *panel)
  257. {
  258. struct vbt_panel *vbt_panel = to_vbt_panel(panel);
  259. struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
  260. struct drm_device *dev = intel_dsi->base.base.dev;
  261. struct drm_i915_private *dev_priv = dev->dev_private;
  262. const u8 *sequence;
  263. sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
  264. generic_exec_sequence(intel_dsi, sequence);
  265. sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
  266. generic_exec_sequence(intel_dsi, sequence);
  267. return 0;
  268. }
  269. static int vbt_panel_unprepare(struct drm_panel *panel)
  270. {
  271. struct vbt_panel *vbt_panel = to_vbt_panel(panel);
  272. struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
  273. struct drm_device *dev = intel_dsi->base.base.dev;
  274. struct drm_i915_private *dev_priv = dev->dev_private;
  275. const u8 *sequence;
  276. sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
  277. generic_exec_sequence(intel_dsi, sequence);
  278. return 0;
  279. }
  280. static int vbt_panel_enable(struct drm_panel *panel)
  281. {
  282. struct vbt_panel *vbt_panel = to_vbt_panel(panel);
  283. struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
  284. struct drm_device *dev = intel_dsi->base.base.dev;
  285. struct drm_i915_private *dev_priv = dev->dev_private;
  286. const u8 *sequence;
  287. sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
  288. generic_exec_sequence(intel_dsi, sequence);
  289. return 0;
  290. }
  291. static int vbt_panel_disable(struct drm_panel *panel)
  292. {
  293. struct vbt_panel *vbt_panel = to_vbt_panel(panel);
  294. struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
  295. struct drm_device *dev = intel_dsi->base.base.dev;
  296. struct drm_i915_private *dev_priv = dev->dev_private;
  297. const u8 *sequence;
  298. sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
  299. generic_exec_sequence(intel_dsi, sequence);
  300. return 0;
  301. }
  302. static int vbt_panel_get_modes(struct drm_panel *panel)
  303. {
  304. struct vbt_panel *vbt_panel = to_vbt_panel(panel);
  305. struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
  306. struct drm_device *dev = intel_dsi->base.base.dev;
  307. struct drm_i915_private *dev_priv = dev->dev_private;
  308. struct drm_display_mode *mode;
  309. if (!panel->connector)
  310. return 0;
  311. mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
  312. if (!mode)
  313. return 0;
  314. mode->type |= DRM_MODE_TYPE_PREFERRED;
  315. drm_mode_probed_add(panel->connector, mode);
  316. return 1;
  317. }
  318. static const struct drm_panel_funcs vbt_panel_funcs = {
  319. .disable = vbt_panel_disable,
  320. .unprepare = vbt_panel_unprepare,
  321. .prepare = vbt_panel_prepare,
  322. .enable = vbt_panel_enable,
  323. .get_modes = vbt_panel_get_modes,
  324. };
  325. struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
  326. {
  327. struct drm_device *dev = intel_dsi->base.base.dev;
  328. struct drm_i915_private *dev_priv = dev->dev_private;
  329. struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
  330. struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
  331. struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
  332. struct vbt_panel *vbt_panel;
  333. u32 bits_per_pixel = 24;
  334. u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
  335. u32 ui_num, ui_den;
  336. u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
  337. u32 ths_prepare_ns, tclk_trail_ns;
  338. u32 tclk_prepare_clkzero, ths_prepare_hszero;
  339. u32 lp_to_hs_switch, hs_to_lp_switch;
  340. u32 pclk, computed_ddr;
  341. u16 burst_mode_ratio;
  342. enum port port;
  343. DRM_DEBUG_KMS("\n");
  344. intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
  345. intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
  346. intel_dsi->lane_count = mipi_config->lane_cnt + 1;
  347. intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
  348. intel_dsi->dual_link = mipi_config->dual_link;
  349. intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
  350. if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
  351. bits_per_pixel = 18;
  352. else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
  353. bits_per_pixel = 16;
  354. intel_dsi->operation_mode = mipi_config->is_cmd_mode;
  355. intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
  356. intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
  357. intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
  358. intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
  359. intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
  360. intel_dsi->init_count = mipi_config->master_init_timer;
  361. intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
  362. intel_dsi->video_frmt_cfg_bits =
  363. mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
  364. pclk = mode->clock;
  365. /* In dual link mode each port needs half of pixel clock */
  366. if (intel_dsi->dual_link) {
  367. pclk = pclk / 2;
  368. /* we can enable pixel_overlap if needed by panel. In this
  369. * case we need to increase the pixelclock for extra pixels
  370. */
  371. if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
  372. pclk += DIV_ROUND_UP(mode->vtotal *
  373. intel_dsi->pixel_overlap *
  374. 60, 1000);
  375. }
  376. }
  377. /* Burst Mode Ratio
  378. * Target ddr frequency from VBT / non burst ddr freq
  379. * multiply by 100 to preserve remainder
  380. */
  381. if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
  382. if (mipi_config->target_burst_mode_freq) {
  383. computed_ddr =
  384. (pclk * bits_per_pixel) / intel_dsi->lane_count;
  385. if (mipi_config->target_burst_mode_freq <
  386. computed_ddr) {
  387. DRM_ERROR("Burst mode freq is less than computed\n");
  388. return NULL;
  389. }
  390. burst_mode_ratio = DIV_ROUND_UP(
  391. mipi_config->target_burst_mode_freq * 100,
  392. computed_ddr);
  393. pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
  394. } else {
  395. DRM_ERROR("Burst mode target is not set\n");
  396. return NULL;
  397. }
  398. } else
  399. burst_mode_ratio = 100;
  400. intel_dsi->burst_mode_ratio = burst_mode_ratio;
  401. intel_dsi->pclk = pclk;
  402. bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
  403. switch (intel_dsi->escape_clk_div) {
  404. case 0:
  405. tlpx_ns = 50;
  406. break;
  407. case 1:
  408. tlpx_ns = 100;
  409. break;
  410. case 2:
  411. tlpx_ns = 200;
  412. break;
  413. default:
  414. tlpx_ns = 50;
  415. break;
  416. }
  417. switch (intel_dsi->lane_count) {
  418. case 1:
  419. case 2:
  420. extra_byte_count = 2;
  421. break;
  422. case 3:
  423. extra_byte_count = 4;
  424. break;
  425. case 4:
  426. default:
  427. extra_byte_count = 3;
  428. break;
  429. }
  430. /*
  431. * ui(s) = 1/f [f in hz]
  432. * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
  433. */
  434. /* in Kbps */
  435. ui_num = NS_KHZ_RATIO;
  436. ui_den = bitrate;
  437. tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
  438. ths_prepare_hszero = mipi_config->ths_prepare_hszero;
  439. /*
  440. * B060
  441. * LP byte clock = TLPX/ (8UI)
  442. */
  443. intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
  444. /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
  445. *
  446. * Since txddrclkhs_i is 2xUI, all the count values programmed in
  447. * DPHY param register are divided by 2
  448. *
  449. * prepare count
  450. */
  451. ths_prepare_ns = max(mipi_config->ths_prepare,
  452. mipi_config->tclk_prepare);
  453. prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
  454. /* exit zero count */
  455. exit_zero_cnt = DIV_ROUND_UP(
  456. (ths_prepare_hszero - ths_prepare_ns) * ui_den,
  457. ui_num * 2
  458. );
  459. /*
  460. * Exit zero is unified val ths_zero and ths_exit
  461. * minimum value for ths_exit = 110ns
  462. * min (exit_zero_cnt * 2) = 110/UI
  463. * exit_zero_cnt = 55/UI
  464. */
  465. if (exit_zero_cnt < (55 * ui_den / ui_num))
  466. if ((55 * ui_den) % ui_num)
  467. exit_zero_cnt += 1;
  468. /* clk zero count */
  469. clk_zero_cnt = DIV_ROUND_UP(
  470. (tclk_prepare_clkzero - ths_prepare_ns)
  471. * ui_den, 2 * ui_num);
  472. /* trail count */
  473. tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
  474. trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
  475. if (prepare_cnt > PREPARE_CNT_MAX ||
  476. exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
  477. clk_zero_cnt > CLK_ZERO_CNT_MAX ||
  478. trail_cnt > TRAIL_CNT_MAX)
  479. DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
  480. if (prepare_cnt > PREPARE_CNT_MAX)
  481. prepare_cnt = PREPARE_CNT_MAX;
  482. if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
  483. exit_zero_cnt = EXIT_ZERO_CNT_MAX;
  484. if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
  485. clk_zero_cnt = CLK_ZERO_CNT_MAX;
  486. if (trail_cnt > TRAIL_CNT_MAX)
  487. trail_cnt = TRAIL_CNT_MAX;
  488. /* B080 */
  489. intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
  490. clk_zero_cnt << 8 | prepare_cnt;
  491. /*
  492. * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
  493. * + 10UI + Extra Byte Count
  494. *
  495. * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
  496. * Extra Byte Count is calculated according to number of lanes.
  497. * High Low Switch Count is the Max of LP to HS and
  498. * HS to LP switch count
  499. *
  500. */
  501. tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
  502. /* B044 */
  503. /* FIXME:
  504. * The comment above does not match with the code */
  505. lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
  506. exit_zero_cnt * 2 + 10, 8);
  507. hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
  508. intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
  509. intel_dsi->hs_to_lp_count += extra_byte_count;
  510. /* B088 */
  511. /* LP -> HS for clock lanes
  512. * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
  513. * extra byte count
  514. * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
  515. * 2(in UI) + extra byte count
  516. * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
  517. * 8 + extra byte count
  518. */
  519. intel_dsi->clk_lp_to_hs_count =
  520. DIV_ROUND_UP(
  521. 4 * tlpx_ui + prepare_cnt * 2 +
  522. clk_zero_cnt * 2,
  523. 8);
  524. intel_dsi->clk_lp_to_hs_count += extra_byte_count;
  525. /* HS->LP for Clock Lanes
  526. * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
  527. * Extra byte count
  528. * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
  529. * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
  530. * Extra byte count
  531. */
  532. intel_dsi->clk_hs_to_lp_count =
  533. DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
  534. 8);
  535. intel_dsi->clk_hs_to_lp_count += extra_byte_count;
  536. DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
  537. DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
  538. "disabled" : "enabled");
  539. DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
  540. if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
  541. DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
  542. else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
  543. DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
  544. else
  545. DRM_DEBUG_KMS("Dual link: NONE\n");
  546. DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
  547. DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
  548. DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
  549. DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
  550. DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
  551. DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
  552. DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
  553. DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
  554. DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
  555. DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
  556. DRM_DEBUG_KMS("BTA %s\n",
  557. intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
  558. "disabled" : "enabled");
  559. /* delays in VBT are in unit of 100us, so need to convert
  560. * here in ms
  561. * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
  562. intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
  563. intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
  564. intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
  565. intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
  566. intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
  567. /* This is cheating a bit with the cleanup. */
  568. vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
  569. vbt_panel->intel_dsi = intel_dsi;
  570. drm_panel_init(&vbt_panel->panel);
  571. vbt_panel->panel.funcs = &vbt_panel_funcs;
  572. drm_panel_add(&vbt_panel->panel);
  573. /* a regular driver would get the device in probe */
  574. for_each_dsi_port(port, intel_dsi->ports) {
  575. mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
  576. }
  577. return &vbt_panel->panel;
  578. }