intel_sideband.c 7.6 KB

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  1. /*
  2. * Copyright © 2013 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #include "i915_drv.h"
  25. #include "intel_drv.h"
  26. /*
  27. * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
  28. * VLV_VLV2_PUNIT_HAS_0.8.docx
  29. */
  30. /* Standard MMIO read, non-posted */
  31. #define SB_MRD_NP 0x00
  32. /* Standard MMIO write, non-posted */
  33. #define SB_MWR_NP 0x01
  34. /* Private register read, double-word addressing, non-posted */
  35. #define SB_CRRDDA_NP 0x06
  36. /* Private register write, double-word addressing, non-posted */
  37. #define SB_CRWRDA_NP 0x07
  38. static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
  39. u32 port, u32 opcode, u32 addr, u32 *val)
  40. {
  41. u32 cmd, be = 0xf, bar = 0;
  42. bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
  43. cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
  44. (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
  45. (bar << IOSF_BAR_SHIFT);
  46. WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
  47. if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
  48. DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
  49. is_read ? "read" : "write");
  50. return -EAGAIN;
  51. }
  52. I915_WRITE(VLV_IOSF_ADDR, addr);
  53. if (!is_read)
  54. I915_WRITE(VLV_IOSF_DATA, *val);
  55. I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
  56. if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
  57. DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
  58. is_read ? "read" : "write");
  59. return -ETIMEDOUT;
  60. }
  61. if (is_read)
  62. *val = I915_READ(VLV_IOSF_DATA);
  63. I915_WRITE(VLV_IOSF_DATA, 0);
  64. return 0;
  65. }
  66. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
  67. {
  68. u32 val = 0;
  69. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  70. mutex_lock(&dev_priv->sb_lock);
  71. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
  72. SB_CRRDDA_NP, addr, &val);
  73. mutex_unlock(&dev_priv->sb_lock);
  74. return val;
  75. }
  76. void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
  77. {
  78. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  79. mutex_lock(&dev_priv->sb_lock);
  80. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
  81. SB_CRWRDA_NP, addr, &val);
  82. mutex_unlock(&dev_priv->sb_lock);
  83. }
  84. u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
  85. {
  86. u32 val = 0;
  87. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
  88. SB_CRRDDA_NP, reg, &val);
  89. return val;
  90. }
  91. void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  92. {
  93. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
  94. SB_CRWRDA_NP, reg, &val);
  95. }
  96. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
  97. {
  98. u32 val = 0;
  99. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  100. mutex_lock(&dev_priv->sb_lock);
  101. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
  102. SB_CRRDDA_NP, addr, &val);
  103. mutex_unlock(&dev_priv->sb_lock);
  104. return val;
  105. }
  106. u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
  107. {
  108. u32 val = 0;
  109. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
  110. SB_CRRDDA_NP, reg, &val);
  111. return val;
  112. }
  113. void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  114. {
  115. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPIO_NC,
  116. SB_CRWRDA_NP, reg, &val);
  117. }
  118. u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
  119. {
  120. u32 val = 0;
  121. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
  122. SB_CRRDDA_NP, reg, &val);
  123. return val;
  124. }
  125. void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  126. {
  127. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
  128. SB_CRWRDA_NP, reg, &val);
  129. }
  130. u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
  131. {
  132. u32 val = 0;
  133. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
  134. SB_CRRDDA_NP, reg, &val);
  135. return val;
  136. }
  137. void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  138. {
  139. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
  140. SB_CRWRDA_NP, reg, &val);
  141. }
  142. u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
  143. {
  144. u32 val = 0;
  145. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
  146. SB_CRRDDA_NP, reg, &val);
  147. return val;
  148. }
  149. void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  150. {
  151. vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_GPS_CORE,
  152. SB_CRWRDA_NP, reg, &val);
  153. }
  154. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
  155. {
  156. u32 val = 0;
  157. vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
  158. SB_MRD_NP, reg, &val);
  159. /*
  160. * FIXME: There might be some registers where all 1's is a valid value,
  161. * so ideally we should check the register offset instead...
  162. */
  163. WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
  164. pipe_name(pipe), reg, val);
  165. return val;
  166. }
  167. void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
  168. {
  169. vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
  170. SB_MWR_NP, reg, &val);
  171. }
  172. /* SBI access */
  173. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  174. enum intel_sbi_destination destination)
  175. {
  176. u32 value = 0;
  177. WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
  178. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  179. 100)) {
  180. DRM_ERROR("timeout waiting for SBI to become ready\n");
  181. return 0;
  182. }
  183. I915_WRITE(SBI_ADDR, (reg << 16));
  184. if (destination == SBI_ICLK)
  185. value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
  186. else
  187. value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
  188. I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
  189. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  190. 100)) {
  191. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  192. return 0;
  193. }
  194. return I915_READ(SBI_DATA);
  195. }
  196. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  197. enum intel_sbi_destination destination)
  198. {
  199. u32 tmp;
  200. WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
  201. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  202. 100)) {
  203. DRM_ERROR("timeout waiting for SBI to become ready\n");
  204. return;
  205. }
  206. I915_WRITE(SBI_ADDR, (reg << 16));
  207. I915_WRITE(SBI_DATA, value);
  208. if (destination == SBI_ICLK)
  209. tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
  210. else
  211. tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
  212. I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
  213. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  214. 100)) {
  215. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  216. return;
  217. }
  218. }
  219. u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
  220. {
  221. u32 val = 0;
  222. vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
  223. reg, &val);
  224. return val;
  225. }
  226. void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  227. {
  228. vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
  229. reg, &val);
  230. }