NOTES 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. NOTES about msm drm/kms driver:
  2. In the current snapdragon SoC's, we have (at least) 3 different
  3. display controller blocks at play:
  4. + MDP3 - ?? seems to be what is on geeksphone peak device
  5. + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
  6. + MDP5 - snapdragon 800
  7. (I don't have a completely clear picture on which display controller
  8. maps to which part #)
  9. Plus a handful of blocks around them for HDMI/DSI/etc output.
  10. And on gpu side of things:
  11. + zero, one, or two 2d cores (z180)
  12. + and either a2xx or a3xx 3d core.
  13. But, HDMI/DSI/etc blocks seem like they can be shared across multiple
  14. display controller blocks. And I for sure don't want to have to deal
  15. with N different kms devices from xf86-video-freedreno. Plus, it
  16. seems like we can do some clever tricks like use GPU to trigger
  17. pageflip after rendering completes (ie. have the kms/crtc code build
  18. up gpu cmdstream to update scanout and write FLUSH register after).
  19. So, the approach is one drm driver, with some modularity. Different
  20. 'struct msm_kms' implementations, depending on display controller.
  21. And one or more 'struct msm_gpu' for the various different gpu sub-
  22. modules.
  23. (Second part is not implemented yet. So far this is just basic KMS
  24. driver, and not exposing any custom ioctls to userspace for now.)
  25. The kms module provides the plane, crtc, and encoder objects, and
  26. loads whatever connectors are appropriate.
  27. For MDP4, the mapping is:
  28. plane -> PIPE{RGBn,VGn} \
  29. crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
  30. encoder -> DTV/LCDC/DSI (within MDP4) /
  31. connector -> HDMI/DSI/etc --> other device(s)
  32. Since the irq's that drm core mostly cares about are vblank/framedone,
  33. we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions
  34. and treat the MDP4 block's irq as "the" irq. Even though the connectors
  35. may have their own irqs which they install themselves. For this reason
  36. the display controller is the "master" device.
  37. For MDP5, the mapping is:
  38. plane -> PIPE{RGBn,VIGn} \
  39. crtc -> LM (layer mixer) |-> MDP "device"
  40. encoder -> INTF /
  41. connector -> HDMI/DSI/eDP/etc --> other device(s)
  42. Unlike MDP4, it appears we can get by with a single encoder, rather
  43. than needing a different implementation for DTV, DSI, etc. (Ie. the
  44. register interface is same, just different bases.)
  45. Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
  46. etc) are routed through MDP.
  47. And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
  48. which blocks need to be allocated to the active pipes based on fetch
  49. stride.
  50. Each connector probably ends up being a separate device, just for the
  51. logistics of finding/mapping io region, irq, etc. Idealy we would
  52. have a better way than just stashing the platform device in a global
  53. (ie. like DT super-node.. but I don't have any snapdragon hw yet that
  54. is using DT).
  55. Note that so far I've not been able to get any docs on the hw, and it
  56. seems that access to such docs would prevent me from working on the
  57. freedreno gallium driver. So there may be some mistakes in register
  58. names (I had to invent a few, since no sufficient hint was given in
  59. the downstream android fbdev driver), bitfield sizes, etc. My current
  60. state of understanding the registers is given in the envytools rnndb
  61. files at:
  62. https://github.com/freedreno/envytools/tree/master/rnndb
  63. (the mdp4/hdmi/dsi directories)
  64. These files are used both for a parser tool (in the same tree) to
  65. parse logged register reads/writes (both from downstream android fbdev
  66. driver, and this driver with register logging enabled), as well as to
  67. generate the register level headers.