adreno_gpu.h 8.4 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __ADRENO_GPU_H__
  20. #define __ADRENO_GPU_H__
  21. #include <linux/firmware.h>
  22. #include "msm_gpu.h"
  23. #include "adreno_common.xml.h"
  24. #include "adreno_pm4.xml.h"
  25. #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
  26. /**
  27. * adreno_regs: List of registers that are used in across all
  28. * 3D devices. Each device type has different offset value for the same
  29. * register, so an array of register offsets are declared for every device
  30. * and are indexed by the enumeration values defined in this enum
  31. */
  32. enum adreno_regs {
  33. REG_ADRENO_CP_DEBUG,
  34. REG_ADRENO_CP_ME_RAM_WADDR,
  35. REG_ADRENO_CP_ME_RAM_DATA,
  36. REG_ADRENO_CP_PFP_UCODE_DATA,
  37. REG_ADRENO_CP_PFP_UCODE_ADDR,
  38. REG_ADRENO_CP_WFI_PEND_CTR,
  39. REG_ADRENO_CP_RB_BASE,
  40. REG_ADRENO_CP_RB_RPTR_ADDR,
  41. REG_ADRENO_CP_RB_RPTR,
  42. REG_ADRENO_CP_RB_WPTR,
  43. REG_ADRENO_CP_PROTECT_CTRL,
  44. REG_ADRENO_CP_ME_CNTL,
  45. REG_ADRENO_CP_RB_CNTL,
  46. REG_ADRENO_CP_IB1_BASE,
  47. REG_ADRENO_CP_IB1_BUFSZ,
  48. REG_ADRENO_CP_IB2_BASE,
  49. REG_ADRENO_CP_IB2_BUFSZ,
  50. REG_ADRENO_CP_TIMESTAMP,
  51. REG_ADRENO_CP_ME_RAM_RADDR,
  52. REG_ADRENO_CP_ROQ_ADDR,
  53. REG_ADRENO_CP_ROQ_DATA,
  54. REG_ADRENO_CP_MERCIU_ADDR,
  55. REG_ADRENO_CP_MERCIU_DATA,
  56. REG_ADRENO_CP_MERCIU_DATA2,
  57. REG_ADRENO_CP_MEQ_ADDR,
  58. REG_ADRENO_CP_MEQ_DATA,
  59. REG_ADRENO_CP_HW_FAULT,
  60. REG_ADRENO_CP_PROTECT_STATUS,
  61. REG_ADRENO_SCRATCH_ADDR,
  62. REG_ADRENO_SCRATCH_UMSK,
  63. REG_ADRENO_SCRATCH_REG2,
  64. REG_ADRENO_RBBM_STATUS,
  65. REG_ADRENO_RBBM_PERFCTR_CTL,
  66. REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
  67. REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
  68. REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
  69. REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
  70. REG_ADRENO_RBBM_INT_0_MASK,
  71. REG_ADRENO_RBBM_INT_0_STATUS,
  72. REG_ADRENO_RBBM_AHB_ERROR_STATUS,
  73. REG_ADRENO_RBBM_PM_OVERRIDE2,
  74. REG_ADRENO_RBBM_AHB_CMD,
  75. REG_ADRENO_RBBM_INT_CLEAR_CMD,
  76. REG_ADRENO_RBBM_SW_RESET_CMD,
  77. REG_ADRENO_RBBM_CLOCK_CTL,
  78. REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
  79. REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
  80. REG_ADRENO_VPC_DEBUG_RAM_SEL,
  81. REG_ADRENO_VPC_DEBUG_RAM_READ,
  82. REG_ADRENO_VSC_SIZE_ADDRESS,
  83. REG_ADRENO_VFD_CONTROL_0,
  84. REG_ADRENO_VFD_INDEX_MAX,
  85. REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
  86. REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
  87. REG_ADRENO_SP_VS_OBJ_START_REG,
  88. REG_ADRENO_SP_FS_OBJ_START_REG,
  89. REG_ADRENO_PA_SC_AA_CONFIG,
  90. REG_ADRENO_SQ_GPR_MANAGEMENT,
  91. REG_ADRENO_SQ_INST_STORE_MANAGMENT,
  92. REG_ADRENO_TP0_CHICKEN,
  93. REG_ADRENO_RBBM_RBBM_CTL,
  94. REG_ADRENO_UCHE_INVALIDATE0,
  95. REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
  96. REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
  97. REG_ADRENO_REGISTER_MAX,
  98. };
  99. struct adreno_rev {
  100. uint8_t core;
  101. uint8_t major;
  102. uint8_t minor;
  103. uint8_t patchid;
  104. };
  105. #define ADRENO_REV(core, major, minor, patchid) \
  106. ((struct adreno_rev){ core, major, minor, patchid })
  107. struct adreno_gpu_funcs {
  108. struct msm_gpu_funcs base;
  109. };
  110. struct adreno_info {
  111. struct adreno_rev rev;
  112. uint32_t revn;
  113. const char *name;
  114. const char *pm4fw, *pfpfw;
  115. uint32_t gmem;
  116. struct msm_gpu *(*init)(struct drm_device *dev);
  117. };
  118. const struct adreno_info *adreno_info(struct adreno_rev rev);
  119. struct adreno_rbmemptrs {
  120. volatile uint32_t rptr;
  121. volatile uint32_t wptr;
  122. volatile uint32_t fence;
  123. };
  124. struct adreno_gpu {
  125. struct msm_gpu base;
  126. struct adreno_rev rev;
  127. const struct adreno_info *info;
  128. uint32_t gmem; /* actual gmem size */
  129. uint32_t revn; /* numeric revision name */
  130. const struct adreno_gpu_funcs *funcs;
  131. /* interesting register offsets to dump: */
  132. const unsigned int *registers;
  133. /* firmware: */
  134. const struct firmware *pm4, *pfp;
  135. /* ringbuffer rptr/wptr: */
  136. // TODO should this be in msm_ringbuffer? I think it would be
  137. // different for z180..
  138. struct adreno_rbmemptrs *memptrs;
  139. struct drm_gem_object *memptrs_bo;
  140. uint32_t memptrs_iova;
  141. /*
  142. * Register offsets are different between some GPUs.
  143. * GPU specific offsets will be exported by GPU specific
  144. * code (a3xx_gpu.c) and stored in this common location.
  145. */
  146. const unsigned int *reg_offsets;
  147. };
  148. #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
  149. /* platform config data (ie. from DT, or pdata) */
  150. struct adreno_platform_config {
  151. struct adreno_rev rev;
  152. uint32_t fast_rate, slow_rate, bus_freq;
  153. #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
  154. struct msm_bus_scale_pdata *bus_scale_table;
  155. #endif
  156. };
  157. #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
  158. #define spin_until(X) ({ \
  159. int __ret = -ETIMEDOUT; \
  160. unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
  161. do { \
  162. if (X) { \
  163. __ret = 0; \
  164. break; \
  165. } \
  166. } while (time_before(jiffies, __t)); \
  167. __ret; \
  168. })
  169. static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
  170. {
  171. return (gpu->revn >= 300) && (gpu->revn < 400);
  172. }
  173. static inline bool adreno_is_a305(struct adreno_gpu *gpu)
  174. {
  175. return gpu->revn == 305;
  176. }
  177. static inline bool adreno_is_a306(struct adreno_gpu *gpu)
  178. {
  179. /* yes, 307, because a305c is 306 */
  180. return gpu->revn == 307;
  181. }
  182. static inline bool adreno_is_a320(struct adreno_gpu *gpu)
  183. {
  184. return gpu->revn == 320;
  185. }
  186. static inline bool adreno_is_a330(struct adreno_gpu *gpu)
  187. {
  188. return gpu->revn == 330;
  189. }
  190. static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
  191. {
  192. return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
  193. }
  194. static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
  195. {
  196. return (gpu->revn >= 400) && (gpu->revn < 500);
  197. }
  198. static inline int adreno_is_a420(struct adreno_gpu *gpu)
  199. {
  200. return gpu->revn == 420;
  201. }
  202. int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
  203. int adreno_hw_init(struct msm_gpu *gpu);
  204. uint32_t adreno_last_fence(struct msm_gpu *gpu);
  205. void adreno_recover(struct msm_gpu *gpu);
  206. int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
  207. struct msm_file_private *ctx);
  208. void adreno_flush(struct msm_gpu *gpu);
  209. void adreno_idle(struct msm_gpu *gpu);
  210. #ifdef CONFIG_DEBUG_FS
  211. void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
  212. #endif
  213. void adreno_dump_info(struct msm_gpu *gpu);
  214. void adreno_dump(struct msm_gpu *gpu);
  215. void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
  216. int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
  217. struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
  218. void adreno_gpu_cleanup(struct adreno_gpu *gpu);
  219. /* ringbuffer helpers (the parts that are adreno specific) */
  220. static inline void
  221. OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
  222. {
  223. adreno_wait_ring(ring->gpu, cnt+1);
  224. OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
  225. }
  226. /* no-op packet: */
  227. static inline void
  228. OUT_PKT2(struct msm_ringbuffer *ring)
  229. {
  230. adreno_wait_ring(ring->gpu, 1);
  231. OUT_RING(ring, CP_TYPE2_PKT);
  232. }
  233. static inline void
  234. OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
  235. {
  236. adreno_wait_ring(ring->gpu, cnt+1);
  237. OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
  238. }
  239. /*
  240. * adreno_checkreg_off() - Checks the validity of a register enum
  241. * @gpu: Pointer to struct adreno_gpu
  242. * @offset_name: The register enum that is checked
  243. */
  244. static inline bool adreno_reg_check(struct adreno_gpu *gpu,
  245. enum adreno_regs offset_name)
  246. {
  247. if (offset_name >= REG_ADRENO_REGISTER_MAX ||
  248. !gpu->reg_offsets[offset_name]) {
  249. BUG();
  250. }
  251. return true;
  252. }
  253. static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
  254. enum adreno_regs offset_name)
  255. {
  256. u32 reg = gpu->reg_offsets[offset_name];
  257. u32 val = 0;
  258. if(adreno_reg_check(gpu,offset_name))
  259. val = gpu_read(&gpu->base, reg - 1);
  260. return val;
  261. }
  262. static inline void adreno_gpu_write(struct adreno_gpu *gpu,
  263. enum adreno_regs offset_name, u32 data)
  264. {
  265. u32 reg = gpu->reg_offsets[offset_name];
  266. if(adreno_reg_check(gpu, offset_name))
  267. gpu_write(&gpu->base, reg - 1, data);
  268. }
  269. #endif /* __ADRENO_GPU_H__ */