omap_crtc.c 14 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_plane_helper.h>
  25. #include "omap_drv.h"
  26. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  27. struct omap_crtc {
  28. struct drm_crtc base;
  29. const char *name;
  30. enum omap_channel channel;
  31. /*
  32. * Temporary: eventually this will go away, but it is needed
  33. * for now to keep the output's happy. (They only need
  34. * mgr->id.) Eventually this will be replaced w/ something
  35. * more common-panel-framework-y
  36. */
  37. struct omap_overlay_manager *mgr;
  38. struct omap_video_timings timings;
  39. struct omap_drm_irq vblank_irq;
  40. struct omap_drm_irq error_irq;
  41. bool ignore_digit_sync_lost;
  42. bool pending;
  43. wait_queue_head_t pending_wait;
  44. };
  45. /* -----------------------------------------------------------------------------
  46. * Helper Functions
  47. */
  48. uint32_t pipe2vbl(struct drm_crtc *crtc)
  49. {
  50. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  51. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  52. }
  53. struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  54. {
  55. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  56. return &omap_crtc->timings;
  57. }
  58. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  59. {
  60. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  61. return omap_crtc->channel;
  62. }
  63. int omap_crtc_wait_pending(struct drm_crtc *crtc)
  64. {
  65. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  66. return wait_event_timeout(omap_crtc->pending_wait,
  67. !omap_crtc->pending,
  68. msecs_to_jiffies(50));
  69. }
  70. /* -----------------------------------------------------------------------------
  71. * DSS Manager Functions
  72. */
  73. /*
  74. * Manager-ops, callbacks from output when they need to configure
  75. * the upstream part of the video pipe.
  76. *
  77. * Most of these we can ignore until we add support for command-mode
  78. * panels.. for video-mode the crtc-helpers already do an adequate
  79. * job of sequencing the setup of the video pipe in the proper order
  80. */
  81. /* ovl-mgr-id -> crtc */
  82. static struct omap_crtc *omap_crtcs[8];
  83. /* we can probably ignore these until we support command-mode panels: */
  84. static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
  85. struct omap_dss_device *dst)
  86. {
  87. if (mgr->output)
  88. return -EINVAL;
  89. if ((mgr->supported_outputs & dst->id) == 0)
  90. return -EINVAL;
  91. dst->manager = mgr;
  92. mgr->output = dst;
  93. return 0;
  94. }
  95. static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
  96. struct omap_dss_device *dst)
  97. {
  98. mgr->output->manager = NULL;
  99. mgr->output = NULL;
  100. }
  101. static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
  102. {
  103. }
  104. /* Called only from the encoder enable/disable and suspend/resume handlers. */
  105. static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
  106. {
  107. struct drm_device *dev = crtc->dev;
  108. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  109. enum omap_channel channel = omap_crtc->channel;
  110. struct omap_irq_wait *wait;
  111. u32 framedone_irq, vsync_irq;
  112. int ret;
  113. if (dispc_mgr_is_enabled(channel) == enable)
  114. return;
  115. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  116. /*
  117. * Digit output produces some sync lost interrupts during the
  118. * first frame when enabling, so we need to ignore those.
  119. */
  120. omap_crtc->ignore_digit_sync_lost = true;
  121. }
  122. framedone_irq = dispc_mgr_get_framedone_irq(channel);
  123. vsync_irq = dispc_mgr_get_vsync_irq(channel);
  124. if (enable) {
  125. wait = omap_irq_wait_init(dev, vsync_irq, 1);
  126. } else {
  127. /*
  128. * When we disable the digit output, we need to wait for
  129. * FRAMEDONE to know that DISPC has finished with the output.
  130. *
  131. * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
  132. * that case we need to use vsync interrupt, and wait for both
  133. * even and odd frames.
  134. */
  135. if (framedone_irq)
  136. wait = omap_irq_wait_init(dev, framedone_irq, 1);
  137. else
  138. wait = omap_irq_wait_init(dev, vsync_irq, 2);
  139. }
  140. dispc_mgr_enable(channel, enable);
  141. ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  142. if (ret) {
  143. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  144. omap_crtc->name, enable ? "enable" : "disable");
  145. }
  146. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  147. omap_crtc->ignore_digit_sync_lost = false;
  148. /* make sure the irq handler sees the value above */
  149. mb();
  150. }
  151. }
  152. static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
  153. {
  154. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  155. struct omap_overlay_manager_info info;
  156. memset(&info, 0, sizeof(info));
  157. info.default_color = 0x00000000;
  158. info.trans_key = 0x00000000;
  159. info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  160. info.trans_enabled = false;
  161. dispc_mgr_setup(omap_crtc->channel, &info);
  162. dispc_mgr_set_timings(omap_crtc->channel,
  163. &omap_crtc->timings);
  164. omap_crtc_set_enabled(&omap_crtc->base, true);
  165. return 0;
  166. }
  167. static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
  168. {
  169. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  170. omap_crtc_set_enabled(&omap_crtc->base, false);
  171. }
  172. static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
  173. const struct omap_video_timings *timings)
  174. {
  175. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  176. DBG("%s", omap_crtc->name);
  177. omap_crtc->timings = *timings;
  178. }
  179. static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
  180. const struct dss_lcd_mgr_config *config)
  181. {
  182. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  183. DBG("%s", omap_crtc->name);
  184. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  185. }
  186. static int omap_crtc_dss_register_framedone(
  187. struct omap_overlay_manager *mgr,
  188. void (*handler)(void *), void *data)
  189. {
  190. return 0;
  191. }
  192. static void omap_crtc_dss_unregister_framedone(
  193. struct omap_overlay_manager *mgr,
  194. void (*handler)(void *), void *data)
  195. {
  196. }
  197. static const struct dss_mgr_ops mgr_ops = {
  198. .connect = omap_crtc_dss_connect,
  199. .disconnect = omap_crtc_dss_disconnect,
  200. .start_update = omap_crtc_dss_start_update,
  201. .enable = omap_crtc_dss_enable,
  202. .disable = omap_crtc_dss_disable,
  203. .set_timings = omap_crtc_dss_set_timings,
  204. .set_lcd_config = omap_crtc_dss_set_lcd_config,
  205. .register_framedone_handler = omap_crtc_dss_register_framedone,
  206. .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
  207. };
  208. /* -----------------------------------------------------------------------------
  209. * Setup, Flush and Page Flip
  210. */
  211. static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
  212. {
  213. struct drm_pending_vblank_event *event;
  214. struct drm_device *dev = crtc->dev;
  215. unsigned long flags;
  216. event = crtc->state->event;
  217. if (!event)
  218. return;
  219. spin_lock_irqsave(&dev->event_lock, flags);
  220. list_del(&event->base.link);
  221. /*
  222. * Queue the event for delivery if it's still linked to a file
  223. * handle, otherwise just destroy it.
  224. */
  225. if (event->base.file_priv)
  226. drm_crtc_send_vblank_event(crtc, event);
  227. else
  228. event->base.destroy(&event->base);
  229. spin_unlock_irqrestore(&dev->event_lock, flags);
  230. }
  231. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  232. {
  233. struct omap_crtc *omap_crtc =
  234. container_of(irq, struct omap_crtc, error_irq);
  235. if (omap_crtc->ignore_digit_sync_lost) {
  236. irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  237. if (!irqstatus)
  238. return;
  239. }
  240. DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  241. }
  242. static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  243. {
  244. struct omap_crtc *omap_crtc =
  245. container_of(irq, struct omap_crtc, vblank_irq);
  246. struct drm_device *dev = omap_crtc->base.dev;
  247. if (dispc_mgr_go_busy(omap_crtc->channel))
  248. return;
  249. DBG("%s: apply done", omap_crtc->name);
  250. __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
  251. rmb();
  252. WARN_ON(!omap_crtc->pending);
  253. omap_crtc->pending = false;
  254. wmb();
  255. /* wake up userspace */
  256. omap_crtc_complete_page_flip(&omap_crtc->base);
  257. /* wake up omap_atomic_complete */
  258. wake_up(&omap_crtc->pending_wait);
  259. }
  260. /* -----------------------------------------------------------------------------
  261. * CRTC Functions
  262. */
  263. static void omap_crtc_destroy(struct drm_crtc *crtc)
  264. {
  265. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  266. DBG("%s", omap_crtc->name);
  267. WARN_ON(omap_crtc->vblank_irq.registered);
  268. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  269. drm_crtc_cleanup(crtc);
  270. kfree(omap_crtc);
  271. }
  272. static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
  273. const struct drm_display_mode *mode,
  274. struct drm_display_mode *adjusted_mode)
  275. {
  276. return true;
  277. }
  278. static void omap_crtc_enable(struct drm_crtc *crtc)
  279. {
  280. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  281. DBG("%s", omap_crtc->name);
  282. rmb();
  283. WARN_ON(omap_crtc->pending);
  284. omap_crtc->pending = true;
  285. wmb();
  286. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  287. drm_crtc_vblank_on(crtc);
  288. }
  289. static void omap_crtc_disable(struct drm_crtc *crtc)
  290. {
  291. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  292. DBG("%s", omap_crtc->name);
  293. drm_crtc_vblank_off(crtc);
  294. }
  295. static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
  296. {
  297. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  298. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  299. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  300. omap_crtc->name, mode->base.id, mode->name,
  301. mode->vrefresh, mode->clock,
  302. mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
  303. mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
  304. mode->type, mode->flags);
  305. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  306. }
  307. static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
  308. struct drm_crtc_state *old_crtc_state)
  309. {
  310. }
  311. static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
  312. struct drm_crtc_state *old_crtc_state)
  313. {
  314. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  315. WARN_ON(omap_crtc->vblank_irq.registered);
  316. if (dispc_mgr_is_enabled(omap_crtc->channel)) {
  317. DBG("%s: GO", omap_crtc->name);
  318. rmb();
  319. WARN_ON(omap_crtc->pending);
  320. omap_crtc->pending = true;
  321. wmb();
  322. dispc_mgr_go(omap_crtc->channel);
  323. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  324. }
  325. }
  326. static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
  327. struct drm_crtc_state *state,
  328. struct drm_property *property,
  329. uint64_t val)
  330. {
  331. struct drm_plane_state *plane_state;
  332. struct drm_plane *plane = crtc->primary;
  333. /*
  334. * Delegate property set to the primary plane. Get the plane state and
  335. * set the property directly.
  336. */
  337. plane_state = drm_atomic_get_plane_state(state->state, plane);
  338. if (!plane_state)
  339. return -EINVAL;
  340. return drm_atomic_plane_set_property(plane, plane_state, property, val);
  341. }
  342. static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
  343. const struct drm_crtc_state *state,
  344. struct drm_property *property,
  345. uint64_t *val)
  346. {
  347. /*
  348. * Delegate property get to the primary plane. The
  349. * drm_atomic_plane_get_property() function isn't exported, but can be
  350. * called through drm_object_property_get_value() as that will call
  351. * drm_atomic_get_property() for atomic drivers.
  352. */
  353. return drm_object_property_get_value(&crtc->primary->base, property,
  354. val);
  355. }
  356. static const struct drm_crtc_funcs omap_crtc_funcs = {
  357. .reset = drm_atomic_helper_crtc_reset,
  358. .set_config = drm_atomic_helper_set_config,
  359. .destroy = omap_crtc_destroy,
  360. .page_flip = drm_atomic_helper_page_flip,
  361. .set_property = drm_atomic_helper_crtc_set_property,
  362. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  363. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  364. .atomic_set_property = omap_crtc_atomic_set_property,
  365. .atomic_get_property = omap_crtc_atomic_get_property,
  366. };
  367. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  368. .mode_fixup = omap_crtc_mode_fixup,
  369. .mode_set_nofb = omap_crtc_mode_set_nofb,
  370. .disable = omap_crtc_disable,
  371. .enable = omap_crtc_enable,
  372. .atomic_begin = omap_crtc_atomic_begin,
  373. .atomic_flush = omap_crtc_atomic_flush,
  374. };
  375. /* -----------------------------------------------------------------------------
  376. * Init and Cleanup
  377. */
  378. static const char *channel_names[] = {
  379. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  380. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  381. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  382. [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
  383. };
  384. void omap_crtc_pre_init(void)
  385. {
  386. dss_install_mgr_ops(&mgr_ops);
  387. }
  388. void omap_crtc_pre_uninit(void)
  389. {
  390. dss_uninstall_mgr_ops();
  391. }
  392. /* initialize crtc */
  393. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  394. struct drm_plane *plane, enum omap_channel channel, int id)
  395. {
  396. struct drm_crtc *crtc = NULL;
  397. struct omap_crtc *omap_crtc;
  398. int ret;
  399. DBG("%s", channel_names[channel]);
  400. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  401. if (!omap_crtc)
  402. return NULL;
  403. crtc = &omap_crtc->base;
  404. init_waitqueue_head(&omap_crtc->pending_wait);
  405. omap_crtc->channel = channel;
  406. omap_crtc->name = channel_names[channel];
  407. omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
  408. omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
  409. omap_crtc->error_irq.irqmask =
  410. dispc_mgr_get_sync_lost_irq(channel);
  411. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  412. omap_irq_register(dev, &omap_crtc->error_irq);
  413. /* temporary: */
  414. omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
  415. ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  416. &omap_crtc_funcs);
  417. if (ret < 0) {
  418. kfree(omap_crtc);
  419. return NULL;
  420. }
  421. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  422. omap_plane_install_properties(crtc->primary, &crtc->base);
  423. omap_crtcs[channel] = omap_crtc;
  424. return crtc;
  425. }