rcar_du_crtc.c 18 KB

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  1. /*
  2. * rcar_du_crtc.c -- R-Car Display Unit CRTCs
  3. *
  4. * Copyright (C) 2013-2014 Renesas Electronics Corporation
  5. *
  6. * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/mutex.h>
  15. #include <drm/drmP.h>
  16. #include <drm/drm_atomic.h>
  17. #include <drm/drm_atomic_helper.h>
  18. #include <drm/drm_crtc.h>
  19. #include <drm/drm_crtc_helper.h>
  20. #include <drm/drm_fb_cma_helper.h>
  21. #include <drm/drm_gem_cma_helper.h>
  22. #include <drm/drm_plane_helper.h>
  23. #include "rcar_du_crtc.h"
  24. #include "rcar_du_drv.h"
  25. #include "rcar_du_kms.h"
  26. #include "rcar_du_plane.h"
  27. #include "rcar_du_regs.h"
  28. static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  29. {
  30. struct rcar_du_device *rcdu = rcrtc->group->dev;
  31. return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  32. }
  33. static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  34. {
  35. struct rcar_du_device *rcdu = rcrtc->group->dev;
  36. rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  37. }
  38. static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  39. {
  40. struct rcar_du_device *rcdu = rcrtc->group->dev;
  41. rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  42. rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  43. }
  44. static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  45. {
  46. struct rcar_du_device *rcdu = rcrtc->group->dev;
  47. rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  48. rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  49. }
  50. static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
  51. u32 clr, u32 set)
  52. {
  53. struct rcar_du_device *rcdu = rcrtc->group->dev;
  54. u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  55. rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
  56. }
  57. static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
  58. {
  59. int ret;
  60. ret = clk_prepare_enable(rcrtc->clock);
  61. if (ret < 0)
  62. return ret;
  63. ret = clk_prepare_enable(rcrtc->extclock);
  64. if (ret < 0)
  65. goto error_clock;
  66. ret = rcar_du_group_get(rcrtc->group);
  67. if (ret < 0)
  68. goto error_group;
  69. return 0;
  70. error_group:
  71. clk_disable_unprepare(rcrtc->extclock);
  72. error_clock:
  73. clk_disable_unprepare(rcrtc->clock);
  74. return ret;
  75. }
  76. static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
  77. {
  78. rcar_du_group_put(rcrtc->group);
  79. clk_disable_unprepare(rcrtc->extclock);
  80. clk_disable_unprepare(rcrtc->clock);
  81. }
  82. /* -----------------------------------------------------------------------------
  83. * Hardware Setup
  84. */
  85. static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
  86. {
  87. const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
  88. unsigned long mode_clock = mode->clock * 1000;
  89. unsigned long clk;
  90. u32 value;
  91. u32 escr;
  92. u32 div;
  93. /* Compute the clock divisor and select the internal or external dot
  94. * clock based on the requested frequency.
  95. */
  96. clk = clk_get_rate(rcrtc->clock);
  97. div = DIV_ROUND_CLOSEST(clk, mode_clock);
  98. div = clamp(div, 1U, 64U) - 1;
  99. escr = div | ESCR_DCLKSEL_CLKS;
  100. if (rcrtc->extclock) {
  101. unsigned long extclk;
  102. unsigned long extrate;
  103. unsigned long rate;
  104. u32 extdiv;
  105. extclk = clk_get_rate(rcrtc->extclock);
  106. extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock);
  107. extdiv = clamp(extdiv, 1U, 64U) - 1;
  108. rate = clk / (div + 1);
  109. extrate = extclk / (extdiv + 1);
  110. if (abs((long)extrate - (long)mode_clock) <
  111. abs((long)rate - (long)mode_clock)) {
  112. dev_dbg(rcrtc->group->dev->dev,
  113. "crtc%u: using external clock\n", rcrtc->index);
  114. escr = extdiv | ESCR_DCLKSEL_DCLKIN;
  115. }
  116. }
  117. rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
  118. escr);
  119. rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
  120. /* Signal polarities */
  121. value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
  122. | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
  123. | DSMR_DIPM_DE | DSMR_CSPM;
  124. rcar_du_crtc_write(rcrtc, DSMR, value);
  125. /* Display timings */
  126. rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
  127. rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
  128. mode->hdisplay - 19);
  129. rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
  130. mode->hsync_start - 1);
  131. rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
  132. rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
  133. mode->crtc_vsync_end - 2);
  134. rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
  135. mode->crtc_vsync_end +
  136. mode->crtc_vdisplay - 2);
  137. rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
  138. mode->crtc_vsync_end +
  139. mode->crtc_vsync_start - 1);
  140. rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
  141. rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
  142. rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
  143. }
  144. void rcar_du_crtc_route_output(struct drm_crtc *crtc,
  145. enum rcar_du_output output)
  146. {
  147. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  148. struct rcar_du_device *rcdu = rcrtc->group->dev;
  149. /* Store the route from the CRTC output to the DU output. The DU will be
  150. * configured when starting the CRTC.
  151. */
  152. rcrtc->outputs |= BIT(output);
  153. /* Store RGB routing to DPAD0, the hardware will be configured when
  154. * starting the CRTC.
  155. */
  156. if (output == RCAR_DU_OUTPUT_DPAD0)
  157. rcdu->dpad0_source = rcrtc->index;
  158. }
  159. static unsigned int plane_zpos(struct rcar_du_plane *plane)
  160. {
  161. return to_rcar_plane_state(plane->plane.state)->zpos;
  162. }
  163. static const struct rcar_du_format_info *
  164. plane_format(struct rcar_du_plane *plane)
  165. {
  166. return to_rcar_plane_state(plane->plane.state)->format;
  167. }
  168. static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
  169. {
  170. struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
  171. unsigned int num_planes = 0;
  172. unsigned int dptsr_planes;
  173. unsigned int hwplanes = 0;
  174. unsigned int prio = 0;
  175. unsigned int i;
  176. u32 dspr = 0;
  177. for (i = 0; i < rcrtc->group->num_planes; ++i) {
  178. struct rcar_du_plane *plane = &rcrtc->group->planes[i];
  179. unsigned int j;
  180. if (plane->plane.state->crtc != &rcrtc->crtc)
  181. continue;
  182. /* Insert the plane in the sorted planes array. */
  183. for (j = num_planes++; j > 0; --j) {
  184. if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
  185. break;
  186. planes[j] = planes[j-1];
  187. }
  188. planes[j] = plane;
  189. prio += plane_format(plane)->planes * 4;
  190. }
  191. for (i = 0; i < num_planes; ++i) {
  192. struct rcar_du_plane *plane = planes[i];
  193. struct drm_plane_state *state = plane->plane.state;
  194. unsigned int index = to_rcar_plane_state(state)->hwindex;
  195. prio -= 4;
  196. dspr |= (index + 1) << prio;
  197. hwplanes |= 1 << index;
  198. if (plane_format(plane)->planes == 2) {
  199. index = (index + 1) % 8;
  200. prio -= 4;
  201. dspr |= (index + 1) << prio;
  202. hwplanes |= 1 << index;
  203. }
  204. }
  205. /* Update the planes to display timing and dot clock generator
  206. * associations.
  207. *
  208. * Updating the DPTSR register requires restarting the CRTC group,
  209. * resulting in visible flicker. To mitigate the issue only update the
  210. * association if needed by enabled planes. Planes being disabled will
  211. * keep their current association.
  212. */
  213. mutex_lock(&rcrtc->group->lock);
  214. dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
  215. : rcrtc->group->dptsr_planes & ~hwplanes;
  216. if (dptsr_planes != rcrtc->group->dptsr_planes) {
  217. rcar_du_group_write(rcrtc->group, DPTSR,
  218. (dptsr_planes << 16) | dptsr_planes);
  219. rcrtc->group->dptsr_planes = dptsr_planes;
  220. if (rcrtc->group->used_crtcs)
  221. rcar_du_group_restart(rcrtc->group);
  222. }
  223. mutex_unlock(&rcrtc->group->lock);
  224. rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
  225. dspr);
  226. }
  227. /* -----------------------------------------------------------------------------
  228. * Page Flip
  229. */
  230. static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
  231. {
  232. struct drm_pending_vblank_event *event;
  233. struct drm_device *dev = rcrtc->crtc.dev;
  234. unsigned long flags;
  235. spin_lock_irqsave(&dev->event_lock, flags);
  236. event = rcrtc->event;
  237. rcrtc->event = NULL;
  238. spin_unlock_irqrestore(&dev->event_lock, flags);
  239. if (event == NULL)
  240. return;
  241. spin_lock_irqsave(&dev->event_lock, flags);
  242. drm_send_vblank_event(dev, rcrtc->index, event);
  243. wake_up(&rcrtc->flip_wait);
  244. spin_unlock_irqrestore(&dev->event_lock, flags);
  245. drm_crtc_vblank_put(&rcrtc->crtc);
  246. }
  247. static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
  248. {
  249. struct drm_device *dev = rcrtc->crtc.dev;
  250. unsigned long flags;
  251. bool pending;
  252. spin_lock_irqsave(&dev->event_lock, flags);
  253. pending = rcrtc->event != NULL;
  254. spin_unlock_irqrestore(&dev->event_lock, flags);
  255. return pending;
  256. }
  257. static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
  258. {
  259. struct rcar_du_device *rcdu = rcrtc->group->dev;
  260. if (wait_event_timeout(rcrtc->flip_wait,
  261. !rcar_du_crtc_page_flip_pending(rcrtc),
  262. msecs_to_jiffies(50)))
  263. return;
  264. dev_warn(rcdu->dev, "page flip timeout\n");
  265. rcar_du_crtc_finish_page_flip(rcrtc);
  266. }
  267. /* -----------------------------------------------------------------------------
  268. * Start/Stop and Suspend/Resume
  269. */
  270. static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
  271. {
  272. struct drm_crtc *crtc = &rcrtc->crtc;
  273. bool interlaced;
  274. if (rcrtc->started)
  275. return;
  276. /* Set display off and background to black */
  277. rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
  278. rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
  279. /* Configure display timings and output routing */
  280. rcar_du_crtc_set_display_timing(rcrtc);
  281. rcar_du_group_set_routing(rcrtc->group);
  282. /* Start with all planes disabled. */
  283. rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
  284. /* Select master sync mode. This enables display operation in master
  285. * sync mode (with the HSYNC and VSYNC signals configured as outputs and
  286. * actively driven).
  287. */
  288. interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
  289. rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
  290. (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
  291. DSYSR_TVM_MASTER);
  292. rcar_du_group_start_stop(rcrtc->group, true);
  293. /* Turn vertical blanking interrupt reporting back on. */
  294. drm_crtc_vblank_on(crtc);
  295. rcrtc->started = true;
  296. }
  297. static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
  298. {
  299. struct rcar_du_device *rcdu = rcrtc->group->dev;
  300. struct drm_crtc *crtc = &rcrtc->crtc;
  301. u32 status;
  302. /* Make sure vblank interrupts are enabled. */
  303. drm_crtc_vblank_get(crtc);
  304. /*
  305. * Disable planes and calculate how many vertical blanking interrupts we
  306. * have to wait for. If a vertical blanking interrupt has been triggered
  307. * but not processed yet, we don't know whether it occurred before or
  308. * after the planes got disabled. We thus have to wait for two vblank
  309. * interrupts in that case.
  310. */
  311. spin_lock_irq(&rcrtc->vblank_lock);
  312. rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
  313. status = rcar_du_crtc_read(rcrtc, DSSR);
  314. rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
  315. spin_unlock_irq(&rcrtc->vblank_lock);
  316. if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
  317. msecs_to_jiffies(100)))
  318. dev_warn(rcdu->dev, "vertical blanking timeout\n");
  319. drm_crtc_vblank_put(crtc);
  320. }
  321. static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
  322. {
  323. struct drm_crtc *crtc = &rcrtc->crtc;
  324. if (!rcrtc->started)
  325. return;
  326. /* Disable all planes and wait for the change to take effect. This is
  327. * required as the plane enable registers are updated on vblank, and no
  328. * vblank will occur once the CRTC is stopped. Disabling planes when
  329. * starting the CRTC thus wouldn't be enough as it would start scanning
  330. * out immediately from old frame buffers until the next vblank.
  331. *
  332. * This increases the CRTC stop delay, especially when multiple CRTCs
  333. * are stopped in one operation as we now wait for one vblank per CRTC.
  334. * Whether this can be improved needs to be researched.
  335. */
  336. rcar_du_crtc_disable_planes(rcrtc);
  337. /* Disable vertical blanking interrupt reporting. We first need to wait
  338. * for page flip completion before stopping the CRTC as userspace
  339. * expects page flips to eventually complete.
  340. */
  341. rcar_du_crtc_wait_page_flip(rcrtc);
  342. drm_crtc_vblank_off(crtc);
  343. /* Select switch sync mode. This stops display operation and configures
  344. * the HSYNC and VSYNC signals as inputs.
  345. */
  346. rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
  347. rcar_du_group_start_stop(rcrtc->group, false);
  348. rcrtc->started = false;
  349. }
  350. void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
  351. {
  352. rcar_du_crtc_stop(rcrtc);
  353. rcar_du_crtc_put(rcrtc);
  354. }
  355. void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
  356. {
  357. unsigned int i;
  358. if (!rcrtc->enabled)
  359. return;
  360. rcar_du_crtc_get(rcrtc);
  361. rcar_du_crtc_start(rcrtc);
  362. /* Commit the planes state. */
  363. for (i = 0; i < rcrtc->group->num_planes; ++i) {
  364. struct rcar_du_plane *plane = &rcrtc->group->planes[i];
  365. if (plane->plane.state->crtc != &rcrtc->crtc)
  366. continue;
  367. rcar_du_plane_setup(plane);
  368. }
  369. rcar_du_crtc_update_planes(rcrtc);
  370. }
  371. /* -----------------------------------------------------------------------------
  372. * CRTC Functions
  373. */
  374. static void rcar_du_crtc_enable(struct drm_crtc *crtc)
  375. {
  376. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  377. if (rcrtc->enabled)
  378. return;
  379. rcar_du_crtc_get(rcrtc);
  380. rcar_du_crtc_start(rcrtc);
  381. rcrtc->enabled = true;
  382. }
  383. static void rcar_du_crtc_disable(struct drm_crtc *crtc)
  384. {
  385. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  386. if (!rcrtc->enabled)
  387. return;
  388. rcar_du_crtc_stop(rcrtc);
  389. rcar_du_crtc_put(rcrtc);
  390. rcrtc->enabled = false;
  391. rcrtc->outputs = 0;
  392. }
  393. static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
  394. const struct drm_display_mode *mode,
  395. struct drm_display_mode *adjusted_mode)
  396. {
  397. /* TODO Fixup modes */
  398. return true;
  399. }
  400. static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
  401. struct drm_crtc_state *old_crtc_state)
  402. {
  403. struct drm_pending_vblank_event *event = crtc->state->event;
  404. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  405. struct drm_device *dev = rcrtc->crtc.dev;
  406. unsigned long flags;
  407. if (event) {
  408. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  409. spin_lock_irqsave(&dev->event_lock, flags);
  410. rcrtc->event = event;
  411. spin_unlock_irqrestore(&dev->event_lock, flags);
  412. }
  413. }
  414. static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
  415. struct drm_crtc_state *old_crtc_state)
  416. {
  417. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  418. rcar_du_crtc_update_planes(rcrtc);
  419. }
  420. static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
  421. .mode_fixup = rcar_du_crtc_mode_fixup,
  422. .disable = rcar_du_crtc_disable,
  423. .enable = rcar_du_crtc_enable,
  424. .atomic_begin = rcar_du_crtc_atomic_begin,
  425. .atomic_flush = rcar_du_crtc_atomic_flush,
  426. };
  427. static const struct drm_crtc_funcs crtc_funcs = {
  428. .reset = drm_atomic_helper_crtc_reset,
  429. .destroy = drm_crtc_cleanup,
  430. .set_config = drm_atomic_helper_set_config,
  431. .page_flip = drm_atomic_helper_page_flip,
  432. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  433. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  434. };
  435. /* -----------------------------------------------------------------------------
  436. * Interrupt Handling
  437. */
  438. static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
  439. {
  440. struct rcar_du_crtc *rcrtc = arg;
  441. irqreturn_t ret = IRQ_NONE;
  442. u32 status;
  443. spin_lock(&rcrtc->vblank_lock);
  444. status = rcar_du_crtc_read(rcrtc, DSSR);
  445. rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
  446. if (status & DSSR_VBK) {
  447. /*
  448. * Wake up the vblank wait if the counter reaches 0. This must
  449. * be protected by the vblank_lock to avoid races in
  450. * rcar_du_crtc_disable_planes().
  451. */
  452. if (rcrtc->vblank_count) {
  453. if (--rcrtc->vblank_count == 0)
  454. wake_up(&rcrtc->vblank_wait);
  455. }
  456. }
  457. spin_unlock(&rcrtc->vblank_lock);
  458. if (status & DSSR_VBK) {
  459. drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
  460. rcar_du_crtc_finish_page_flip(rcrtc);
  461. ret = IRQ_HANDLED;
  462. }
  463. return ret;
  464. }
  465. /* -----------------------------------------------------------------------------
  466. * Initialization
  467. */
  468. int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
  469. {
  470. static const unsigned int mmio_offsets[] = {
  471. DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
  472. };
  473. struct rcar_du_device *rcdu = rgrp->dev;
  474. struct platform_device *pdev = to_platform_device(rcdu->dev);
  475. struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
  476. struct drm_crtc *crtc = &rcrtc->crtc;
  477. unsigned int irqflags;
  478. struct clk *clk;
  479. char clk_name[9];
  480. char *name;
  481. int irq;
  482. int ret;
  483. /* Get the CRTC clock and the optional external clock. */
  484. if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
  485. sprintf(clk_name, "du.%u", index);
  486. name = clk_name;
  487. } else {
  488. name = NULL;
  489. }
  490. rcrtc->clock = devm_clk_get(rcdu->dev, name);
  491. if (IS_ERR(rcrtc->clock)) {
  492. dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
  493. return PTR_ERR(rcrtc->clock);
  494. }
  495. sprintf(clk_name, "dclkin.%u", index);
  496. clk = devm_clk_get(rcdu->dev, clk_name);
  497. if (!IS_ERR(clk)) {
  498. rcrtc->extclock = clk;
  499. } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) {
  500. dev_info(rcdu->dev, "can't get external clock %u\n", index);
  501. return -EPROBE_DEFER;
  502. }
  503. init_waitqueue_head(&rcrtc->flip_wait);
  504. init_waitqueue_head(&rcrtc->vblank_wait);
  505. spin_lock_init(&rcrtc->vblank_lock);
  506. rcrtc->group = rgrp;
  507. rcrtc->mmio_offset = mmio_offsets[index];
  508. rcrtc->index = index;
  509. rcrtc->enabled = false;
  510. ret = drm_crtc_init_with_planes(rcdu->ddev, crtc,
  511. &rgrp->planes[index % 2].plane,
  512. NULL, &crtc_funcs);
  513. if (ret < 0)
  514. return ret;
  515. drm_crtc_helper_add(crtc, &crtc_helper_funcs);
  516. /* Start with vertical blanking interrupt reporting disabled. */
  517. drm_crtc_vblank_off(crtc);
  518. /* Register the interrupt handler. */
  519. if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
  520. irq = platform_get_irq(pdev, index);
  521. irqflags = 0;
  522. } else {
  523. irq = platform_get_irq(pdev, 0);
  524. irqflags = IRQF_SHARED;
  525. }
  526. if (irq < 0) {
  527. dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
  528. return irq;
  529. }
  530. ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
  531. dev_name(rcdu->dev), rcrtc);
  532. if (ret < 0) {
  533. dev_err(rcdu->dev,
  534. "failed to register IRQ for CRTC %u\n", index);
  535. return ret;
  536. }
  537. return 0;
  538. }
  539. void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
  540. {
  541. if (enable) {
  542. rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
  543. rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
  544. } else {
  545. rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
  546. }
  547. }