dw_hdmi-rockchip.c 8.0 KB

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  1. /*
  2. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/regmap.h>
  13. #include <drm/drm_of.h>
  14. #include <drm/drmP.h>
  15. #include <drm/drm_crtc_helper.h>
  16. #include <drm/drm_edid.h>
  17. #include <drm/drm_encoder_slave.h>
  18. #include <drm/bridge/dw_hdmi.h>
  19. #include "rockchip_drm_drv.h"
  20. #include "rockchip_drm_vop.h"
  21. #define GRF_SOC_CON6 0x025c
  22. #define HDMI_SEL_VOP_LIT (1 << 4)
  23. struct rockchip_hdmi {
  24. struct device *dev;
  25. struct regmap *regmap;
  26. struct drm_encoder encoder;
  27. };
  28. #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
  29. static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  30. {
  31. 27000000, {
  32. { 0x00b3, 0x0000},
  33. { 0x2153, 0x0000},
  34. { 0x40f3, 0x0000}
  35. },
  36. }, {
  37. 36000000, {
  38. { 0x00b3, 0x0000},
  39. { 0x2153, 0x0000},
  40. { 0x40f3, 0x0000}
  41. },
  42. }, {
  43. 40000000, {
  44. { 0x00b3, 0x0000},
  45. { 0x2153, 0x0000},
  46. { 0x40f3, 0x0000}
  47. },
  48. }, {
  49. 54000000, {
  50. { 0x0072, 0x0001},
  51. { 0x2142, 0x0001},
  52. { 0x40a2, 0x0001},
  53. },
  54. }, {
  55. 65000000, {
  56. { 0x0072, 0x0001},
  57. { 0x2142, 0x0001},
  58. { 0x40a2, 0x0001},
  59. },
  60. }, {
  61. 66000000, {
  62. { 0x013e, 0x0003},
  63. { 0x217e, 0x0002},
  64. { 0x4061, 0x0002}
  65. },
  66. }, {
  67. 74250000, {
  68. { 0x0072, 0x0001},
  69. { 0x2145, 0x0002},
  70. { 0x4061, 0x0002}
  71. },
  72. }, {
  73. 83500000, {
  74. { 0x0072, 0x0001},
  75. },
  76. }, {
  77. 108000000, {
  78. { 0x0051, 0x0002},
  79. { 0x2145, 0x0002},
  80. { 0x4061, 0x0002}
  81. },
  82. }, {
  83. 106500000, {
  84. { 0x0051, 0x0002},
  85. { 0x2145, 0x0002},
  86. { 0x4061, 0x0002}
  87. },
  88. }, {
  89. 146250000, {
  90. { 0x0051, 0x0002},
  91. { 0x2145, 0x0002},
  92. { 0x4061, 0x0002}
  93. },
  94. }, {
  95. 148500000, {
  96. { 0x0051, 0x0003},
  97. { 0x214c, 0x0003},
  98. { 0x4064, 0x0003}
  99. },
  100. }, {
  101. ~0UL, {
  102. { 0x00a0, 0x000a },
  103. { 0x2001, 0x000f },
  104. { 0x4002, 0x000f },
  105. },
  106. }
  107. };
  108. static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
  109. /* pixelclk bpp8 bpp10 bpp12 */
  110. {
  111. 40000000, { 0x0018, 0x0018, 0x0018 },
  112. }, {
  113. 65000000, { 0x0028, 0x0028, 0x0028 },
  114. }, {
  115. 66000000, { 0x0038, 0x0038, 0x0038 },
  116. }, {
  117. 74250000, { 0x0028, 0x0038, 0x0038 },
  118. }, {
  119. 83500000, { 0x0028, 0x0038, 0x0038 },
  120. }, {
  121. 146250000, { 0x0038, 0x0038, 0x0038 },
  122. }, {
  123. 148500000, { 0x0000, 0x0038, 0x0038 },
  124. }, {
  125. ~0UL, { 0x0000, 0x0000, 0x0000},
  126. }
  127. };
  128. static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
  129. /*pixelclk symbol term vlev*/
  130. { 74250000, 0x8009, 0x0004, 0x0272},
  131. { 148500000, 0x802b, 0x0004, 0x028d},
  132. { 297000000, 0x8039, 0x0005, 0x028d},
  133. { ~0UL, 0x0000, 0x0000, 0x0000}
  134. };
  135. static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
  136. {
  137. struct device_node *np = hdmi->dev->of_node;
  138. hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  139. if (IS_ERR(hdmi->regmap)) {
  140. dev_err(hdmi->dev, "Unable to get rockchip,grf\n");
  141. return PTR_ERR(hdmi->regmap);
  142. }
  143. return 0;
  144. }
  145. static enum drm_mode_status
  146. dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
  147. struct drm_display_mode *mode)
  148. {
  149. const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
  150. int pclk = mode->clock * 1000;
  151. bool valid = false;
  152. int i;
  153. for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
  154. if (pclk == mpll_cfg[i].mpixelclock) {
  155. valid = true;
  156. break;
  157. }
  158. }
  159. return (valid) ? MODE_OK : MODE_BAD;
  160. }
  161. static struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
  162. .destroy = drm_encoder_cleanup,
  163. };
  164. static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
  165. {
  166. }
  167. static bool
  168. dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
  169. const struct drm_display_mode *mode,
  170. struct drm_display_mode *adj_mode)
  171. {
  172. return true;
  173. }
  174. static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
  175. struct drm_display_mode *mode,
  176. struct drm_display_mode *adj_mode)
  177. {
  178. }
  179. static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
  180. {
  181. struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
  182. u32 val;
  183. int mux;
  184. mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
  185. if (mux)
  186. val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
  187. else
  188. val = HDMI_SEL_VOP_LIT << 16;
  189. regmap_write(hdmi->regmap, GRF_SOC_CON6, val);
  190. dev_dbg(hdmi->dev, "vop %s output to hdmi\n",
  191. (mux) ? "LIT" : "BIG");
  192. }
  193. static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
  194. {
  195. rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
  196. ROCKCHIP_OUT_MODE_AAAA);
  197. }
  198. static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
  199. .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
  200. .mode_set = dw_hdmi_rockchip_encoder_mode_set,
  201. .prepare = dw_hdmi_rockchip_encoder_prepare,
  202. .commit = dw_hdmi_rockchip_encoder_commit,
  203. .disable = dw_hdmi_rockchip_encoder_disable,
  204. };
  205. static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = {
  206. .mode_valid = dw_hdmi_rockchip_mode_valid,
  207. .mpll_cfg = rockchip_mpll_cfg,
  208. .cur_ctr = rockchip_cur_ctr,
  209. .phy_config = rockchip_phy_config,
  210. .dev_type = RK3288_HDMI,
  211. };
  212. static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
  213. { .compatible = "rockchip,rk3288-dw-hdmi",
  214. .data = &rockchip_hdmi_drv_data
  215. },
  216. {},
  217. };
  218. MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
  219. static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
  220. void *data)
  221. {
  222. struct platform_device *pdev = to_platform_device(dev);
  223. const struct dw_hdmi_plat_data *plat_data;
  224. const struct of_device_id *match;
  225. struct drm_device *drm = data;
  226. struct drm_encoder *encoder;
  227. struct rockchip_hdmi *hdmi;
  228. struct resource *iores;
  229. int irq;
  230. int ret;
  231. if (!pdev->dev.of_node)
  232. return -ENODEV;
  233. hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
  234. if (!hdmi)
  235. return -ENOMEM;
  236. match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
  237. plat_data = match->data;
  238. hdmi->dev = &pdev->dev;
  239. encoder = &hdmi->encoder;
  240. irq = platform_get_irq(pdev, 0);
  241. if (irq < 0)
  242. return irq;
  243. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  244. if (!iores)
  245. return -ENXIO;
  246. platform_set_drvdata(pdev, hdmi);
  247. encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
  248. /*
  249. * If we failed to find the CRTC(s) which this encoder is
  250. * supposed to be connected to, it's because the CRTC has
  251. * not been registered yet. Defer probing, and hope that
  252. * the required CRTC is added later.
  253. */
  254. if (encoder->possible_crtcs == 0)
  255. return -EPROBE_DEFER;
  256. ret = rockchip_hdmi_parse_dt(hdmi);
  257. if (ret) {
  258. dev_err(hdmi->dev, "Unable to parse OF data\n");
  259. return ret;
  260. }
  261. drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
  262. drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
  263. DRM_MODE_ENCODER_TMDS);
  264. return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
  265. }
  266. static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
  267. void *data)
  268. {
  269. return dw_hdmi_unbind(dev, master, data);
  270. }
  271. static const struct component_ops dw_hdmi_rockchip_ops = {
  272. .bind = dw_hdmi_rockchip_bind,
  273. .unbind = dw_hdmi_rockchip_unbind,
  274. };
  275. static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
  276. {
  277. return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
  278. }
  279. static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
  280. {
  281. component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
  282. return 0;
  283. }
  284. static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
  285. .probe = dw_hdmi_rockchip_probe,
  286. .remove = dw_hdmi_rockchip_remove,
  287. .driver = {
  288. .name = "dwhdmi-rockchip",
  289. .of_match_table = dw_hdmi_rockchip_dt_ids,
  290. },
  291. };
  292. module_platform_driver(dw_hdmi_rockchip_pltfm_driver);
  293. MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
  294. MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
  295. MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension");
  296. MODULE_LICENSE("GPL");
  297. MODULE_ALIAS("platform:dwhdmi-rockchip");