dsi.h 4.9 KB

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  1. /*
  2. * Copyright (C) 2013 NVIDIA Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #ifndef DRM_TEGRA_DSI_H
  9. #define DRM_TEGRA_DSI_H
  10. #define DSI_INCR_SYNCPT 0x00
  11. #define DSI_INCR_SYNCPT_CONTROL 0x01
  12. #define DSI_INCR_SYNCPT_ERROR 0x02
  13. #define DSI_CTXSW 0x08
  14. #define DSI_RD_DATA 0x09
  15. #define DSI_WR_DATA 0x0a
  16. #define DSI_POWER_CONTROL 0x0b
  17. #define DSI_POWER_CONTROL_ENABLE (1 << 0)
  18. #define DSI_INT_ENABLE 0x0c
  19. #define DSI_INT_STATUS 0x0d
  20. #define DSI_INT_MASK 0x0e
  21. #define DSI_HOST_CONTROL 0x0f
  22. #define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
  23. #define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
  24. #define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
  25. #define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
  26. #define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
  27. #define DSI_HOST_CONTROL_RAW (1 << 6)
  28. #define DSI_HOST_CONTROL_HS (1 << 5)
  29. #define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
  30. #define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
  31. #define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
  32. #define DSI_HOST_CONTROL_CS (1 << 1)
  33. #define DSI_HOST_CONTROL_ECC (1 << 0)
  34. #define DSI_CONTROL 0x10
  35. #define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
  36. #define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
  37. #define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
  38. #define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
  39. #define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
  40. #define DSI_CONTROL_DCS_ENABLE (1 << 3)
  41. #define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
  42. #define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
  43. #define DSI_CONTROL_HOST_ENABLE (1 << 0)
  44. #define DSI_SOL_DELAY 0x11
  45. #define DSI_MAX_THRESHOLD 0x12
  46. #define DSI_TRIGGER 0x13
  47. #define DSI_TRIGGER_HOST (1 << 1)
  48. #define DSI_TRIGGER_VIDEO (1 << 0)
  49. #define DSI_TX_CRC 0x14
  50. #define DSI_STATUS 0x15
  51. #define DSI_STATUS_IDLE (1 << 10)
  52. #define DSI_STATUS_UNDERFLOW (1 << 9)
  53. #define DSI_STATUS_OVERFLOW (1 << 8)
  54. #define DSI_INIT_SEQ_CONTROL 0x1a
  55. #define DSI_INIT_SEQ_DATA_0 0x1b
  56. #define DSI_INIT_SEQ_DATA_1 0x1c
  57. #define DSI_INIT_SEQ_DATA_2 0x1d
  58. #define DSI_INIT_SEQ_DATA_3 0x1e
  59. #define DSI_INIT_SEQ_DATA_4 0x1f
  60. #define DSI_INIT_SEQ_DATA_5 0x20
  61. #define DSI_INIT_SEQ_DATA_6 0x21
  62. #define DSI_INIT_SEQ_DATA_7 0x22
  63. #define DSI_PKT_SEQ_0_LO 0x23
  64. #define DSI_PKT_SEQ_0_HI 0x24
  65. #define DSI_PKT_SEQ_1_LO 0x25
  66. #define DSI_PKT_SEQ_1_HI 0x26
  67. #define DSI_PKT_SEQ_2_LO 0x27
  68. #define DSI_PKT_SEQ_2_HI 0x28
  69. #define DSI_PKT_SEQ_3_LO 0x29
  70. #define DSI_PKT_SEQ_3_HI 0x2a
  71. #define DSI_PKT_SEQ_4_LO 0x2b
  72. #define DSI_PKT_SEQ_4_HI 0x2c
  73. #define DSI_PKT_SEQ_5_LO 0x2d
  74. #define DSI_PKT_SEQ_5_HI 0x2e
  75. #define DSI_DCS_CMDS 0x33
  76. #define DSI_PKT_LEN_0_1 0x34
  77. #define DSI_PKT_LEN_2_3 0x35
  78. #define DSI_PKT_LEN_4_5 0x36
  79. #define DSI_PKT_LEN_6_7 0x37
  80. #define DSI_PHY_TIMING_0 0x3c
  81. #define DSI_PHY_TIMING_1 0x3d
  82. #define DSI_PHY_TIMING_2 0x3e
  83. #define DSI_BTA_TIMING 0x3f
  84. #define DSI_TIMING_FIELD(value, period, hwinc) \
  85. ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
  86. #define DSI_TIMEOUT_0 0x44
  87. #define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
  88. #define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
  89. #define DSI_TIMEOUT_1 0x45
  90. #define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
  91. #define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
  92. #define DSI_TO_TALLY 0x46
  93. #define DSI_TALLY_TA(x) (((x) & 0xff) << 16)
  94. #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
  95. #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
  96. #define DSI_PAD_CONTROL_0 0x4b
  97. #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
  98. #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
  99. #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
  100. #define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
  101. #define DSI_PAD_CONTROL_CD 0x4c
  102. #define DSI_PAD_CD_STATUS 0x4d
  103. #define DSI_VIDEO_MODE_CONTROL 0x4e
  104. #define DSI_PAD_CONTROL_1 0x4f
  105. #define DSI_PAD_CONTROL_2 0x50
  106. #define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
  107. #define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4)
  108. #define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8)
  109. #define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
  110. #define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
  111. #define DSI_PAD_CONTROL_3 0x51
  112. #define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
  113. #define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
  114. #define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
  115. #define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
  116. #define DSI_PAD_CONTROL_4 0x52
  117. #define DSI_GANGED_MODE_CONTROL 0x53
  118. #define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0)
  119. #define DSI_GANGED_MODE_START 0x54
  120. #define DSI_GANGED_MODE_SIZE 0x55
  121. #define DSI_RAW_DATA_BYTE_COUNT 0x56
  122. #define DSI_ULTRA_LOW_POWER_CONTROL 0x57
  123. #define DSI_INIT_SEQ_DATA_8 0x58
  124. #define DSI_INIT_SEQ_DATA_9 0x59
  125. #define DSI_INIT_SEQ_DATA_10 0x5a
  126. #define DSI_INIT_SEQ_DATA_11 0x5b
  127. #define DSI_INIT_SEQ_DATA_12 0x5c
  128. #define DSI_INIT_SEQ_DATA_13 0x5d
  129. #define DSI_INIT_SEQ_DATA_14 0x5e
  130. #define DSI_INIT_SEQ_DATA_15 0x5f
  131. /*
  132. * pixel format as used in the DSI_CONTROL_FORMAT field
  133. */
  134. enum tegra_dsi_format {
  135. TEGRA_DSI_FORMAT_16P,
  136. TEGRA_DSI_FORMAT_18NP,
  137. TEGRA_DSI_FORMAT_18P,
  138. TEGRA_DSI_FORMAT_24P,
  139. };
  140. #endif