tilcdc_drv.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723
  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include <linux/component.h>
  19. #include "tilcdc_drv.h"
  20. #include "tilcdc_regs.h"
  21. #include "tilcdc_tfp410.h"
  22. #include "tilcdc_panel.h"
  23. #include "tilcdc_external.h"
  24. #include "drm_fb_helper.h"
  25. static LIST_HEAD(module_list);
  26. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  27. const struct tilcdc_module_ops *funcs)
  28. {
  29. mod->name = name;
  30. mod->funcs = funcs;
  31. INIT_LIST_HEAD(&mod->list);
  32. list_add(&mod->list, &module_list);
  33. }
  34. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  35. {
  36. list_del(&mod->list);
  37. }
  38. static struct of_device_id tilcdc_of_match[];
  39. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  40. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  41. {
  42. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  43. }
  44. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  45. {
  46. struct tilcdc_drm_private *priv = dev->dev_private;
  47. drm_fbdev_cma_hotplug_event(priv->fbdev);
  48. }
  49. static const struct drm_mode_config_funcs mode_config_funcs = {
  50. .fb_create = tilcdc_fb_create,
  51. .output_poll_changed = tilcdc_fb_output_poll_changed,
  52. };
  53. static int modeset_init(struct drm_device *dev)
  54. {
  55. struct tilcdc_drm_private *priv = dev->dev_private;
  56. struct tilcdc_module *mod;
  57. drm_mode_config_init(dev);
  58. priv->crtc = tilcdc_crtc_create(dev);
  59. list_for_each_entry(mod, &module_list, list) {
  60. DBG("loading module: %s", mod->name);
  61. mod->funcs->modeset_init(mod, dev);
  62. }
  63. dev->mode_config.min_width = 0;
  64. dev->mode_config.min_height = 0;
  65. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  66. dev->mode_config.max_height = 2048;
  67. dev->mode_config.funcs = &mode_config_funcs;
  68. return 0;
  69. }
  70. #ifdef CONFIG_CPU_FREQ
  71. static int cpufreq_transition(struct notifier_block *nb,
  72. unsigned long val, void *data)
  73. {
  74. struct tilcdc_drm_private *priv = container_of(nb,
  75. struct tilcdc_drm_private, freq_transition);
  76. if (val == CPUFREQ_POSTCHANGE) {
  77. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  78. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  79. tilcdc_crtc_update_clk(priv->crtc);
  80. }
  81. }
  82. return 0;
  83. }
  84. #endif
  85. /*
  86. * DRM operations:
  87. */
  88. static int tilcdc_unload(struct drm_device *dev)
  89. {
  90. struct tilcdc_drm_private *priv = dev->dev_private;
  91. tilcdc_remove_external_encoders(dev);
  92. drm_fbdev_cma_fini(priv->fbdev);
  93. drm_kms_helper_poll_fini(dev);
  94. drm_mode_config_cleanup(dev);
  95. drm_vblank_cleanup(dev);
  96. pm_runtime_get_sync(dev->dev);
  97. drm_irq_uninstall(dev);
  98. pm_runtime_put_sync(dev->dev);
  99. #ifdef CONFIG_CPU_FREQ
  100. cpufreq_unregister_notifier(&priv->freq_transition,
  101. CPUFREQ_TRANSITION_NOTIFIER);
  102. #endif
  103. if (priv->clk)
  104. clk_put(priv->clk);
  105. if (priv->mmio)
  106. iounmap(priv->mmio);
  107. flush_workqueue(priv->wq);
  108. destroy_workqueue(priv->wq);
  109. dev->dev_private = NULL;
  110. pm_runtime_disable(dev->dev);
  111. kfree(priv);
  112. return 0;
  113. }
  114. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  115. {
  116. struct platform_device *pdev = dev->platformdev;
  117. struct device_node *node = pdev->dev.of_node;
  118. struct tilcdc_drm_private *priv;
  119. struct tilcdc_module *mod;
  120. struct resource *res;
  121. u32 bpp = 0;
  122. int ret;
  123. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  124. if (!priv) {
  125. dev_err(dev->dev, "failed to allocate private data\n");
  126. return -ENOMEM;
  127. }
  128. dev->dev_private = priv;
  129. priv->is_componentized =
  130. tilcdc_get_external_components(dev->dev, NULL) > 0;
  131. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  132. if (!priv->wq) {
  133. ret = -ENOMEM;
  134. goto fail_free_priv;
  135. }
  136. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  137. if (!res) {
  138. dev_err(dev->dev, "failed to get memory resource\n");
  139. ret = -EINVAL;
  140. goto fail_free_wq;
  141. }
  142. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  143. if (!priv->mmio) {
  144. dev_err(dev->dev, "failed to ioremap\n");
  145. ret = -ENOMEM;
  146. goto fail_free_wq;
  147. }
  148. priv->clk = clk_get(dev->dev, "fck");
  149. if (IS_ERR(priv->clk)) {
  150. dev_err(dev->dev, "failed to get functional clock\n");
  151. ret = -ENODEV;
  152. goto fail_iounmap;
  153. }
  154. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  155. if (IS_ERR(priv->clk)) {
  156. dev_err(dev->dev, "failed to get display clock\n");
  157. ret = -ENODEV;
  158. goto fail_put_clk;
  159. }
  160. #ifdef CONFIG_CPU_FREQ
  161. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  162. priv->freq_transition.notifier_call = cpufreq_transition;
  163. ret = cpufreq_register_notifier(&priv->freq_transition,
  164. CPUFREQ_TRANSITION_NOTIFIER);
  165. if (ret) {
  166. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  167. goto fail_put_disp_clk;
  168. }
  169. #endif
  170. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  171. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  172. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  173. if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
  174. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
  175. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  176. if (of_property_read_u32(node, "ti,max-pixelclock",
  177. &priv->max_pixelclock))
  178. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  179. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  180. pm_runtime_enable(dev->dev);
  181. pm_runtime_irq_safe(dev->dev);
  182. /* Determine LCD IP Version */
  183. pm_runtime_get_sync(dev->dev);
  184. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  185. case 0x4c100102:
  186. priv->rev = 1;
  187. break;
  188. case 0x4f200800:
  189. case 0x4f201000:
  190. priv->rev = 2;
  191. break;
  192. default:
  193. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  194. "defaulting to LCD revision 1\n",
  195. tilcdc_read(dev, LCDC_PID_REG));
  196. priv->rev = 1;
  197. break;
  198. }
  199. pm_runtime_put_sync(dev->dev);
  200. ret = modeset_init(dev);
  201. if (ret < 0) {
  202. dev_err(dev->dev, "failed to initialize mode setting\n");
  203. goto fail_cpufreq_unregister;
  204. }
  205. platform_set_drvdata(pdev, dev);
  206. if (priv->is_componentized) {
  207. ret = component_bind_all(dev->dev, dev);
  208. if (ret < 0)
  209. goto fail_mode_config_cleanup;
  210. ret = tilcdc_add_external_encoders(dev, &bpp);
  211. if (ret < 0)
  212. goto fail_component_cleanup;
  213. }
  214. if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
  215. dev_err(dev->dev, "no encoders/connectors found\n");
  216. ret = -ENXIO;
  217. goto fail_external_cleanup;
  218. }
  219. ret = drm_vblank_init(dev, 1);
  220. if (ret < 0) {
  221. dev_err(dev->dev, "failed to initialize vblank\n");
  222. goto fail_external_cleanup;
  223. }
  224. pm_runtime_get_sync(dev->dev);
  225. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  226. pm_runtime_put_sync(dev->dev);
  227. if (ret < 0) {
  228. dev_err(dev->dev, "failed to install IRQ handler\n");
  229. goto fail_vblank_cleanup;
  230. }
  231. list_for_each_entry(mod, &module_list, list) {
  232. DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
  233. bpp = mod->preferred_bpp;
  234. if (bpp > 0)
  235. break;
  236. }
  237. priv->fbdev = drm_fbdev_cma_init(dev, bpp,
  238. dev->mode_config.num_crtc,
  239. dev->mode_config.num_connector);
  240. if (IS_ERR(priv->fbdev)) {
  241. ret = PTR_ERR(priv->fbdev);
  242. goto fail_irq_uninstall;
  243. }
  244. drm_kms_helper_poll_init(dev);
  245. return 0;
  246. fail_irq_uninstall:
  247. pm_runtime_get_sync(dev->dev);
  248. drm_irq_uninstall(dev);
  249. pm_runtime_put_sync(dev->dev);
  250. fail_vblank_cleanup:
  251. drm_vblank_cleanup(dev);
  252. fail_mode_config_cleanup:
  253. drm_mode_config_cleanup(dev);
  254. fail_component_cleanup:
  255. if (priv->is_componentized)
  256. component_unbind_all(dev->dev, dev);
  257. fail_external_cleanup:
  258. tilcdc_remove_external_encoders(dev);
  259. fail_cpufreq_unregister:
  260. pm_runtime_disable(dev->dev);
  261. #ifdef CONFIG_CPU_FREQ
  262. cpufreq_unregister_notifier(&priv->freq_transition,
  263. CPUFREQ_TRANSITION_NOTIFIER);
  264. fail_put_disp_clk:
  265. clk_put(priv->disp_clk);
  266. #endif
  267. fail_put_clk:
  268. clk_put(priv->clk);
  269. fail_iounmap:
  270. iounmap(priv->mmio);
  271. fail_free_wq:
  272. flush_workqueue(priv->wq);
  273. destroy_workqueue(priv->wq);
  274. fail_free_priv:
  275. dev->dev_private = NULL;
  276. kfree(priv);
  277. return ret;
  278. }
  279. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  280. {
  281. struct tilcdc_drm_private *priv = dev->dev_private;
  282. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  283. }
  284. static void tilcdc_lastclose(struct drm_device *dev)
  285. {
  286. struct tilcdc_drm_private *priv = dev->dev_private;
  287. drm_fbdev_cma_restore_mode(priv->fbdev);
  288. }
  289. static irqreturn_t tilcdc_irq(int irq, void *arg)
  290. {
  291. struct drm_device *dev = arg;
  292. struct tilcdc_drm_private *priv = dev->dev_private;
  293. return tilcdc_crtc_irq(priv->crtc);
  294. }
  295. static void tilcdc_irq_preinstall(struct drm_device *dev)
  296. {
  297. tilcdc_clear_irqstatus(dev, 0xffffffff);
  298. }
  299. static int tilcdc_irq_postinstall(struct drm_device *dev)
  300. {
  301. struct tilcdc_drm_private *priv = dev->dev_private;
  302. /* enable FIFO underflow irq: */
  303. if (priv->rev == 1)
  304. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  305. else
  306. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  307. return 0;
  308. }
  309. static void tilcdc_irq_uninstall(struct drm_device *dev)
  310. {
  311. struct tilcdc_drm_private *priv = dev->dev_private;
  312. /* disable irqs that we might have enabled: */
  313. if (priv->rev == 1) {
  314. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  315. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  316. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  317. } else {
  318. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  319. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  320. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  321. LCDC_FRAME_DONE);
  322. }
  323. }
  324. static void enable_vblank(struct drm_device *dev, bool enable)
  325. {
  326. struct tilcdc_drm_private *priv = dev->dev_private;
  327. u32 reg, mask;
  328. if (priv->rev == 1) {
  329. reg = LCDC_DMA_CTRL_REG;
  330. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  331. } else {
  332. reg = LCDC_INT_ENABLE_SET_REG;
  333. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  334. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  335. }
  336. if (enable)
  337. tilcdc_set(dev, reg, mask);
  338. else
  339. tilcdc_clear(dev, reg, mask);
  340. }
  341. static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
  342. {
  343. enable_vblank(dev, true);
  344. return 0;
  345. }
  346. static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
  347. {
  348. enable_vblank(dev, false);
  349. }
  350. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  351. static const struct {
  352. const char *name;
  353. uint8_t rev;
  354. uint8_t save;
  355. uint32_t reg;
  356. } registers[] = {
  357. #define REG(rev, save, reg) { #reg, rev, save, reg }
  358. /* exists in revision 1: */
  359. REG(1, false, LCDC_PID_REG),
  360. REG(1, true, LCDC_CTRL_REG),
  361. REG(1, false, LCDC_STAT_REG),
  362. REG(1, true, LCDC_RASTER_CTRL_REG),
  363. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  364. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  365. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  366. REG(1, true, LCDC_DMA_CTRL_REG),
  367. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  368. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  369. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  370. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  371. /* new in revision 2: */
  372. REG(2, false, LCDC_RAW_STAT_REG),
  373. REG(2, false, LCDC_MASKED_STAT_REG),
  374. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  375. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  376. REG(2, false, LCDC_END_OF_INT_IND_REG),
  377. REG(2, true, LCDC_CLK_ENABLE_REG),
  378. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  379. #undef REG
  380. };
  381. #endif
  382. #ifdef CONFIG_DEBUG_FS
  383. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  384. {
  385. struct drm_info_node *node = (struct drm_info_node *) m->private;
  386. struct drm_device *dev = node->minor->dev;
  387. struct tilcdc_drm_private *priv = dev->dev_private;
  388. unsigned i;
  389. pm_runtime_get_sync(dev->dev);
  390. seq_printf(m, "revision: %d\n", priv->rev);
  391. for (i = 0; i < ARRAY_SIZE(registers); i++)
  392. if (priv->rev >= registers[i].rev)
  393. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  394. tilcdc_read(dev, registers[i].reg));
  395. pm_runtime_put_sync(dev->dev);
  396. return 0;
  397. }
  398. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  399. {
  400. struct drm_info_node *node = (struct drm_info_node *) m->private;
  401. struct drm_device *dev = node->minor->dev;
  402. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  403. }
  404. static struct drm_info_list tilcdc_debugfs_list[] = {
  405. { "regs", tilcdc_regs_show, 0 },
  406. { "mm", tilcdc_mm_show, 0 },
  407. { "fb", drm_fb_cma_debugfs_show, 0 },
  408. };
  409. static int tilcdc_debugfs_init(struct drm_minor *minor)
  410. {
  411. struct drm_device *dev = minor->dev;
  412. struct tilcdc_module *mod;
  413. int ret;
  414. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  415. ARRAY_SIZE(tilcdc_debugfs_list),
  416. minor->debugfs_root, minor);
  417. list_for_each_entry(mod, &module_list, list)
  418. if (mod->funcs->debugfs_init)
  419. mod->funcs->debugfs_init(mod, minor);
  420. if (ret) {
  421. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  422. return ret;
  423. }
  424. return ret;
  425. }
  426. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  427. {
  428. struct tilcdc_module *mod;
  429. drm_debugfs_remove_files(tilcdc_debugfs_list,
  430. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  431. list_for_each_entry(mod, &module_list, list)
  432. if (mod->funcs->debugfs_cleanup)
  433. mod->funcs->debugfs_cleanup(mod, minor);
  434. }
  435. #endif
  436. static const struct file_operations fops = {
  437. .owner = THIS_MODULE,
  438. .open = drm_open,
  439. .release = drm_release,
  440. .unlocked_ioctl = drm_ioctl,
  441. #ifdef CONFIG_COMPAT
  442. .compat_ioctl = drm_compat_ioctl,
  443. #endif
  444. .poll = drm_poll,
  445. .read = drm_read,
  446. .llseek = no_llseek,
  447. .mmap = drm_gem_cma_mmap,
  448. };
  449. static struct drm_driver tilcdc_driver = {
  450. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  451. .load = tilcdc_load,
  452. .unload = tilcdc_unload,
  453. .preclose = tilcdc_preclose,
  454. .lastclose = tilcdc_lastclose,
  455. .set_busid = drm_platform_set_busid,
  456. .irq_handler = tilcdc_irq,
  457. .irq_preinstall = tilcdc_irq_preinstall,
  458. .irq_postinstall = tilcdc_irq_postinstall,
  459. .irq_uninstall = tilcdc_irq_uninstall,
  460. .get_vblank_counter = drm_vblank_no_hw_counter,
  461. .enable_vblank = tilcdc_enable_vblank,
  462. .disable_vblank = tilcdc_disable_vblank,
  463. .gem_free_object = drm_gem_cma_free_object,
  464. .gem_vm_ops = &drm_gem_cma_vm_ops,
  465. .dumb_create = drm_gem_cma_dumb_create,
  466. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  467. .dumb_destroy = drm_gem_dumb_destroy,
  468. #ifdef CONFIG_DEBUG_FS
  469. .debugfs_init = tilcdc_debugfs_init,
  470. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  471. #endif
  472. .fops = &fops,
  473. .name = "tilcdc",
  474. .desc = "TI LCD Controller DRM",
  475. .date = "20121205",
  476. .major = 1,
  477. .minor = 0,
  478. };
  479. /*
  480. * Power management:
  481. */
  482. #ifdef CONFIG_PM_SLEEP
  483. static int tilcdc_pm_suspend(struct device *dev)
  484. {
  485. struct drm_device *ddev = dev_get_drvdata(dev);
  486. struct tilcdc_drm_private *priv = ddev->dev_private;
  487. unsigned i, n = 0;
  488. drm_kms_helper_poll_disable(ddev);
  489. /* Save register state: */
  490. for (i = 0; i < ARRAY_SIZE(registers); i++)
  491. if (registers[i].save && (priv->rev >= registers[i].rev))
  492. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  493. return 0;
  494. }
  495. static int tilcdc_pm_resume(struct device *dev)
  496. {
  497. struct drm_device *ddev = dev_get_drvdata(dev);
  498. struct tilcdc_drm_private *priv = ddev->dev_private;
  499. unsigned i, n = 0;
  500. /* Restore register state: */
  501. for (i = 0; i < ARRAY_SIZE(registers); i++)
  502. if (registers[i].save && (priv->rev >= registers[i].rev))
  503. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  504. drm_kms_helper_poll_enable(ddev);
  505. return 0;
  506. }
  507. #endif
  508. static const struct dev_pm_ops tilcdc_pm_ops = {
  509. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  510. };
  511. /*
  512. * Platform driver:
  513. */
  514. static int tilcdc_bind(struct device *dev)
  515. {
  516. return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
  517. }
  518. static void tilcdc_unbind(struct device *dev)
  519. {
  520. drm_put_dev(dev_get_drvdata(dev));
  521. }
  522. static const struct component_master_ops tilcdc_comp_ops = {
  523. .bind = tilcdc_bind,
  524. .unbind = tilcdc_unbind,
  525. };
  526. static int tilcdc_pdev_probe(struct platform_device *pdev)
  527. {
  528. struct component_match *match = NULL;
  529. int ret;
  530. /* bail out early if no DT data: */
  531. if (!pdev->dev.of_node) {
  532. dev_err(&pdev->dev, "device-tree data is missing\n");
  533. return -ENXIO;
  534. }
  535. ret = tilcdc_get_external_components(&pdev->dev, &match);
  536. if (ret < 0)
  537. return ret;
  538. else if (ret == 0)
  539. return drm_platform_init(&tilcdc_driver, pdev);
  540. else
  541. return component_master_add_with_match(&pdev->dev,
  542. &tilcdc_comp_ops,
  543. match);
  544. }
  545. static int tilcdc_pdev_remove(struct platform_device *pdev)
  546. {
  547. struct drm_device *ddev = dev_get_drvdata(&pdev->dev);
  548. struct tilcdc_drm_private *priv = ddev->dev_private;
  549. /* Check if a subcomponent has already triggered the unloading. */
  550. if (!priv)
  551. return 0;
  552. if (priv->is_componentized)
  553. component_master_del(&pdev->dev, &tilcdc_comp_ops);
  554. else
  555. drm_put_dev(platform_get_drvdata(pdev));
  556. return 0;
  557. }
  558. static struct of_device_id tilcdc_of_match[] = {
  559. { .compatible = "ti,am33xx-tilcdc", },
  560. { },
  561. };
  562. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  563. static struct platform_driver tilcdc_platform_driver = {
  564. .probe = tilcdc_pdev_probe,
  565. .remove = tilcdc_pdev_remove,
  566. .driver = {
  567. .name = "tilcdc",
  568. .pm = &tilcdc_pm_ops,
  569. .of_match_table = tilcdc_of_match,
  570. },
  571. };
  572. static int __init tilcdc_drm_init(void)
  573. {
  574. DBG("init");
  575. tilcdc_tfp410_init();
  576. tilcdc_panel_init();
  577. return platform_driver_register(&tilcdc_platform_driver);
  578. }
  579. static void __exit tilcdc_drm_fini(void)
  580. {
  581. DBG("fini");
  582. platform_driver_unregister(&tilcdc_platform_driver);
  583. tilcdc_panel_fini();
  584. tilcdc_tfp410_fini();
  585. }
  586. module_init(tilcdc_drm_init);
  587. module_exit(tilcdc_drm_fini);
  588. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  589. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  590. MODULE_LICENSE("GPL");