intr_hw.c 4.1 KB

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  1. /*
  2. * Tegra host1x Interrupt Management
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (c) 2010-2013, NVIDIA Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/io.h>
  22. #include "../intr.h"
  23. #include "../dev.h"
  24. /*
  25. * Sync point threshold interrupt service function
  26. * Handles sync point threshold triggers, in interrupt context
  27. */
  28. static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt)
  29. {
  30. unsigned int id = syncpt->id;
  31. struct host1x *host = syncpt->host;
  32. host1x_sync_writel(host, BIT_MASK(id),
  33. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id)));
  34. host1x_sync_writel(host, BIT_MASK(id),
  35. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id)));
  36. queue_work(host->intr_wq, &syncpt->intr.work);
  37. }
  38. static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
  39. {
  40. struct host1x *host = dev_id;
  41. unsigned long reg;
  42. int i, id;
  43. for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
  44. reg = host1x_sync_readl(host,
  45. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
  46. for_each_set_bit(id, &reg, BITS_PER_LONG) {
  47. struct host1x_syncpt *syncpt =
  48. host->syncpt + (i * BITS_PER_LONG + id);
  49. host1x_intr_syncpt_handle(syncpt);
  50. }
  51. }
  52. return IRQ_HANDLED;
  53. }
  54. static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
  55. {
  56. u32 i;
  57. for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
  58. host1x_sync_writel(host, 0xffffffffu,
  59. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
  60. host1x_sync_writel(host, 0xffffffffu,
  61. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
  62. }
  63. }
  64. static int _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,
  65. void (*syncpt_thresh_work)(struct work_struct *))
  66. {
  67. int i, err;
  68. host1x_hw_intr_disable_all_syncpt_intrs(host);
  69. for (i = 0; i < host->info->nb_pts; i++)
  70. INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work);
  71. err = devm_request_irq(host->dev, host->intr_syncpt_irq,
  72. syncpt_thresh_isr, IRQF_SHARED,
  73. "host1x_syncpt", host);
  74. if (IS_ERR_VALUE(err)) {
  75. WARN_ON(1);
  76. return err;
  77. }
  78. /* disable the ip_busy_timeout. this prevents write drops */
  79. host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
  80. /*
  81. * increase the auto-ack timout to the maximum value. 2d will hang
  82. * otherwise on Tegra2.
  83. */
  84. host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
  85. /* update host clocks per usec */
  86. host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
  87. return 0;
  88. }
  89. static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
  90. u32 id, u32 thresh)
  91. {
  92. host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
  93. }
  94. static void _host1x_intr_enable_syncpt_intr(struct host1x *host, u32 id)
  95. {
  96. host1x_sync_writel(host, BIT_MASK(id),
  97. HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(BIT_WORD(id)));
  98. }
  99. static void _host1x_intr_disable_syncpt_intr(struct host1x *host, u32 id)
  100. {
  101. host1x_sync_writel(host, BIT_MASK(id),
  102. HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id)));
  103. host1x_sync_writel(host, BIT_MASK(id),
  104. HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id)));
  105. }
  106. static int _host1x_free_syncpt_irq(struct host1x *host)
  107. {
  108. devm_free_irq(host->dev, host->intr_syncpt_irq, host);
  109. flush_workqueue(host->intr_wq);
  110. return 0;
  111. }
  112. static const struct host1x_intr_ops host1x_intr_ops = {
  113. .init_host_sync = _host1x_intr_init_host_sync,
  114. .set_syncpt_threshold = _host1x_intr_set_syncpt_threshold,
  115. .enable_syncpt_intr = _host1x_intr_enable_syncpt_intr,
  116. .disable_syncpt_intr = _host1x_intr_disable_syncpt_intr,
  117. .disable_all_syncpt_intrs = _host1x_intr_disable_all_syncpt_intrs,
  118. .free_syncpt_irq = _host1x_free_syncpt_irq,
  119. };