omap_ssi.c 16 KB

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  1. /* OMAP SSI driver.
  2. *
  3. * Copyright (C) 2010 Nokia Corporation. All rights reserved.
  4. * Copyright (C) 2014 Sebastian Reichel <sre@kernel.org>
  5. *
  6. * Contact: Carlos Chinea <carlos.chinea@nokia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. */
  22. #include <linux/compiler.h>
  23. #include <linux/err.h>
  24. #include <linux/ioport.h>
  25. #include <linux/io.h>
  26. #include <linux/gpio.h>
  27. #include <linux/clk.h>
  28. #include <linux/device.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/dmaengine.h>
  32. #include <linux/delay.h>
  33. #include <linux/seq_file.h>
  34. #include <linux/scatterlist.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/spinlock.h>
  37. #include <linux/debugfs.h>
  38. #include <linux/pm_runtime.h>
  39. #include <linux/of_platform.h>
  40. #include <linux/hsi/hsi.h>
  41. #include <linux/idr.h>
  42. #include "omap_ssi_regs.h"
  43. #include "omap_ssi.h"
  44. /* For automatically allocated device IDs */
  45. static DEFINE_IDA(platform_omap_ssi_ida);
  46. #ifdef CONFIG_DEBUG_FS
  47. static int ssi_debug_show(struct seq_file *m, void *p __maybe_unused)
  48. {
  49. struct hsi_controller *ssi = m->private;
  50. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  51. void __iomem *sys = omap_ssi->sys;
  52. pm_runtime_get_sync(ssi->device.parent);
  53. seq_printf(m, "REVISION\t: 0x%08x\n", readl(sys + SSI_REVISION_REG));
  54. seq_printf(m, "SYSCONFIG\t: 0x%08x\n", readl(sys + SSI_SYSCONFIG_REG));
  55. seq_printf(m, "SYSSTATUS\t: 0x%08x\n", readl(sys + SSI_SYSSTATUS_REG));
  56. pm_runtime_put_sync(ssi->device.parent);
  57. return 0;
  58. }
  59. static int ssi_debug_gdd_show(struct seq_file *m, void *p __maybe_unused)
  60. {
  61. struct hsi_controller *ssi = m->private;
  62. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  63. void __iomem *gdd = omap_ssi->gdd;
  64. void __iomem *sys = omap_ssi->sys;
  65. int lch;
  66. pm_runtime_get_sync(ssi->device.parent);
  67. seq_printf(m, "GDD_MPU_STATUS\t: 0x%08x\n",
  68. readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG));
  69. seq_printf(m, "GDD_MPU_ENABLE\t: 0x%08x\n\n",
  70. readl(sys + SSI_GDD_MPU_IRQ_ENABLE_REG));
  71. seq_printf(m, "HW_ID\t\t: 0x%08x\n",
  72. readl(gdd + SSI_GDD_HW_ID_REG));
  73. seq_printf(m, "PPORT_ID\t: 0x%08x\n",
  74. readl(gdd + SSI_GDD_PPORT_ID_REG));
  75. seq_printf(m, "MPORT_ID\t: 0x%08x\n",
  76. readl(gdd + SSI_GDD_MPORT_ID_REG));
  77. seq_printf(m, "TEST\t\t: 0x%08x\n",
  78. readl(gdd + SSI_GDD_TEST_REG));
  79. seq_printf(m, "GCR\t\t: 0x%08x\n",
  80. readl(gdd + SSI_GDD_GCR_REG));
  81. for (lch = 0; lch < SSI_MAX_GDD_LCH; lch++) {
  82. seq_printf(m, "\nGDD LCH %d\n=========\n", lch);
  83. seq_printf(m, "CSDP\t\t: 0x%04x\n",
  84. readw(gdd + SSI_GDD_CSDP_REG(lch)));
  85. seq_printf(m, "CCR\t\t: 0x%04x\n",
  86. readw(gdd + SSI_GDD_CCR_REG(lch)));
  87. seq_printf(m, "CICR\t\t: 0x%04x\n",
  88. readw(gdd + SSI_GDD_CICR_REG(lch)));
  89. seq_printf(m, "CSR\t\t: 0x%04x\n",
  90. readw(gdd + SSI_GDD_CSR_REG(lch)));
  91. seq_printf(m, "CSSA\t\t: 0x%08x\n",
  92. readl(gdd + SSI_GDD_CSSA_REG(lch)));
  93. seq_printf(m, "CDSA\t\t: 0x%08x\n",
  94. readl(gdd + SSI_GDD_CDSA_REG(lch)));
  95. seq_printf(m, "CEN\t\t: 0x%04x\n",
  96. readw(gdd + SSI_GDD_CEN_REG(lch)));
  97. seq_printf(m, "CSAC\t\t: 0x%04x\n",
  98. readw(gdd + SSI_GDD_CSAC_REG(lch)));
  99. seq_printf(m, "CDAC\t\t: 0x%04x\n",
  100. readw(gdd + SSI_GDD_CDAC_REG(lch)));
  101. seq_printf(m, "CLNK_CTRL\t: 0x%04x\n",
  102. readw(gdd + SSI_GDD_CLNK_CTRL_REG(lch)));
  103. }
  104. pm_runtime_put_sync(ssi->device.parent);
  105. return 0;
  106. }
  107. static int ssi_regs_open(struct inode *inode, struct file *file)
  108. {
  109. return single_open(file, ssi_debug_show, inode->i_private);
  110. }
  111. static int ssi_gdd_regs_open(struct inode *inode, struct file *file)
  112. {
  113. return single_open(file, ssi_debug_gdd_show, inode->i_private);
  114. }
  115. static const struct file_operations ssi_regs_fops = {
  116. .open = ssi_regs_open,
  117. .read = seq_read,
  118. .llseek = seq_lseek,
  119. .release = single_release,
  120. };
  121. static const struct file_operations ssi_gdd_regs_fops = {
  122. .open = ssi_gdd_regs_open,
  123. .read = seq_read,
  124. .llseek = seq_lseek,
  125. .release = single_release,
  126. };
  127. static int __init ssi_debug_add_ctrl(struct hsi_controller *ssi)
  128. {
  129. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  130. struct dentry *dir;
  131. /* SSI controller */
  132. omap_ssi->dir = debugfs_create_dir(dev_name(&ssi->device), NULL);
  133. if (!omap_ssi->dir)
  134. return -ENOMEM;
  135. debugfs_create_file("regs", S_IRUGO, omap_ssi->dir, ssi,
  136. &ssi_regs_fops);
  137. /* SSI GDD (DMA) */
  138. dir = debugfs_create_dir("gdd", omap_ssi->dir);
  139. if (!dir)
  140. goto rback;
  141. debugfs_create_file("regs", S_IRUGO, dir, ssi, &ssi_gdd_regs_fops);
  142. return 0;
  143. rback:
  144. debugfs_remove_recursive(omap_ssi->dir);
  145. return -ENOMEM;
  146. }
  147. static void ssi_debug_remove_ctrl(struct hsi_controller *ssi)
  148. {
  149. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  150. debugfs_remove_recursive(omap_ssi->dir);
  151. }
  152. #endif /* CONFIG_DEBUG_FS */
  153. /*
  154. * FIXME: Horrible HACK needed until we remove the useless wakeline test
  155. * in the CMT. To be removed !!!!
  156. */
  157. void ssi_waketest(struct hsi_client *cl, unsigned int enable)
  158. {
  159. struct hsi_port *port = hsi_get_port(cl);
  160. struct omap_ssi_port *omap_port = hsi_port_drvdata(port);
  161. struct hsi_controller *ssi = to_hsi_controller(port->device.parent);
  162. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  163. omap_port->wktest = !!enable;
  164. if (omap_port->wktest) {
  165. pm_runtime_get_sync(ssi->device.parent);
  166. writel_relaxed(SSI_WAKE(0),
  167. omap_ssi->sys + SSI_SET_WAKE_REG(port->num));
  168. } else {
  169. writel_relaxed(SSI_WAKE(0),
  170. omap_ssi->sys + SSI_CLEAR_WAKE_REG(port->num));
  171. pm_runtime_put_sync(ssi->device.parent);
  172. }
  173. }
  174. EXPORT_SYMBOL_GPL(ssi_waketest);
  175. static void ssi_gdd_complete(struct hsi_controller *ssi, unsigned int lch)
  176. {
  177. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  178. struct hsi_msg *msg = omap_ssi->gdd_trn[lch].msg;
  179. struct hsi_port *port = to_hsi_port(msg->cl->device.parent);
  180. struct omap_ssi_port *omap_port = hsi_port_drvdata(port);
  181. unsigned int dir;
  182. u32 csr;
  183. u32 val;
  184. spin_lock(&omap_ssi->lock);
  185. val = readl(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
  186. val &= ~SSI_GDD_LCH(lch);
  187. writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
  188. if (msg->ttype == HSI_MSG_READ) {
  189. dir = DMA_FROM_DEVICE;
  190. val = SSI_DATAAVAILABLE(msg->channel);
  191. pm_runtime_put_sync(ssi->device.parent);
  192. } else {
  193. dir = DMA_TO_DEVICE;
  194. val = SSI_DATAACCEPT(msg->channel);
  195. /* Keep clocks reference for write pio event */
  196. }
  197. dma_unmap_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, dir);
  198. csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch));
  199. omap_ssi->gdd_trn[lch].msg = NULL; /* release GDD lch */
  200. dev_dbg(&port->device, "DMA completed ch %d ttype %d\n",
  201. msg->channel, msg->ttype);
  202. spin_unlock(&omap_ssi->lock);
  203. if (csr & SSI_CSR_TOUR) { /* Timeout error */
  204. msg->status = HSI_STATUS_ERROR;
  205. msg->actual_len = 0;
  206. spin_lock(&omap_port->lock);
  207. list_del(&msg->link); /* Dequeue msg */
  208. spin_unlock(&omap_port->lock);
  209. msg->complete(msg);
  210. return;
  211. }
  212. spin_lock(&omap_port->lock);
  213. val |= readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
  214. writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
  215. spin_unlock(&omap_port->lock);
  216. msg->status = HSI_STATUS_COMPLETED;
  217. msg->actual_len = sg_dma_len(msg->sgt.sgl);
  218. }
  219. static void ssi_gdd_tasklet(unsigned long dev)
  220. {
  221. struct hsi_controller *ssi = (struct hsi_controller *)dev;
  222. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  223. void __iomem *sys = omap_ssi->sys;
  224. unsigned int lch;
  225. u32 status_reg;
  226. pm_runtime_get_sync(ssi->device.parent);
  227. status_reg = readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG);
  228. for (lch = 0; lch < SSI_MAX_GDD_LCH; lch++) {
  229. if (status_reg & SSI_GDD_LCH(lch))
  230. ssi_gdd_complete(ssi, lch);
  231. }
  232. writel_relaxed(status_reg, sys + SSI_GDD_MPU_IRQ_STATUS_REG);
  233. status_reg = readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG);
  234. pm_runtime_put_sync(ssi->device.parent);
  235. if (status_reg)
  236. tasklet_hi_schedule(&omap_ssi->gdd_tasklet);
  237. else
  238. enable_irq(omap_ssi->gdd_irq);
  239. }
  240. static irqreturn_t ssi_gdd_isr(int irq, void *ssi)
  241. {
  242. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  243. tasklet_hi_schedule(&omap_ssi->gdd_tasklet);
  244. disable_irq_nosync(irq);
  245. return IRQ_HANDLED;
  246. }
  247. static unsigned long ssi_get_clk_rate(struct hsi_controller *ssi)
  248. {
  249. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  250. unsigned long rate = clk_get_rate(omap_ssi->fck);
  251. return rate;
  252. }
  253. static int __init ssi_get_iomem(struct platform_device *pd,
  254. const char *name, void __iomem **pbase, dma_addr_t *phy)
  255. {
  256. struct resource *mem;
  257. void __iomem *base;
  258. struct hsi_controller *ssi = platform_get_drvdata(pd);
  259. mem = platform_get_resource_byname(pd, IORESOURCE_MEM, name);
  260. base = devm_ioremap_resource(&ssi->device, mem);
  261. if (IS_ERR(base))
  262. return PTR_ERR(base);
  263. *pbase = base;
  264. if (phy)
  265. *phy = mem->start;
  266. return 0;
  267. }
  268. static int __init ssi_add_controller(struct hsi_controller *ssi,
  269. struct platform_device *pd)
  270. {
  271. struct omap_ssi_controller *omap_ssi;
  272. int err;
  273. omap_ssi = devm_kzalloc(&ssi->device, sizeof(*omap_ssi), GFP_KERNEL);
  274. if (!omap_ssi) {
  275. dev_err(&pd->dev, "not enough memory for omap ssi\n");
  276. return -ENOMEM;
  277. }
  278. ssi->id = ida_simple_get(&platform_omap_ssi_ida, 0, 0, GFP_KERNEL);
  279. if (ssi->id < 0) {
  280. err = ssi->id;
  281. goto out_err;
  282. }
  283. ssi->owner = THIS_MODULE;
  284. ssi->device.parent = &pd->dev;
  285. dev_set_name(&ssi->device, "ssi%d", ssi->id);
  286. hsi_controller_set_drvdata(ssi, omap_ssi);
  287. omap_ssi->dev = &ssi->device;
  288. err = ssi_get_iomem(pd, "sys", &omap_ssi->sys, NULL);
  289. if (err < 0)
  290. goto out_err;
  291. err = ssi_get_iomem(pd, "gdd", &omap_ssi->gdd, NULL);
  292. if (err < 0)
  293. goto out_err;
  294. err = platform_get_irq_byname(pd, "gdd_mpu");
  295. if (err < 0) {
  296. dev_err(&pd->dev, "GDD IRQ resource missing\n");
  297. goto out_err;
  298. }
  299. omap_ssi->gdd_irq = err;
  300. tasklet_init(&omap_ssi->gdd_tasklet, ssi_gdd_tasklet,
  301. (unsigned long)ssi);
  302. err = devm_request_irq(&ssi->device, omap_ssi->gdd_irq, ssi_gdd_isr,
  303. 0, "gdd_mpu", ssi);
  304. if (err < 0) {
  305. dev_err(&ssi->device, "Request GDD IRQ %d failed (%d)",
  306. omap_ssi->gdd_irq, err);
  307. goto out_err;
  308. }
  309. omap_ssi->port = devm_kzalloc(&ssi->device,
  310. sizeof(struct omap_ssi_port *) * ssi->num_ports, GFP_KERNEL);
  311. if (!omap_ssi->port) {
  312. err = -ENOMEM;
  313. goto out_err;
  314. }
  315. omap_ssi->fck = devm_clk_get(&ssi->device, "ssi_ssr_fck");
  316. if (IS_ERR(omap_ssi->fck)) {
  317. dev_err(&pd->dev, "Could not acquire clock \"ssi_ssr_fck\": %li\n",
  318. PTR_ERR(omap_ssi->fck));
  319. err = -ENODEV;
  320. goto out_err;
  321. }
  322. /* TODO: find register, which can be used to detect context loss */
  323. omap_ssi->get_loss = NULL;
  324. omap_ssi->max_speed = UINT_MAX;
  325. spin_lock_init(&omap_ssi->lock);
  326. err = hsi_register_controller(ssi);
  327. if (err < 0)
  328. goto out_err;
  329. return 0;
  330. out_err:
  331. ida_simple_remove(&platform_omap_ssi_ida, ssi->id);
  332. return err;
  333. }
  334. static int __init ssi_hw_init(struct hsi_controller *ssi)
  335. {
  336. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  337. unsigned int i;
  338. u32 val;
  339. int err;
  340. err = pm_runtime_get_sync(ssi->device.parent);
  341. if (err < 0) {
  342. dev_err(&ssi->device, "runtime PM failed %d\n", err);
  343. return err;
  344. }
  345. /* Reseting SSI controller */
  346. writel_relaxed(SSI_SOFTRESET, omap_ssi->sys + SSI_SYSCONFIG_REG);
  347. val = readl(omap_ssi->sys + SSI_SYSSTATUS_REG);
  348. for (i = 0; ((i < 20) && !(val & SSI_RESETDONE)); i++) {
  349. msleep(20);
  350. val = readl(omap_ssi->sys + SSI_SYSSTATUS_REG);
  351. }
  352. if (!(val & SSI_RESETDONE)) {
  353. dev_err(&ssi->device, "SSI HW reset failed\n");
  354. pm_runtime_put_sync(ssi->device.parent);
  355. return -EIO;
  356. }
  357. /* Reseting GDD */
  358. writel_relaxed(SSI_SWRESET, omap_ssi->gdd + SSI_GDD_GRST_REG);
  359. /* Get FCK rate in KHz */
  360. omap_ssi->fck_rate = DIV_ROUND_CLOSEST(ssi_get_clk_rate(ssi), 1000);
  361. dev_dbg(&ssi->device, "SSI fck rate %lu KHz\n", omap_ssi->fck_rate);
  362. /* Set default PM settings */
  363. val = SSI_AUTOIDLE | SSI_SIDLEMODE_SMART | SSI_MIDLEMODE_SMART;
  364. writel_relaxed(val, omap_ssi->sys + SSI_SYSCONFIG_REG);
  365. omap_ssi->sysconfig = val;
  366. writel_relaxed(SSI_CLK_AUTOGATING_ON, omap_ssi->sys + SSI_GDD_GCR_REG);
  367. omap_ssi->gdd_gcr = SSI_CLK_AUTOGATING_ON;
  368. pm_runtime_put_sync(ssi->device.parent);
  369. return 0;
  370. }
  371. static void ssi_remove_controller(struct hsi_controller *ssi)
  372. {
  373. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  374. int id = ssi->id;
  375. tasklet_kill(&omap_ssi->gdd_tasklet);
  376. hsi_unregister_controller(ssi);
  377. ida_simple_remove(&platform_omap_ssi_ida, id);
  378. }
  379. static inline int ssi_of_get_available_ports_count(const struct device_node *np)
  380. {
  381. struct device_node *child;
  382. int num = 0;
  383. for_each_available_child_of_node(np, child)
  384. if (of_device_is_compatible(child, "ti,omap3-ssi-port"))
  385. num++;
  386. return num;
  387. }
  388. static int ssi_remove_ports(struct device *dev, void *c)
  389. {
  390. struct platform_device *pdev = to_platform_device(dev);
  391. of_device_unregister(pdev);
  392. return 0;
  393. }
  394. static int __init ssi_probe(struct platform_device *pd)
  395. {
  396. struct platform_device *childpdev;
  397. struct device_node *np = pd->dev.of_node;
  398. struct device_node *child;
  399. struct hsi_controller *ssi;
  400. int err;
  401. int num_ports;
  402. if (!np) {
  403. dev_err(&pd->dev, "missing device tree data\n");
  404. return -EINVAL;
  405. }
  406. num_ports = ssi_of_get_available_ports_count(np);
  407. ssi = hsi_alloc_controller(num_ports, GFP_KERNEL);
  408. if (!ssi) {
  409. dev_err(&pd->dev, "No memory for controller\n");
  410. return -ENOMEM;
  411. }
  412. platform_set_drvdata(pd, ssi);
  413. err = ssi_add_controller(ssi, pd);
  414. if (err < 0)
  415. goto out1;
  416. pm_runtime_irq_safe(&pd->dev);
  417. pm_runtime_enable(&pd->dev);
  418. err = ssi_hw_init(ssi);
  419. if (err < 0)
  420. goto out2;
  421. #ifdef CONFIG_DEBUG_FS
  422. err = ssi_debug_add_ctrl(ssi);
  423. if (err < 0)
  424. goto out2;
  425. #endif
  426. for_each_available_child_of_node(np, child) {
  427. if (!of_device_is_compatible(child, "ti,omap3-ssi-port"))
  428. continue;
  429. childpdev = of_platform_device_create(child, NULL, &pd->dev);
  430. if (!childpdev) {
  431. err = -ENODEV;
  432. dev_err(&pd->dev, "failed to create ssi controller port\n");
  433. goto out3;
  434. }
  435. }
  436. dev_info(&pd->dev, "ssi controller %d initialized (%d ports)!\n",
  437. ssi->id, num_ports);
  438. return err;
  439. out3:
  440. device_for_each_child(&pd->dev, NULL, ssi_remove_ports);
  441. out2:
  442. ssi_remove_controller(ssi);
  443. out1:
  444. platform_set_drvdata(pd, NULL);
  445. pm_runtime_disable(&pd->dev);
  446. return err;
  447. }
  448. static int __exit ssi_remove(struct platform_device *pd)
  449. {
  450. struct hsi_controller *ssi = platform_get_drvdata(pd);
  451. #ifdef CONFIG_DEBUG_FS
  452. ssi_debug_remove_ctrl(ssi);
  453. #endif
  454. ssi_remove_controller(ssi);
  455. platform_set_drvdata(pd, NULL);
  456. pm_runtime_disable(&pd->dev);
  457. /* cleanup of of_platform_populate() call */
  458. device_for_each_child(&pd->dev, NULL, ssi_remove_ports);
  459. return 0;
  460. }
  461. #ifdef CONFIG_PM
  462. static int omap_ssi_runtime_suspend(struct device *dev)
  463. {
  464. struct hsi_controller *ssi = dev_get_drvdata(dev);
  465. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  466. dev_dbg(dev, "runtime suspend!\n");
  467. if (omap_ssi->get_loss)
  468. omap_ssi->loss_count =
  469. omap_ssi->get_loss(ssi->device.parent);
  470. return 0;
  471. }
  472. static int omap_ssi_runtime_resume(struct device *dev)
  473. {
  474. struct hsi_controller *ssi = dev_get_drvdata(dev);
  475. struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
  476. dev_dbg(dev, "runtime resume!\n");
  477. if ((omap_ssi->get_loss) && (omap_ssi->loss_count ==
  478. omap_ssi->get_loss(ssi->device.parent)))
  479. return 0;
  480. writel_relaxed(omap_ssi->gdd_gcr, omap_ssi->gdd + SSI_GDD_GCR_REG);
  481. return 0;
  482. }
  483. static const struct dev_pm_ops omap_ssi_pm_ops = {
  484. SET_RUNTIME_PM_OPS(omap_ssi_runtime_suspend, omap_ssi_runtime_resume,
  485. NULL)
  486. };
  487. #define DEV_PM_OPS (&omap_ssi_pm_ops)
  488. #else
  489. #define DEV_PM_OPS NULL
  490. #endif
  491. #ifdef CONFIG_OF
  492. static const struct of_device_id omap_ssi_of_match[] = {
  493. { .compatible = "ti,omap3-ssi", },
  494. {},
  495. };
  496. MODULE_DEVICE_TABLE(of, omap_ssi_of_match);
  497. #else
  498. #define omap_ssi_of_match NULL
  499. #endif
  500. static struct platform_driver ssi_pdriver = {
  501. .remove = __exit_p(ssi_remove),
  502. .driver = {
  503. .name = "omap_ssi",
  504. .pm = DEV_PM_OPS,
  505. .of_match_table = omap_ssi_of_match,
  506. },
  507. };
  508. module_platform_driver_probe(ssi_pdriver, ssi_probe);
  509. MODULE_ALIAS("platform:omap_ssi");
  510. MODULE_AUTHOR("Carlos Chinea <carlos.chinea@nokia.com>");
  511. MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
  512. MODULE_DESCRIPTION("Synchronous Serial Interface Driver");
  513. MODULE_LICENSE("GPL v2");